MachineVerifier: Move verification of G_* instructions to function

llvm-svn: 353111

GlobalISel: Verify memory size for load/store

llvm-svn: 352578

GlobalISel: Verify pointer casts

Not sure if the old AArch64 tests should be just
deleted or not.

llvm-svn: 352562

GlobalISel: Verify load/store has a pointer input

I expected this to be automatically verified, but it seems
nothing uses that the type index was declared as a "ptype"

llvm-svn: 352319

Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""

I reverted it originally due to a bot failing. The underlying bug has been fixed
as of r352311.

llvm-svn: 352312

GlobalISel: Disallow vectors for G_CONSTANT/G_FCONSTANT

llvm-svn: 351853

GlobalISel: Fix out of bounds crashes in verifier

llvm-svn: 351769

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the ne

Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636

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Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"

This new assertion triggered on the AArch64 GlobalISel bots. Reverting while it's being investigated.

llvm-svn: 351617

GlobalISel: Verify G_BITCAST

llvm-svn: 351594

GlobalISel: Verify G_ICMP/G_FCMP vector types

llvm-svn: 351591

GlobalISel: Verify g_zextload and g_sextload

llvm-svn: 351584

[NFC] fix trivial typos in comments

llvm-svn: 350690

[MachineVerifier] Include offending register in allocatable live-in error msg.

This patch adds a convenience report() method for physical registers and
uses it to print the offending register with t

[MachineVerifier] Include offending register in allocatable live-in error msg.

This patch adds a convenience report() method for physical registers and
uses it to print the offending register with the 'MBB has allocatable
live-in' error.

Reviewers: MatzeB, rtereshin, dsanders

Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D55946

llvm-svn: 350630

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[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.

This patch restricts the capability of G_MERGE_VALUES, and uses the new
G_BUILD_VECTOR and G_CONCAT_VECTORS opcodes inst

[GlobalISel] Restrict G_MERGE_VALUES capability and replace with new opcodes.

This patch restricts the capability of G_MERGE_VALUES, and uses the new
G_BUILD_VECTOR and G_CONCAT_VECTORS opcodes instead in the appropriate places.

This patch also includes AArch64 support for selecting G_BUILD_VECTOR of <4 x s32>
and <2 x s64> vectors.

Differential Revisions: https://reviews.llvm.org/D53629

llvm-svn: 348788

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[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes.

These opcodes are intended to subsume some of the capability of G_MERGE_VALUES,
as it was too powerful and th

[GlobalISel] Introduce G_BUILD_VECTOR, G_BUILD_VECTOR_TRUNC and G_CONCAT_VECTOR opcodes.

These opcodes are intended to subsume some of the capability of G_MERGE_VALUES,
as it was too powerful and thus complex to add deal with throughout the GISel
pipeline.

G_BUILD_VECTOR creates a vector value from a sequence of uniformly typed
scalar values. G_BUILD_VECTOR_TRUNC is a special opcode for handling scalar
operands which are larger than the destination vector element type, and
therefore does an implicit truncate.

G_CONCAT_VECTOR creates a vector by concatenating smaller, uniformly typed,
vectors together.

These will be used in a subsequent commit. This commit just adds the initial
infrastructure.

Differential Revision: https://reviews.llvm.org/D53594

llvm-svn: 348430

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Fix typo in verifier error message

llvm-svn: 345083

[machineverifier] Detect PHI's that are preceeded by non-PHI's

If present, PHI nodes must appear before non-PHI nodes in a basic block. The
register allocator relies on this and will fail to elimina

[machineverifier] Detect PHI's that are preceeded by non-PHI's

If present, PHI nodes must appear before non-PHI nodes in a basic block. The
register allocator relies on this and will fail to eliminate PHI's that do not
meet this requirement.

llvm-svn: 343731

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[globalisel][verifier] Run the MachineVerifier from IRTranslator onwards

-verify-machineinstrs inserts the MachineVerifier after every MachineInstr-based
pass. However, GlobalISel creates MachineIns

[globalisel][verifier] Run the MachineVerifier from IRTranslator onwards

-verify-machineinstrs inserts the MachineVerifier after every MachineInstr-based
pass. However, GlobalISel creates MachineInstr-based passes earlier than DAGISel
and the corresponding verifiers are not being added. This patch fixes that.

If GlobalISel triggers the fallback path then the MIR can be left in a bad
state that is going to be cleared by ResetMachineFunctions. In this situation
verifying between GlobalISel passes will prevent the fallback path from
recovering from this. As a result, we bail out of verifying a function if the
FailedISel attribute is present.

llvm-svn: 343613

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[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs

Summary:
Consider an instruction that has multiple defs of the same
vreg, but defining different subregs:
%7.sub1:rc, dead %7.

[MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defs

Summary:
Consider an instruction that has multiple defs of the same
vreg, but defining different subregs:
%7.sub1:rc, dead %7.sub2:rc = inst

Calling checkLivenessAtDef for the live interval associated
with %7 incorrectly reported "live range continues after a
dead def". The live range for %7 has a dead def at the slot
index for "inst" even if the live range continues (given that
there are later uses of %7.sub1).

This patch adjusts MachineVerifier::checkLivenessAtDef
to allow dead subregister definitions, unless we are checking
a subrange (when tracking subregister liveness).

A limitation is that we do not detect the situation when the
live range continues past an instruction that defines the
full virtual register by multiple dead subreg defines.

I also removed some dead code related to physical register
in checkLivenessAtDef. Wwe only call that method for virtual
registers, so I added an assertion instead.

Reviewers: kparzysz

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D52237

llvm-svn: 342618

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MachineVerifier: Fix assert on implicit virtreg use

If the liveness of a physical register was invalid, this
was attempting to iterate the subregisters of all register
uses of the instruction, which

MachineVerifier: Fix assert on implicit virtreg use

If the liveness of a physical register was invalid, this
was attempting to iterate the subregisters of all register
uses of the instruction, which would assert when it
encountered an implicit virtual register operand.

llvm-svn: 340763

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[MachineVerifier] Check if predecessor is jointly dominated by undefs

Each use of a value should be jointly dominated by the union of defs and
undefs. It can happen that it will only be jointly domi

[MachineVerifier] Check if predecessor is jointly dominated by undefs

Each use of a value should be jointly dominated by the union of defs and
undefs. It can happen that it will only be jointly dominated by undefs,
and that is still legal. Make sure that the verifier is aware of that.

llvm-svn: 339924

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Remove trailing space

sed -Ei 's/[[:space:]]+$//' include/**/*.{def,h,td} lib/**/*.{cpp,h}

llvm-svn: 338293

[CodeGen] Fix inconsistent declaration parameter name

llvm-svn: 337200

[DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property

Summary:
In some cases, these operands lacked the IsDebug property, which is meant to signal that
they should not affect c

[DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug property

Summary:
In some cases, these operands lacked the IsDebug property, which is meant to signal that
they should not affect codegen. This patch adds a check for this property in the
MachineVerifier and adds it where it was missing.

This includes refactorings to use MachineInstrBuilder construction functions instead of
manually setting up the intrinsic everywhere.

Patch by: JesperAntonsson

Reviewers: aprantl, rnk, echristo, javed.absar

Reviewed By: aprantl

Subscribers: qcolombet, sdardis, nemanjai, JDevlieghere, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D48319

llvm-svn: 335214

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