[GlobalISel] Catching inconsistencies in load memory, result, and range metadata type (#121247)

This is a fix for:
https://github.com/llvm/llvm-project/issues/97290
Please let me know if that is t

[GlobalISel] Catching inconsistencies in load memory, result, and range metadata type (#121247)

This is a fix for:
https://github.com/llvm/llvm-project/issues/97290
Please let me know if that is the right way to address the issue. Thank
you!

---------

Co-authored-by: Renat Idrisov <parsifal-47@users.noreply.github.com>
Co-authored-by: Matt Arsenault <arsenm2@gmail.com>

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[CodeGen] Introduce a VirtRegOrUnit class to hold virtual reg or physical reg unit. NFC (#123768)

LiveIntervals and MachineVerifier were previously using Register to
store this, but reg units are d

[CodeGen] Introduce a VirtRegOrUnit class to hold virtual reg or physical reg unit. NFC (#123768)

LiveIntervals and MachineVerifier were previously using Register to
store this, but reg units are different than physical registers. One
important difference is that 0 is a valid reg unit number, but it is not
a valid phyiscal register.

This patch introduces a new VirtRegOrUnit class that is distinct from
Register. It can be be converted to/from a virtual Register or a
MCRegUnit. I've made all conversions explicit and used assertions to
check the validity.

I also fixed a place in MachineVerifier that was ignoring reg unit 0.

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[CodeGen] Use MCRegister instead of MCPhysReg in RegisterMaskPair. NFC (#123688)

Update some other places to avoid implicit conversions this introduces,
but I probably missed some.

MachineVerifier: Check stack protector is top-most in frame (#122635)

Mitigate against potential bugs that might place it elsewhere and render
the mechanism useless.

Revert 86b1b0671cafd "MachineVerifier: Check stack protector is top-most in frame" (#122444)

Reverts llvm/llvm-project#121481

This is causing build failures on EXPENSIVE_CHECKS builds:
https://l

Revert 86b1b0671cafd "MachineVerifier: Check stack protector is top-most in frame" (#122444)

Reverts llvm/llvm-project#121481

This is causing build failures on EXPENSIVE_CHECKS builds:
https://lab.llvm.org/buildbot/#/builders/187/builds/3653
https://lab.llvm.org/buildbot/#/builders/16/builds/11758

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MachineVerifier: Check stack protector is top-most in frame (#121481)

Somewhat paranoid, but mitigates potential bugs in the future that might
place it elsewhere and render the mechanism useless.

[GISel] Improve MachineVerifier for G_SCMP/UCMP. (#120017)

-Ensure destination type is at least 2 bits.
-Remove unnecessary check that both sources are the same type. The
verifier already handles

[GISel] Improve MachineVerifier for G_SCMP/UCMP. (#120017)

-Ensure destination type is at least 2 bits.
-Remove unnecessary check that both sources are the same type. The
verifier already handles this generically.

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[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. (#120014)

These are declared to use a single type index for all operands in
GenericOpcodes.td and the verifier knows how to chec

[GISel] Remove unnecessary MachineVerifier checks for G_ABDS/G_ABDU. (#120014)

These are declared to use a single type index for all operands in
GenericOpcodes.td and the verifier knows how to check that all operands
with the same type index match.

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[CodeGen][NewPM] Port LiveStacks analysis to NPM (#118778)

[GlobalISel] Add G_ABDS and G_ABDU instructions (#118122)

The DAG has the same instructions: the signed and unsigned absolute
difference of it's input. For AArch64, they map to uabd and sabd for
N

[GlobalISel] Add G_ABDS and G_ABDU instructions (#118122)

The DAG has the same instructions: the signed and unsigned absolute
difference of it's input. For AArch64, they map to uabd and sabd for
Neon and SVE. The Neon and SVE instructions will require custom
patterns.

They are pseudo opcodes and are not imported by the IRTranslator. We
need combines to create them.

PowerPC, ARM, and AArch64 have native instructions.

/// i.e trunc(abs(sext(Op0) - sext(Op1))) becomes abds(Op0, Op1)
/// or trunc(abs(zext(Op0) - zext(Op1))) becomes abdu(Op0, Op1)

For GlobalISel, we are going to write the combines in MIR patterns.

see:
llvm/test/CodeGen/AArch64/abd-combine.ll

- [ ] combine into abd
- [ ] legalize and add td patterns

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[RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980)

For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the Mac

[RISCV][MachineVerifier] Use RegUnit for register liveness checking (#115980)

For the RISC-V target, V14_V15 are not subregisters of v14m4, even
though they share some registers. Currently, the MachineVerifier reports
an error when checking register liveness for segment load/store
operations.

This patch adds additional register liveness checking, using RegUnit
instead of subregisters, to prevent this error.

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[GlobalISel] Add G_STEP_VECTOR instruction (#115598)

aka llvm.stepvector Intrinsic

[GlobalISel][AArch64] Allow vector ptr to int unmerges (#115228)

Vector pointer -> scalar integer unmerges are already legal. This
loosens the verifier check for vector-of-pointers -> vectors.

[MachineVerifier] Report errors from one thread at a time (#111605)

Create the `ReportedErrors` class to track the number of reported errors
during verification. The class will block reporting erro

[MachineVerifier] Report errors from one thread at a time (#111605)

Create the `ReportedErrors` class to track the number of reported errors
during verification. The class will block reporting errors if some other
thread is currently reporting an error.

I've encountered a case where there were many different verifications
reporting errors at the same time on different threads. This ensures
that we don't start printing the error from one case until we are
completely done printing errors from other cases. Most of the time
`AbortOnError = true` so we usually abort after reporting the first
error.

Depends on https://github.com/llvm/llvm-project/pull/111602.

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[NFC] Format MachineVerifier.cpp to remove extra indentation (#111602)

Many structs in this class have the wrong indentation. To generate this
diff, I touched the first line of each struct and then

[NFC] Format MachineVerifier.cpp to remove extra indentation (#111602)

Many structs in this class have the wrong indentation. To generate this
diff, I touched the first line of each struct and then ran `git
clang-format`. This will make blaming more difficult, but this
autoformatting is difficult to avoid triggering. I think it's best to
push this as one NFC PR.

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llvm-reduce: Don't print verifier failed machine functions (#109673)

This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness o

llvm-reduce: Don't print verifier failed machine functions (#109673)

This produces far too much terminal output, particularly for the
instruction reduction. Since it doesn't consider the liveness of of
the instructions it's deleting, it produces quite a lot of verifier
errors.

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LiveInterval: Make verify functions return bool (#109672)

This will allow the MachineVerifier to check these properties
instead of just asserting

[MachineVerifier] Improve checks for G_INSERT_SUBVECTOR. (#109209)

-Improve messages.
-Remove redundant checks that are handled in generic code.
-Add check that the subvector is smaller than the v

[MachineVerifier] Improve checks for G_INSERT_SUBVECTOR. (#109209)

-Improve messages.
-Remove redundant checks that are handled in generic code.
-Add check that the subvector is smaller than the vector.
-Add checks that subvector is smaller than the vector.

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[MachineVerifier] Improve G_EXTRACT_SUBVECTOR checking (#109202)

Check that the destination of G_EXTRACT_SUBVECTOR is smaller than the
source. Improve wording of error messages.

[MachineVerifier] Fix bug in MachineVerifier for G_INSERT_SUBVECTOR (#109048)

[GISEL] Fix bugs and clarify spec of G_EXTRACT_SUBVECTOR (#108848)

The implementation was missing the fact that `G_EXTRACT_SUBVECTOR`
destination and source vector can be different types.

Also f

[GISEL] Fix bugs and clarify spec of G_EXTRACT_SUBVECTOR (#108848)

The implementation was missing the fact that `G_EXTRACT_SUBVECTOR`
destination and source vector can be different types.

Also fix a bug in the MIR builder for `G_EXTRACT_SUBVECTOR` to generate
the correct opcode.

Clarify the G_EXTRACT_SUBVECTOR specification.

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[GISel][RISCV] Correctly handle scalable vector shuffles of pointer vectors in IRTranslator. (#106580)

llvm.lround: Update verifier to validate support of vector types. (#98950)

Both IRVerifier and Machine Verifier are updated

[GlobalIsel] Add G_SCMP and G_UCMP instructions (#98894)

https://github.com/llvm/llvm-project/pull/83227

[CodeGen][NewPM] Port `MachineVerifier` to new pass manager (#98628)

- Add `MachineVerifierPass`.
- Use complete `MachineVerifierPass` in `VerifyInstrumentation` if
possible.

`LiveStacksAnalysi

[CodeGen][NewPM] Port `MachineVerifier` to new pass manager (#98628)

- Add `MachineVerifierPass`.
- Use complete `MachineVerifierPass` in `VerifyInstrumentation` if
possible.

`LiveStacksAnalysis` will be added in future, all other analyses are
done.

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