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/llvm-project/llvm/test/MC/Disassembler/PowerPC/
H A Dppc64-encoding-vmx.txt4 0x7c 0x43 0x20 0x0e
7 0x7c 0x43 0x20 0x4e
10 0x7c 0x43 0x20 0x8e
13 0x7c 0x43 0x20 0xce
16 0x7c 0x43 0x22 0xce
19 0x7c 0x43 0x21 0x0e
22 0x7c 0x43 0x21 0x4e
25 0x7c 0x43 0x21 0x8e
28 0x7c 0x43 0x21 0xce
31 0x7c 0x43 0x23 0xce
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/
H A Dlegalize-fptoi-rv64-libcall.mir9 liveins: $x10
11 ; CHECK: liveins: $x10
13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
14 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
15 ; CHECK-NEXT: $x10 = COPY [[COPY]](s64)
16 …et-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10
17 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x10
19 ; CHECK-NEXT: $x10 = COPY [[COPY1]](s64)
20 ; CHECK-NEXT: PseudoRET implicit $x10
[all …]
H A Dlegalize-fptoi-rv32-libcall.mir9 liveins: $x10
11 ; CHECK: liveins: $x10
13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
14 ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $x2, implicit $x2
15 ; CHECK-NEXT: $x10 = COPY [[COPY]](s32)
16 …et-flags(riscv-call) &__fixsfsi, csr_ilp32_lp64, implicit-def $x1, implicit $x10, implicit-def $x10
17 ; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $x2, implicit $x2
18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x10
19 ; CHECK-NEXT: $x10 = COPY [[COPY1]](s32)
20 ; CHECK-NEXT: PseudoRET implicit $x10
[all …]
H A Dlegalize-extload-rv64.mir8 bb.0:
9 liveins: $x10
12 ; CHECK: liveins: $x10
14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
15 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
16 ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s64)
17 ; CHECK-NEXT: PseudoRET implicit $x10
18 %0:_(p0) = COPY $x10
[all...]
H A Dlegalize-extload-rv32.mir8 bb.0:
9 liveins: $x10
12 ; CHECK: liveins: $x10
14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
15 ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
16 ; CHECK-NEXT: $x10 = COPY [[ZEXTLOAD]](s32)
17 ; CHECK-NEXT: PseudoRET implicit $x10
18 %0:_(p0) = COPY $x10
19 %2:_(s16) = G_ZEXTLOAD %0(p0) :: (load (s8))
21 $x10 = COPY %3(s32)
[all …]
H A Dlegalize-ptrtoint-rv64.mir7 bb.0:
8 liveins: $x10
11 ; CHECK: liveins: $x10
13 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x10
14 ; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s64) = G_PTRTOINT [[COPY]](p0)
15 ; CHECK-NEXT: $x10 = COPY [[PTRTOINT]](s64)
16 ; CHECK-NEXT: PseudoRET implicit $x10
17 %0:_(p0) = COPY $x10
18 %1:_(s64) = G_PTRTOINT %0(p0)
19 $x10 = COPY %1(s64)
[all …]
H A Dmerge-unmerge-rv32.mir8 bb.0.entry:
9 liveins: $x10
11 ; RV32: liveins: $x10
13 ; RV32-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
14 ; RV32-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s32) = G_ASSERT_ZEXT [[COPY]], 16
15 ; RV32-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16
16 ; RV32-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[ASSERT_ZEXT]], [[C]](s32)
17 ; RV32-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[ASSERT_ZEXT]], [[SHL]]
18 ; RV32-NEXT: $x10 = COPY [[OR]](s32)
19 ; RV32-NEXT: PseudoRET implicit $x10
[all …]
/llvm-project/llvm/test/MC/PowerPC/
H A Dppc64-encoding-vmx.s9 # CHECK-BE: lvebx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x0e]
10 # CHECK-LE: lvebx 2, 3, 4 # encoding: [0x0e,0x20,0x43,0x7c]
12 # CHECK-BE: lvehx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x4e]
13 # CHECK-LE: lvehx 2, 3, 4 # encoding: [0x4e,0x20,0x43,0x7c]
15 # CHECK-BE: lvewx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0x8e]
16 # CHECK-LE: lvewx 2, 3, 4 # encoding: [0x8e,0x20,0x43,0x7c]
18 # CHECK-BE: lvx 2, 3, 4 # encoding: [0x7c,0x43,0x20,0xce]
19 # CHECK-LE: lvx 2, 3, 4 # encoding: [0xce,0x20,0x43,0x7c]
21 # CHECK-BE: lvxl 2, 3, 4 # encoding: [0x7c,0x43,0x22,0xce]
22 # CHECK-LE: lvxl 2, 3, 4 # encoding: [0xce,0x22,0x43,0x7c]
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/
H A Dicmp-rv32.mir10 bb.0.entry:
11 liveins: $x10, $x11
14 ; CHECK: liveins: $x10, $x11
16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
17 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
18 ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]]
19 ; CHECK-NEXT: $x10 = COPY [[SLTU]]
20 ; CHECK-NEXT: PseudoRET implicit $x10
21 %0:gprb(s32) = COPY $x10
23 %2:gprb(s32) = G_ICMP intpred(ult), %0, %1
[all …]
H A Dicmp-rv64.mir10 bb.0.entry:
11 liveins: $x10, $x11
14 ; CHECK: liveins: $x10, $x11
16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
17 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
18 ; CHECK-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY1]]
19 ; CHECK-NEXT: $x10 = COPY [[SLTU]]
20 ; CHECK-NEXT: PseudoRET implicit $x10
21 %0:gprb(s64) = COPY $x10
23 %2:gprb(s64) = G_ICMP intpred(ult), %0, %1
[all …]
H A Dalu-rv64.mir11 bb.0.entry:
12 liveins: $x10, $x11
15 ; RV64I: liveins: $x10, $x11
17 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; RV64I-NEXT: [[SLLW:%[0-9]+]]:gpr = SLLW [[COPY]], [[COPY1]]
20 ; RV64I-NEXT: $x10 = COPY [[SLLW]]
21 ; RV64I-NEXT: PseudoRET implicit $x10
22 %0
[all...]
H A Dalu-rv32.mir11 bb.0.entry:
12 liveins: $x10, $x11
15 ; RV32I: liveins: $x10, $x11
17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
20 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 24
21 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 24
22 ; RV32I-NEXT: $x10
[all...]
H A Dload-rv64.mir11 bb.0:
12 liveins: $x10
15 ; CHECK: liveins: $x10
17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
19 ; CHECK-NEXT: $x10 = COPY [[LBU]]
20 ; CHECK-NEXT: PseudoRET implicit $x10
21 %0
[all...]
H A Dload-rv32.mir11 bb.0:
12 liveins: $x10
15 ; CHECK: liveins: $x10
17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
19 ; CHECK-NEXT: $x10 = COPY [[LBU]]
20 ; CHECK-NEXT: PseudoRET implicit $x10
21 %0
[all...]
H A Dconstant64.mir10 bb.0:
11 liveins: $x10
14 ; CHECK: liveins: $x10
16 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1
17 ; CHECK-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADDI]], 63
18 ; CHECK-NEXT: $x10 = COPY [[SLLI]]
19 ; CHECK-NEXT: PseudoRET implicit $x10
20 %0:gprb(s64) = G_CONSTANT i64 -9223372036854775808
21 $x10 = COPY %0(s6
[all...]
H A Dalu_m-rv64.mir11 bb.0.entry:
12 liveins: $x10, $x11
15 ; RV64I: liveins: $x10, $x11
17 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]]
20 ; RV64I-NEXT: $x10 = COPY [[DIVW]]
21 ; RV64I-NEXT: PseudoRET implicit $x10
22 %0
[all...]
H A Dshift-rv64.mir11 bb.0:
12 liveins: $x10, $x11
15 ; CHECK: liveins: $x10, $x11
17 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
20 ; CHECK-NEXT: $x10 = COPY [[SLL]]
21 ; CHECK-NEXT: PseudoRET implicit $x10
22 %0
[all...]
H A Drotate-rv64.mir13 bb.0:
14 liveins: $x10, $x11
17 ; CHECK: liveins: $x10, $x11
19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
20 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
21 ; CHECK-NEXT: [[ROLW:%[0-9]+]]:gpr = ROLW [[COPY]], [[COPY1]]
22 ; CHECK-NEXT: $x10 = COPY [[ROLW]]
23 ; CHECK-NEXT: PseudoRET implicit $x10
24 %0
[all...]
H A Dshift-rv32.mir12 bb.0:
13 liveins: $x10, $x11
16 ; CHECK: liveins: $x10, $x11
18 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
19 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
20 ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
21 ; CHECK-NEXT: $x10 = COPY [[SLL]]
22 ; CHECK-NEXT: PseudoRET implicit $x10
23 %0:gprb(s32) = COPY $x10
25 %3:gprb(s32) = G_SHL %0, %1
[all …]
/llvm-project/llvm/test/MC/Disassembler/ARM/
H A Darm-vmrs_vmsr.txt8 [0x10,0xfa,0xf1,0xee]
9 [0x10,0xfa,0xf1,0xee]
10 [0x10,0xfa,0xf1,0xee]
11 [0x10,0xaa,0xf1,0xee]
12 [0x10,0x2a,0xf0,0xee]
13 [0x10,0x3a,0xf0,0xee]
14 [0x10,0x4a,0xf7,0xee]
15 [0x10,0x5a,0xf6,0xee]
16 [0x10,0x6a,0xf5,0xee]
17 [0x10,0xda,0xf1,0xee]
[all …]
H A Dthumb-vmrs_vmsr.txt16 [0xf1,0xee,0x10,0xfa]
17 [0xf1,0xee,0x10,0xfa]
18 [0xf1,0xee,0x10,0xfa]
19 [0xf1,0xee,0x10,0xaa]
20 [0xf0,0xee,0x10,0x2a]
21 [0xf0,0xee,0x10,0x3a]
22 [0xf7,0xee,0x10,0x4a]
23 [0xf6,0xee,0x10,0x5a]
24 [0xf5,0xee,0x10,0x6a]
25 [0xf1,0xee,0x10,0xda]
[all …]
/llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/
H A Dalu-rv32.mir11 bb.0.entry:
12 liveins: $x10, $x11
15 ; RV32I: liveins: $x10, $x11
17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
18 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
19 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
20 ; RV32I-NEXT: $x10 = COPY [[ADD]](s32)
21 ; RV32I-NEXT: PseudoRET implicit $x10
22 %0
[all...]
H A Dalu-rv64.mir11 bb.0.entry:
12 liveins: $x10, $x11
15 ; RV64I: liveins: $x10, $x11
17 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(s64) = COPY $x10
18 ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gprb(s64) = COPY $x11
19 ; RV64I-NEXT: [[ADD:%[0-9]+]]:gprb(s64) = G_ADD [[COPY]], [[COPY1]]
20 ; RV64I-NEXT: $x10 = COPY [[ADD]](s64)
21 ; RV64I-NEXT: PseudoRET implicit $x10
22 %0
[all...]
H A Dload-rv64.mir11 bb.0:
12 liveins: $x10
15 ; RV64I: liveins: $x10
17 ; RV64I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
18 ; RV64I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
19 ; RV64I-NEXT: [[ANYEXT:%[0-9]+]]:gprb(s64) = G_ANYEXT [[LOAD]](s32)
20 ; RV64I-NEXT: $x10 = COPY [[ANYEXT]](s64)
21 ; RV64I-NEXT: PseudoRET implicit $x10
22 %0
[all...]
H A Dload-rv32.mir11 bb.0:
12 liveins: $x10
15 ; RV32I: liveins: $x10
17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
18 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8))
19 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32)
20 ; RV32I-NEXT: PseudoRET implicit $x10
21 %0:_(p0) = COPY $x10
[all...]

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