xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv32.mir (revision d78fe84d49b3db675ae4c502ead38ce9e5c2539f) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
3# RUN: | FileCheck -check-prefix=RV32I %s
4
5---
6name:            add_i8_signext
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0.entry:
12    liveins: $x10, $x11
13
14    ; RV32I-LABEL: name: add_i8_signext
15    ; RV32I: liveins: $x10, $x11
16    ; RV32I-NEXT: {{  $}}
17    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
20    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 24
21    ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 24
22    ; RV32I-NEXT: $x10 = COPY [[SRAI]]
23    ; RV32I-NEXT: PseudoRET implicit $x10
24    %0:gprb(s32) = COPY $x10
25    %1:gprb(s32) = COPY $x11
26    %2:gprb(s32) = G_ADD %0, %1
27    %3:gprb(s32) = G_CONSTANT i32 24
28    %4:gprb(s32) = G_SHL %2, %3(s32)
29    %5:gprb(s32) = G_ASHR %4, %3(s32)
30    $x10 = COPY %5(s32)
31    PseudoRET implicit $x10
32
33...
34---
35name:            add_i8_zeroext
36legalized:       true
37regBankSelected: true
38tracksRegLiveness: true
39body:             |
40  bb.0.entry:
41    liveins: $x10, $x11
42
43    ; RV32I-LABEL: name: add_i8_zeroext
44    ; RV32I: liveins: $x10, $x11
45    ; RV32I-NEXT: {{  $}}
46    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
47    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
48    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
49    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[ADD]], 255
50    ; RV32I-NEXT: $x10 = COPY [[ANDI]]
51    ; RV32I-NEXT: PseudoRET implicit $x10
52    %0:gprb(s32) = COPY $x10
53    %1:gprb(s32) = COPY $x11
54    %2:gprb(s32) = G_ADD %0, %1
55    %3:gprb(s32) = G_CONSTANT i32 255
56    %4:gprb(s32) = G_AND %2, %3
57    $x10 = COPY %4(s32)
58    PseudoRET implicit $x10
59
60...
61---
62name:            add_i16_signext
63legalized:       true
64regBankSelected: true
65tracksRegLiveness: true
66body:             |
67  bb.0.entry:
68    liveins: $x10, $x11
69
70    ; RV32I-LABEL: name: add_i16_signext
71    ; RV32I: liveins: $x10, $x11
72    ; RV32I-NEXT: {{  $}}
73    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
74    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
75    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
76    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16
77    ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 16
78    ; RV32I-NEXT: $x10 = COPY [[SRAI]]
79    ; RV32I-NEXT: PseudoRET implicit $x10
80    %0:gprb(s32) = COPY $x10
81    %1:gprb(s32) = COPY $x11
82    %2:gprb(s32) = G_ADD %0, %1
83    %3:gprb(s32) = G_CONSTANT i32 16
84    %4:gprb(s32) = G_SHL %2, %3(s32)
85    %5:gprb(s32) = G_ASHR %4, %3(s32)
86    $x10 = COPY %5(s32)
87    PseudoRET implicit $x10
88
89...
90---
91name:            add_i16_zeroext
92legalized:       true
93regBankSelected: true
94tracksRegLiveness: true
95body:             |
96  bb.0.entry:
97    liveins: $x10, $x11
98
99    ; RV32I-LABEL: name: add_i16_zeroext
100    ; RV32I: liveins: $x10, $x11
101    ; RV32I-NEXT: {{  $}}
102    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
103    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
104    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
105    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16
106    ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 16
107    ; RV32I-NEXT: $x10 = COPY [[SRLI]]
108    ; RV32I-NEXT: PseudoRET implicit $x10
109    %0:gprb(s32) = COPY $x10
110    %1:gprb(s32) = COPY $x11
111    %2:gprb(s32) = G_ADD %0, %1
112    %3:gprb(s32) = G_CONSTANT i32 65535
113    %4:gprb(s32) = G_AND %2, %3
114    $x10 = COPY %4(s32)
115    PseudoRET implicit $x10
116
117...
118---
119name:            add_i32
120legalized:       true
121regBankSelected: true
122tracksRegLiveness: true
123body:             |
124  bb.0.entry:
125    liveins: $x10, $x11
126
127    ; RV32I-LABEL: name: add_i32
128    ; RV32I: liveins: $x10, $x11
129    ; RV32I-NEXT: {{  $}}
130    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
131    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
132    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
133    ; RV32I-NEXT: $x10 = COPY [[ADD]]
134    ; RV32I-NEXT: PseudoRET implicit $x10
135    %0:gprb(s32) = COPY $x10
136    %1:gprb(s32) = COPY $x11
137    %2:gprb(s32) = G_ADD %0, %1
138    $x10 = COPY %2(s32)
139    PseudoRET implicit $x10
140
141...
142---
143name:            addi_i32
144legalized:       true
145regBankSelected: true
146tracksRegLiveness: true
147body:             |
148  bb.0.entry:
149    liveins: $x10
150
151    ; RV32I-LABEL: name: addi_i32
152    ; RV32I: liveins: $x10
153    ; RV32I-NEXT: {{  $}}
154    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
155    ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
156    ; RV32I-NEXT: $x10 = COPY [[ADDI]]
157    ; RV32I-NEXT: PseudoRET implicit $x10
158    %0:gprb(s32) = COPY $x10
159    %1:gprb(s32) = G_CONSTANT i32 1234
160    %2:gprb(s32) = G_ADD %0, %1
161    $x10 = COPY %2(s32)
162    PseudoRET implicit $x10
163
164...
165---
166name:            sub_i32
167legalized:       true
168regBankSelected: true
169tracksRegLiveness: true
170body:             |
171  bb.0.entry:
172    liveins: $x10, $x11
173
174    ; RV32I-LABEL: name: sub_i32
175    ; RV32I: liveins: $x10, $x11
176    ; RV32I-NEXT: {{  $}}
177    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
178    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
179    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
180    ; RV32I-NEXT: $x10 = COPY [[SUB]]
181    ; RV32I-NEXT: PseudoRET implicit $x10
182    %0:gprb(s32) = COPY $x10
183    %1:gprb(s32) = COPY $x11
184    %2:gprb(s32) = G_SUB %0, %1
185    $x10 = COPY %2(s32)
186    PseudoRET implicit $x10
187
188...
189---
190name:            subi_i32
191legalized:       true
192regBankSelected: true
193tracksRegLiveness: true
194body:             |
195  bb.0.entry:
196    liveins: $x10
197
198    ; RV32I-LABEL: name: subi_i32
199    ; RV32I: liveins: $x10
200    ; RV32I-NEXT: {{  $}}
201    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
202    ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1234
203    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[ADDI]]
204    ; RV32I-NEXT: $x10 = COPY [[SUB]]
205    ; RV32I-NEXT: PseudoRET implicit $x10
206    %0:gprb(s32) = COPY $x10
207    %1:gprb(s32) = G_CONSTANT i32 -1234
208    %2:gprb(s32) = G_SUB %0, %1
209    $x10 = COPY %2(s32)
210    PseudoRET implicit $x10
211
212...
213---
214name:            sll_i32
215legalized:       true
216regBankSelected: true
217tracksRegLiveness: true
218body:             |
219  bb.0.entry:
220    liveins: $x10, $x11
221
222    ; RV32I-LABEL: name: sll_i32
223    ; RV32I: liveins: $x10, $x11
224    ; RV32I-NEXT: {{  $}}
225    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
226    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
227    ; RV32I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
228    ; RV32I-NEXT: $x10 = COPY [[SLL]]
229    ; RV32I-NEXT: PseudoRET implicit $x10
230    %0:gprb(s32) = COPY $x10
231    %1:gprb(s32) = COPY $x11
232    %2:gprb(s32) = G_SHL %0, %1
233    $x10 = COPY %2(s32)
234    PseudoRET implicit $x10
235
236...
237---
238name:            slli_i32
239legalized:       true
240regBankSelected: true
241tracksRegLiveness: true
242body:             |
243  bb.0.entry:
244    liveins: $x10
245
246    ; RV32I-LABEL: name: slli_i32
247    ; RV32I: liveins: $x10
248    ; RV32I-NEXT: {{  $}}
249    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
250    ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31
251    ; RV32I-NEXT: $x10 = COPY [[SLLI]]
252    ; RV32I-NEXT: PseudoRET implicit $x10
253    %0:gprb(s32) = COPY $x10
254    %1:gprb(s32) = G_CONSTANT i32 31
255    %2:gprb(s32) = G_SHL %0, %1
256    $x10 = COPY %2(s32)
257    PseudoRET implicit $x10
258
259...
260---
261name:            sra_i32
262legalized:       true
263regBankSelected: true
264tracksRegLiveness: true
265body:             |
266  bb.0.entry:
267    liveins: $x10, $x11
268
269    ; RV32I-LABEL: name: sra_i32
270    ; RV32I: liveins: $x10, $x11
271    ; RV32I-NEXT: {{  $}}
272    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
273    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
274    ; RV32I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]]
275    ; RV32I-NEXT: $x10 = COPY [[SRA]]
276    ; RV32I-NEXT: PseudoRET implicit $x10
277    %0:gprb(s32) = COPY $x10
278    %1:gprb(s32) = COPY $x11
279    %2:gprb(s32) = G_ASHR %0, %1
280    $x10 = COPY %2(s32)
281    PseudoRET implicit $x10
282
283...
284---
285name:            srai_i32
286legalized:       true
287regBankSelected: true
288tracksRegLiveness: true
289body:             |
290  bb.0.entry:
291    liveins: $x10
292
293    ; RV32I-LABEL: name: srai_i32
294    ; RV32I: liveins: $x10
295    ; RV32I-NEXT: {{  $}}
296    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
297    ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 31
298    ; RV32I-NEXT: $x10 = COPY [[SRAI]]
299    ; RV32I-NEXT: PseudoRET implicit $x10
300    %0:gprb(s32) = COPY $x10
301    %1:gprb(s32) = G_CONSTANT i32 31
302    %2:gprb(s32) = G_ASHR %0, %1
303    $x10 = COPY %2(s32)
304    PseudoRET implicit $x10
305
306...
307---
308name:            srl_i32
309legalized:       true
310regBankSelected: true
311tracksRegLiveness: true
312body:             |
313  bb.0.entry:
314    liveins: $x10, $x11
315
316    ; RV32I-LABEL: name: srl_i32
317    ; RV32I: liveins: $x10, $x11
318    ; RV32I-NEXT: {{  $}}
319    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
320    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
321    ; RV32I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]]
322    ; RV32I-NEXT: $x10 = COPY [[SRL]]
323    ; RV32I-NEXT: PseudoRET implicit $x10
324    %0:gprb(s32) = COPY $x10
325    %1:gprb(s32) = COPY $x11
326    %2:gprb(s32) = G_LSHR %0, %1
327    $x10 = COPY %2(s32)
328    PseudoRET implicit $x10
329
330...
331---
332name:            srli_i32
333legalized:       true
334regBankSelected: true
335tracksRegLiveness: true
336body:             |
337  bb.0.entry:
338    liveins: $x10
339
340    ; RV32I-LABEL: name: srli_i32
341    ; RV32I: liveins: $x10
342    ; RV32I-NEXT: {{  $}}
343    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
344    ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 31
345    ; RV32I-NEXT: $x10 = COPY [[SRLI]]
346    ; RV32I-NEXT: PseudoRET implicit $x10
347    %0:gprb(s32) = COPY $x10
348    %1:gprb(s32) = G_CONSTANT i32 31
349    %2:gprb(s32) = G_LSHR %0, %1
350    $x10 = COPY %2(s32)
351    PseudoRET implicit $x10
352
353...
354---
355name:            and_i32
356legalized:       true
357regBankSelected: true
358tracksRegLiveness: true
359body:             |
360  bb.0.entry:
361    liveins: $x10, $x11
362
363    ; RV32I-LABEL: name: and_i32
364    ; RV32I: liveins: $x10, $x11
365    ; RV32I-NEXT: {{  $}}
366    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
367    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
368    ; RV32I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
369    ; RV32I-NEXT: $x10 = COPY [[AND]]
370    ; RV32I-NEXT: PseudoRET implicit $x10
371    %0:gprb(s32) = COPY $x10
372    %1:gprb(s32) = COPY $x11
373    %2:gprb(s32) = G_AND %0, %1
374    $x10 = COPY %2(s32)
375    PseudoRET implicit $x10
376
377...
378---
379name:            andi_i32
380legalized:       true
381regBankSelected: true
382tracksRegLiveness: true
383body:             |
384  bb.0.entry:
385    liveins: $x10
386
387    ; RV32I-LABEL: name: andi_i32
388    ; RV32I: liveins: $x10
389    ; RV32I-NEXT: {{  $}}
390    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
391    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234
392    ; RV32I-NEXT: $x10 = COPY [[ANDI]]
393    ; RV32I-NEXT: PseudoRET implicit $x10
394    %0:gprb(s32) = COPY $x10
395    %1:gprb(s32) = G_CONSTANT i32 1234
396    %2:gprb(s32) = G_AND %0, %1
397    $x10 = COPY %2(s32)
398    PseudoRET implicit $x10
399
400...
401---
402name:            or_i32
403legalized:       true
404regBankSelected: true
405tracksRegLiveness: true
406body:             |
407  bb.0.entry:
408    liveins: $x10, $x11
409
410    ; RV32I-LABEL: name: or_i32
411    ; RV32I: liveins: $x10, $x11
412    ; RV32I-NEXT: {{  $}}
413    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
414    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
415    ; RV32I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
416    ; RV32I-NEXT: $x10 = COPY [[OR]]
417    ; RV32I-NEXT: PseudoRET implicit $x10
418    %0:gprb(s32) = COPY $x10
419    %1:gprb(s32) = COPY $x11
420    %2:gprb(s32) = G_OR %0, %1
421    $x10 = COPY %2(s32)
422    PseudoRET implicit $x10
423
424...
425---
426name:            ori_i32
427legalized:       true
428regBankSelected: true
429tracksRegLiveness: true
430body:             |
431  bb.0.entry:
432    liveins: $x10
433
434    ; RV32I-LABEL: name: ori_i32
435    ; RV32I: liveins: $x10
436    ; RV32I-NEXT: {{  $}}
437    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
438    ; RV32I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234
439    ; RV32I-NEXT: $x10 = COPY [[ORI]]
440    ; RV32I-NEXT: PseudoRET implicit $x10
441    %0:gprb(s32) = COPY $x10
442    %1:gprb(s32) = G_CONSTANT i32 1234
443    %2:gprb(s32) = G_OR %0, %1
444    $x10 = COPY %2(s32)
445    PseudoRET implicit $x10
446
447...
448---
449name:            xor_i32
450legalized:       true
451regBankSelected: true
452tracksRegLiveness: true
453body:             |
454  bb.0.entry:
455    liveins: $x10, $x11
456
457    ; RV32I-LABEL: name: xor_i32
458    ; RV32I: liveins: $x10, $x11
459    ; RV32I-NEXT: {{  $}}
460    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
461    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
462    ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
463    ; RV32I-NEXT: $x10 = COPY [[XOR]]
464    ; RV32I-NEXT: PseudoRET implicit $x10
465    %0:gprb(s32) = COPY $x10
466    %1:gprb(s32) = COPY $x11
467    %2:gprb(s32) = G_XOR %0, %1
468    $x10 = COPY %2(s32)
469    PseudoRET implicit $x10
470
471...
472---
473name:            xori_i32
474legalized:       true
475regBankSelected: true
476tracksRegLiveness: true
477body:             |
478  bb.0.entry:
479    liveins: $x10
480
481    ; RV32I-LABEL: name: xori_i32
482    ; RV32I: liveins: $x10
483    ; RV32I-NEXT: {{  $}}
484    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
485    ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234
486    ; RV32I-NEXT: $x10 = COPY [[XORI]]
487    ; RV32I-NEXT: PseudoRET implicit $x10
488    %0:gprb(s32) = COPY $x10
489    %1:gprb(s32) = G_CONSTANT i32 1234
490    %2:gprb(s32) = G_XOR %0, %1
491    $x10 = COPY %2(s32)
492    PseudoRET implicit $x10
493
494...
495---
496name:            add_i64
497legalized:       true
498regBankSelected: true
499tracksRegLiveness: true
500body:             |
501  bb.0.entry:
502    liveins: $x10, $x11, $x12, $x13
503
504    ; RV32I-LABEL: name: add_i64
505    ; RV32I: liveins: $x10, $x11, $x12, $x13
506    ; RV32I-NEXT: {{  $}}
507    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
508    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
509    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
510    ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
511    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]]
512    ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]]
513    ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]]
514    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
515    ; RV32I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]]
516    ; RV32I-NEXT: $x10 = COPY [[ADD]]
517    ; RV32I-NEXT: $x11 = COPY [[ADD2]]
518    ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
519    %0:gprb(s32) = COPY $x10
520    %1:gprb(s32) = COPY $x11
521    %2:gprb(s32) = COPY $x12
522    %3:gprb(s32) = COPY $x13
523    %4:gprb(s32) = G_ADD %0, %2
524    %5:gprb(s32) = G_ICMP intpred(ult), %4(s32), %2
525    %6:gprb(s32) = G_ADD %1, %3
526    %7:gprb(s32) = G_CONSTANT i32 1
527    %8:gprb(s32) = G_AND %5, %7
528    %9:gprb(s32) = G_ADD %6, %8
529    $x10 = COPY %4(s32)
530    $x11 = COPY %9(s32)
531    PseudoRET implicit $x10, implicit $x11
532
533...
534---
535name:            sub_i64
536legalized:       true
537regBankSelected: true
538tracksRegLiveness: true
539body:             |
540  bb.0.entry:
541    liveins: $x10, $x11, $x12, $x13
542
543    ; RV32I-LABEL: name: sub_i64
544    ; RV32I: liveins: $x10, $x11, $x12, $x13
545    ; RV32I-NEXT: {{  $}}
546    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
547    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
548    ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
549    ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
550    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]]
551    ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]]
552    ; RV32I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]]
553    ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
554    ; RV32I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]]
555    ; RV32I-NEXT: $x10 = COPY [[SUB]]
556    ; RV32I-NEXT: $x11 = COPY [[SUB2]]
557    ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
558    %0:gprb(s32) = COPY $x10
559    %1:gprb(s32) = COPY $x11
560    %2:gprb(s32) = COPY $x12
561    %3:gprb(s32) = COPY $x13
562    %4:gprb(s32) = G_SUB %0, %2
563    %5:gprb(s32) = G_ICMP intpred(ult), %0(s32), %2
564    %6:gprb(s32) = G_SUB %1, %3
565    %7:gprb(s32) = G_CONSTANT i32 1
566    %8:gprb(s32) = G_AND %5, %7
567    %9:gprb(s32) = G_SUB %6, %8
568    $x10 = COPY %4(s32)
569    $x11 = COPY %9(s32)
570    PseudoRET implicit $x10, implicit $x11
571
572...
573