Lines Matching +full:0 +full:x10
11 bb.0.entry:
12 liveins: $x10, $x11
15 ; RV32I: liveins: $x10, $x11
17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
20 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 24
21 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 24
22 ; RV32I-NEXT: $x10 = COPY [[SRAI]]
23 ; RV32I-NEXT: PseudoRET implicit $x10
24 %0:gprb(s32) = COPY $x10
26 %2:gprb(s32) = G_ADD %0, %1
30 $x10 = COPY %5(s32)
31 PseudoRET implicit $x10
40 bb.0.entry:
41 liveins: $x10, $x11
44 ; RV32I: liveins: $x10, $x11
46 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
47 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
48 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
49 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[ADD]], 255
50 ; RV32I-NEXT: $x10 = COPY [[ANDI]]
51 ; RV32I-NEXT: PseudoRET implicit $x10
52 %0:gprb(s32) = COPY $x10
54 %2:gprb(s32) = G_ADD %0, %1
57 $x10 = COPY %4(s32)
58 PseudoRET implicit $x10
67 bb.0.entry:
68 liveins: $x10, $x11
71 ; RV32I: liveins: $x10, $x11
73 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
74 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
75 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
76 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16
77 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[SLLI]], 16
78 ; RV32I-NEXT: $x10 = COPY [[SRAI]]
79 ; RV32I-NEXT: PseudoRET implicit $x10
80 %0:gprb(s32) = COPY $x10
82 %2:gprb(s32) = G_ADD %0, %1
86 $x10 = COPY %5(s32)
87 PseudoRET implicit $x10
96 bb.0.entry:
97 liveins: $x10, $x11
100 ; RV32I: liveins: $x10, $x11
102 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
103 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
104 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
105 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[ADD]], 16
106 ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[SLLI]], 16
107 ; RV32I-NEXT: $x10 = COPY [[SRLI]]
108 ; RV32I-NEXT: PseudoRET implicit $x10
109 %0:gprb(s32) = COPY $x10
111 %2:gprb(s32) = G_ADD %0, %1
114 $x10 = COPY %4(s32)
115 PseudoRET implicit $x10
124 bb.0.entry:
125 liveins: $x10, $x11
128 ; RV32I: liveins: $x10, $x11
130 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
131 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
132 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
133 ; RV32I-NEXT: $x10 = COPY [[ADD]]
134 ; RV32I-NEXT: PseudoRET implicit $x10
135 %0:gprb(s32) = COPY $x10
137 %2:gprb(s32) = G_ADD %0, %1
138 $x10 = COPY %2(s32)
139 PseudoRET implicit $x10
148 bb.0.entry:
149 liveins: $x10
152 ; RV32I: liveins: $x10
154 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
155 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
156 ; RV32I-NEXT: $x10 = COPY [[ADDI]]
157 ; RV32I-NEXT: PseudoRET implicit $x10
158 %0:gprb(s32) = COPY $x10
160 %2:gprb(s32) = G_ADD %0, %1
161 $x10 = COPY %2(s32)
162 PseudoRET implicit $x10
171 bb.0.entry:
172 liveins: $x10, $x11
175 ; RV32I: liveins: $x10, $x11
177 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
178 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
179 ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
180 ; RV32I-NEXT: $x10 = COPY [[SUB]]
181 ; RV32I-NEXT: PseudoRET implicit $x10
182 %0:gprb(s32) = COPY $x10
184 %2:gprb(s32) = G_SUB %0, %1
185 $x10 = COPY %2(s32)
186 PseudoRET implicit $x10
195 bb.0.entry:
196 liveins: $x10
199 ; RV32I: liveins: $x10
201 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
202 ; RV32I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1234
203 ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[ADDI]]
204 ; RV32I-NEXT: $x10 = COPY [[SUB]]
205 ; RV32I-NEXT: PseudoRET implicit $x10
206 %0:gprb(s32) = COPY $x10
208 %2:gprb(s32) = G_SUB %0, %1
209 $x10 = COPY %2(s32)
210 PseudoRET implicit $x10
219 bb.0.entry:
220 liveins: $x10, $x11
223 ; RV32I: liveins: $x10, $x11
225 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
226 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
227 ; RV32I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
228 ; RV32I-NEXT: $x10 = COPY [[SLL]]
229 ; RV32I-NEXT: PseudoRET implicit $x10
230 %0:gprb(s32) = COPY $x10
232 %2:gprb(s32) = G_SHL %0, %1
233 $x10 = COPY %2(s32)
234 PseudoRET implicit $x10
243 bb.0.entry:
244 liveins: $x10
247 ; RV32I: liveins: $x10
249 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
250 ; RV32I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31
251 ; RV32I-NEXT: $x10 = COPY [[SLLI]]
252 ; RV32I-NEXT: PseudoRET implicit $x10
253 %0:gprb(s32) = COPY $x10
255 %2:gprb(s32) = G_SHL %0, %1
256 $x10 = COPY %2(s32)
257 PseudoRET implicit $x10
266 bb.0.entry:
267 liveins: $x10, $x11
270 ; RV32I: liveins: $x10, $x11
272 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
273 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
274 ; RV32I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]]
275 ; RV32I-NEXT: $x10 = COPY [[SRA]]
276 ; RV32I-NEXT: PseudoRET implicit $x10
277 %0:gprb(s32) = COPY $x10
279 %2:gprb(s32) = G_ASHR %0, %1
280 $x10 = COPY %2(s32)
281 PseudoRET implicit $x10
290 bb.0.entry:
291 liveins: $x10
294 ; RV32I: liveins: $x10
296 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
297 ; RV32I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 31
298 ; RV32I-NEXT: $x10 = COPY [[SRAI]]
299 ; RV32I-NEXT: PseudoRET implicit $x10
300 %0:gprb(s32) = COPY $x10
302 %2:gprb(s32) = G_ASHR %0, %1
303 $x10 = COPY %2(s32)
304 PseudoRET implicit $x10
313 bb.0.entry:
314 liveins: $x10, $x11
317 ; RV32I: liveins: $x10, $x11
319 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
320 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
321 ; RV32I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]]
322 ; RV32I-NEXT: $x10 = COPY [[SRL]]
323 ; RV32I-NEXT: PseudoRET implicit $x10
324 %0:gprb(s32) = COPY $x10
326 %2:gprb(s32) = G_LSHR %0, %1
327 $x10 = COPY %2(s32)
328 PseudoRET implicit $x10
337 bb.0.entry:
338 liveins: $x10
341 ; RV32I: liveins: $x10
343 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
344 ; RV32I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 31
345 ; RV32I-NEXT: $x10 = COPY [[SRLI]]
346 ; RV32I-NEXT: PseudoRET implicit $x10
347 %0:gprb(s32) = COPY $x10
349 %2:gprb(s32) = G_LSHR %0, %1
350 $x10 = COPY %2(s32)
351 PseudoRET implicit $x10
360 bb.0.entry:
361 liveins: $x10, $x11
364 ; RV32I: liveins: $x10, $x11
366 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
367 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
368 ; RV32I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
369 ; RV32I-NEXT: $x10 = COPY [[AND]]
370 ; RV32I-NEXT: PseudoRET implicit $x10
371 %0:gprb(s32) = COPY $x10
373 %2:gprb(s32) = G_AND %0, %1
374 $x10 = COPY %2(s32)
375 PseudoRET implicit $x10
384 bb.0.entry:
385 liveins: $x10
388 ; RV32I: liveins: $x10
390 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
391 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234
392 ; RV32I-NEXT: $x10 = COPY [[ANDI]]
393 ; RV32I-NEXT: PseudoRET implicit $x10
394 %0:gprb(s32) = COPY $x10
396 %2:gprb(s32) = G_AND %0, %1
397 $x10 = COPY %2(s32)
398 PseudoRET implicit $x10
407 bb.0.entry:
408 liveins: $x10, $x11
411 ; RV32I: liveins: $x10, $x11
413 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
414 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
415 ; RV32I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
416 ; RV32I-NEXT: $x10 = COPY [[OR]]
417 ; RV32I-NEXT: PseudoRET implicit $x10
418 %0:gprb(s32) = COPY $x10
420 %2:gprb(s32) = G_OR %0, %1
421 $x10 = COPY %2(s32)
422 PseudoRET implicit $x10
431 bb.0.entry:
432 liveins: $x10
435 ; RV32I: liveins: $x10
437 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
438 ; RV32I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234
439 ; RV32I-NEXT: $x10 = COPY [[ORI]]
440 ; RV32I-NEXT: PseudoRET implicit $x10
441 %0:gprb(s32) = COPY $x10
443 %2:gprb(s32) = G_OR %0, %1
444 $x10 = COPY %2(s32)
445 PseudoRET implicit $x10
454 bb.0.entry:
455 liveins: $x10, $x11
458 ; RV32I: liveins: $x10, $x11
460 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
461 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
462 ; RV32I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
463 ; RV32I-NEXT: $x10 = COPY [[XOR]]
464 ; RV32I-NEXT: PseudoRET implicit $x10
465 %0:gprb(s32) = COPY $x10
467 %2:gprb(s32) = G_XOR %0, %1
468 $x10 = COPY %2(s32)
469 PseudoRET implicit $x10
478 bb.0.entry:
479 liveins: $x10
482 ; RV32I: liveins: $x10
484 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
485 ; RV32I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234
486 ; RV32I-NEXT: $x10 = COPY [[XORI]]
487 ; RV32I-NEXT: PseudoRET implicit $x10
488 %0:gprb(s32) = COPY $x10
490 %2:gprb(s32) = G_XOR %0, %1
491 $x10 = COPY %2(s32)
492 PseudoRET implicit $x10
501 bb.0.entry:
502 liveins: $x10, $x11, $x12, $x13
505 ; RV32I: liveins: $x10, $x11, $x12, $x13
507 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
508 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
509 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
510 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
511 ; RV32I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]]
512 ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]]
513 ; RV32I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]]
514 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
515 ; RV32I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]]
516 ; RV32I-NEXT: $x10 = COPY [[ADD]]
518 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
519 %0:gprb(s32) = COPY $x10
523 %4:gprb(s32) = G_ADD %0, %2
529 $x10 = COPY %4(s32)
531 PseudoRET implicit $x10, implicit $x11
540 bb.0.entry:
541 liveins: $x10, $x11, $x12, $x13
544 ; RV32I: liveins: $x10, $x11, $x12, $x13
546 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
547 ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
548 ; RV32I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
549 ; RV32I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
550 ; RV32I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]]
551 ; RV32I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]]
552 ; RV32I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]]
553 ; RV32I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
554 ; RV32I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]]
555 ; RV32I-NEXT: $x10 = COPY [[SUB]]
557 ; RV32I-NEXT: PseudoRET implicit $x10, implicit $x11
558 %0:gprb(s32) = COPY $x10
562 %4:gprb(s32) = G_SUB %0, %2
563 %5:gprb(s32) = G_ICMP intpred(ult), %0(s32), %2
568 $x10 = COPY %4(s32)
570 PseudoRET implicit $x10, implicit $x11