xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir (revision 87feafc391ab1e35997994ad378af727e4947c67) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv64 -mattr=+zbb -run-pass=instruction-select \
3# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4# RUN: llc -mtriple=riscv64 -mattr=+zbkb -run-pass=instruction-select \
5# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
6
7---
8name:            rotl_i32
9legalized:       true
10regBankSelected: true
11tracksRegLiveness: true
12body:             |
13  bb.0:
14    liveins: $x10, $x11
15
16    ; CHECK-LABEL: name: rotl_i32
17    ; CHECK: liveins: $x10, $x11
18    ; CHECK-NEXT: {{  $}}
19    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
20    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
21    ; CHECK-NEXT: [[ROLW:%[0-9]+]]:gpr = ROLW [[COPY]], [[COPY1]]
22    ; CHECK-NEXT: $x10 = COPY [[ROLW]]
23    ; CHECK-NEXT: PseudoRET implicit $x10
24    %0:gprb(s64) = COPY $x10
25    %1:gprb(s64) = COPY $x11
26    %2:gprb(s64) = G_ROLW %0, %1(s64)
27    $x10 = COPY %2(s64)
28    PseudoRET implicit $x10
29
30...
31---
32name:            rotl_i64
33legalized:       true
34regBankSelected: true
35tracksRegLiveness: true
36body:             |
37  bb.0:
38    liveins: $x10, $x11
39
40    ; CHECK-LABEL: name: rotl_i64
41    ; CHECK: liveins: $x10, $x11
42    ; CHECK-NEXT: {{  $}}
43    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
44    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
45    ; CHECK-NEXT: [[ROL:%[0-9]+]]:gpr = ROL [[COPY]], [[COPY1]]
46    ; CHECK-NEXT: $x10 = COPY [[ROL]]
47    ; CHECK-NEXT: PseudoRET implicit $x10
48    %0:gprb(s64) = COPY $x10
49    %1:gprb(s64) = COPY $x11
50    %2:gprb(s64) = G_ROTL %0, %1(s64)
51    $x10 = COPY %2(s64)
52    PseudoRET implicit $x10
53
54...
55---
56name:            rotr_i32
57legalized:       true
58regBankSelected: true
59body:             |
60  bb.0:
61    liveins: $x10, $x11
62
63    ; CHECK-LABEL: name: rotr_i32
64    ; CHECK: liveins: $x10, $x11
65    ; CHECK-NEXT: {{  $}}
66    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
67    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
68    ; CHECK-NEXT: [[RORW:%[0-9]+]]:gpr = RORW [[COPY]], [[COPY1]]
69    ; CHECK-NEXT: $x10 = COPY [[RORW]]
70    ; CHECK-NEXT: PseudoRET implicit $x10
71    %0:gprb(s64) = COPY $x10
72    %1:gprb(s64) = COPY $x11
73    %2:gprb(s64) = G_RORW %0, %1(s64)
74    $x10 = COPY %2(s64)
75    PseudoRET implicit $x10
76
77...
78---
79name:            rotr_i64
80legalized:       true
81regBankSelected: true
82body:             |
83  bb.0:
84    liveins: $x10, $x11
85
86    ; CHECK-LABEL: name: rotr_i64
87    ; CHECK: liveins: $x10, $x11
88    ; CHECK-NEXT: {{  $}}
89    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
90    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
91    ; CHECK-NEXT: [[ROR:%[0-9]+]]:gpr = ROR [[COPY]], [[COPY1]]
92    ; CHECK-NEXT: $x10 = COPY [[ROR]]
93    ; CHECK-NEXT: PseudoRET implicit $x10
94    %0:gprb(s64) = COPY $x10
95    %1:gprb(s64) = COPY $x11
96    %2:gprb(s64) = G_ROTR %0, %1(s64)
97    $x10 = COPY %2(s64)
98    PseudoRET implicit $x10
99
100...
101---
102name:            rotl_imm_i32
103legalized:       true
104regBankSelected: true
105tracksRegLiveness: true
106body:             |
107  bb.0:
108    liveins: $x10
109
110    ; CHECK-LABEL: name: rotl_imm_i32
111    ; CHECK: liveins: $x10
112    ; CHECK-NEXT: {{  $}}
113    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
114    ; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 17
115    ; CHECK-NEXT: $x10 = COPY [[RORIW]]
116    ; CHECK-NEXT: PseudoRET implicit $x10
117    %0:gprb(s64) = COPY $x10
118    %1:gprb(s64) = G_CONSTANT i64 15
119    %2:gprb(s64) = G_ROLW %0, %1(s64)
120    $x10 = COPY %2(s64)
121    PseudoRET implicit $x10
122
123...
124---
125name:            rotl_imm_i64
126legalized:       true
127regBankSelected: true
128tracksRegLiveness: true
129body:             |
130  bb.0:
131    liveins: $x10
132
133    ; CHECK-LABEL: name: rotl_imm_i64
134    ; CHECK: liveins: $x10
135    ; CHECK-NEXT: {{  $}}
136    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
137    ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 31
138    ; CHECK-NEXT: $x10 = COPY [[RORI]]
139    ; CHECK-NEXT: PseudoRET implicit $x10
140    %0:gprb(s64) = COPY $x10
141    %1:gprb(s64) = G_CONSTANT i64 33
142    %2:gprb(s64) = G_ROTL %0, %1(s64)
143    $x10 = COPY %2(s64)
144    PseudoRET implicit $x10
145
146...
147---
148name:            rotr_imm_i32
149legalized:       true
150regBankSelected: true
151tracksRegLiveness: true
152body:             |
153  bb.0:
154    liveins: $x10
155
156    ; CHECK-LABEL: name: rotr_imm_i32
157    ; CHECK: liveins: $x10
158    ; CHECK-NEXT: {{  $}}
159    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
160    ; CHECK-NEXT: [[RORIW:%[0-9]+]]:gpr = RORIW [[COPY]], 15
161    ; CHECK-NEXT: $x10 = COPY [[RORIW]]
162    ; CHECK-NEXT: PseudoRET implicit $x10
163    %0:gprb(s64) = COPY $x10
164    %1:gprb(s64) = G_CONSTANT i64 15
165    %2:gprb(s64) = G_RORW %0, %1(s64)
166    $x10 = COPY %2(s64)
167    PseudoRET implicit $x10
168
169...
170---
171name:            rotr_imm_i64
172legalized:       true
173regBankSelected: true
174tracksRegLiveness: true
175body:             |
176  bb.0:
177    liveins: $x10
178
179    ; CHECK-LABEL: name: rotr_imm_i64
180    ; CHECK: liveins: $x10
181    ; CHECK-NEXT: {{  $}}
182    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
183    ; CHECK-NEXT: [[RORI:%[0-9]+]]:gpr = RORI [[COPY]], 33
184    ; CHECK-NEXT: $x10 = COPY [[RORI]]
185    ; CHECK-NEXT: PseudoRET implicit $x10
186    %0:gprb(s64) = COPY $x10
187    %1:gprb(s64) = G_CONSTANT i64 33
188    %2:gprb(s64) = G_ROTR %0, %1(s64)
189    $x10 = COPY %2(s64)
190    PseudoRET implicit $x10
191
192...
193