xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir (revision ed3a60c796c2ed3c9fc59efc83856913ab5860f5) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select \
3# RUN:   -simplify-mir -verify-machineinstrs %s -o - | FileCheck %s
4
5# This 32-bit version doesn't have tests for zext, because there is no legal type to zext from.
6---
7name:            shl
8legalized:       true
9regBankSelected: true
10tracksRegLiveness: true
11body:             |
12  bb.0:
13    liveins: $x10, $x11
14
15    ; CHECK-LABEL: name: shl
16    ; CHECK: liveins: $x10, $x11
17    ; CHECK-NEXT: {{  $}}
18    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
19    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
20    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
21    ; CHECK-NEXT: $x10 = COPY [[SLL]]
22    ; CHECK-NEXT: PseudoRET implicit $x10
23    %0:gprb(s32) = COPY $x10
24    %1:gprb(s32) = COPY $x11
25    %3:gprb(s32) = G_SHL %0, %1
26    $x10 = COPY %3(s32)
27    PseudoRET implicit $x10
28...
29
30---
31name:            shl_and
32legalized:       true
33regBankSelected: true
34tracksRegLiveness: true
35body:             |
36  bb.0:
37    liveins: $x10, $x11
38
39    ; CHECK-LABEL: name: shl_and
40    ; CHECK: liveins: $x10, $x11
41    ; CHECK-NEXT: {{  $}}
42    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
43    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
44    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
45    ; CHECK-NEXT: $x10 = COPY [[SLL]]
46    ; CHECK-NEXT: PseudoRET implicit $x10
47    %0:gprb(s32) = COPY $x10
48    %1:gprb(s32) = COPY $x11
49    %2:gprb(s32) = G_CONSTANT i32 31
50    %3:gprb(s32) = G_AND %1, %2
51    %4:gprb(s32) = G_SHL %0, %3(s32)
52    $x10 = COPY %4(s32)
53    PseudoRET implicit $x10
54...
55
56---
57name:            shl_and_with_simplified_mask
58legalized:       true
59regBankSelected: true
60tracksRegLiveness: true
61body:             |
62  bb.0:
63    liveins: $x10, $x11
64
65    ; CHECK-LABEL: name: shl_and_with_simplified_mask
66    ; CHECK: liveins: $x10, $x11
67    ; CHECK-NEXT: {{  $}}
68    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
69    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
70    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY1]], 31
71    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[ANDI]]
72    ; CHECK-NEXT: $x10 = COPY [[SLL]]
73    ; CHECK-NEXT: PseudoRET implicit $x10
74    %0:gprb(s32) = COPY $x10
75    %1:gprb(s32) = COPY $x11
76    %2:gprb(s32) = G_CONSTANT i32 31
77    %3:gprb(s32) = G_AND %1, %2
78    %4:gprb(s32) = G_CONSTANT i32 31
79    %5:gprb(s32) = G_AND %3, %4
80    %6:gprb(s32) = G_SHL %0, %5(s32)
81    $x10 = COPY %6(s32)
82    PseudoRET implicit $x10
83...
84
85---
86name:            shl_add
87legalized:       true
88regBankSelected: true
89tracksRegLiveness: true
90body:             |
91  bb.0:
92    liveins: $x10, $x11
93
94    ; CHECK-LABEL: name: shl_add
95    ; CHECK: liveins: $x10, $x11
96    ; CHECK-NEXT: {{  $}}
97    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
98    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
99    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
100    ; CHECK-NEXT: $x10 = COPY [[SLL]]
101    ; CHECK-NEXT: PseudoRET implicit $x10
102    %0:gprb(s32) = COPY $x10
103    %1:gprb(s32) = COPY $x11
104    %2:gprb(s32) = G_CONSTANT i32 32
105    %3:gprb(s32) = G_ADD %1, %2
106    %4:gprb(s32) = G_SHL %0, %3(s32)
107    $x10 = COPY %4(s32)
108    PseudoRET implicit $x10
109...
110
111---
112name:            shl_sub
113legalized:       true
114regBankSelected: true
115tracksRegLiveness: true
116body:             |
117  bb.0:
118    liveins: $x10, $x11
119
120    ; CHECK-LABEL: name: shl_sub
121    ; CHECK: liveins: $x10, $x11
122    ; CHECK-NEXT: {{  $}}
123    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
124    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
125    ; CHECK-NEXT: [[SUB:%[0-9]+]]:gpr = SUB $x0, [[COPY1]]
126    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[SUB]]
127    ; CHECK-NEXT: $x10 = COPY [[SLL]]
128    ; CHECK-NEXT: PseudoRET implicit $x10
129    %0:gprb(s32) = COPY $x10
130    %1:gprb(s32) = COPY $x11
131    %2:gprb(s32) = G_CONSTANT i32 32
132    %3:gprb(s32) = G_SUB %2, %1
133    %4:gprb(s32) = G_SHL %0, %3(s32)
134    $x10 = COPY %4(s32)
135    PseudoRET implicit $x10
136...
137
138---
139name:            shl_bitwise_not
140legalized:       true
141regBankSelected: true
142tracksRegLiveness: true
143body:             |
144  bb.0:
145    liveins: $x10, $x11
146
147    ; CHECK-LABEL: name: shl_bitwise_not
148    ; CHECK: liveins: $x10, $x11
149    ; CHECK-NEXT: {{  $}}
150    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
151    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
152    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1
153    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]
154    ; CHECK-NEXT: $x10 = COPY [[SLL]]
155    ; CHECK-NEXT: PseudoRET implicit $x10
156    %0:gprb(s32) = COPY $x10
157    %1:gprb(s32) = COPY $x11
158    %2:gprb(s32) = G_CONSTANT i32 -1
159    %3:gprb(s32) = G_SUB %2, %1
160    %4:gprb(s32) = G_SHL %0, %3(s32)
161    $x10 = COPY %4(s32)
162    PseudoRET implicit $x10
163...
164
165---
166name:            shl_bitwise_not_2
167legalized:       true
168regBankSelected: true
169tracksRegLiveness: true
170body:             |
171  bb.0:
172    liveins: $x10, $x11
173
174    ; CHECK-LABEL: name: shl_bitwise_not_2
175    ; CHECK: liveins: $x10, $x11
176    ; CHECK-NEXT: {{  $}}
177    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
178    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
179    ; CHECK-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY1]], -1
180    ; CHECK-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[XORI]]
181    ; CHECK-NEXT: $x10 = COPY [[SLL]]
182    ; CHECK-NEXT: PseudoRET implicit $x10
183    %0:gprb(s32) = COPY $x10
184    %1:gprb(s32) = COPY $x11
185    %2:gprb(s32) = G_CONSTANT i32 31
186    %3:gprb(s32) = G_SUB %2, %1
187    %4:gprb(s32) = G_SHL %0, %3(s32)
188    $x10 = COPY %4(s32)
189    PseudoRET implicit $x10
190...
191
192---
193name:            srl_and_needed
194legalized:       true
195regBankSelected: true
196tracksRegLiveness: true
197body:             |
198  bb.1.entry:
199    liveins: $x10, $x11
200
201    ; CHECK-LABEL: name: srl_and_needed
202    ; CHECK: liveins: $x10, $x11
203    ; CHECK-NEXT: {{  $}}
204    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
205    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
206    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 15
207    ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]
208    ; CHECK-NEXT: $x10 = COPY [[SRL]]
209    ; CHECK-NEXT: PseudoRET implicit $x10
210    %0:gprb(s32) = COPY $x10
211    %1:gprb(s32) = COPY $x11
212    %2:gprb(s32) = G_CONSTANT i32 15
213    %3:gprb(s32) = G_AND %0, %2
214    %4:gprb(s32) = G_LSHR %1, %3(s32)
215    $x10 = COPY %4(s32)
216    PseudoRET implicit $x10
217...
218
219---
220name:            srl_and_eliminated
221legalized:       true
222regBankSelected: true
223tracksRegLiveness: true
224body:             |
225  bb.1.entry:
226    liveins: $x10, $x11
227
228    ; CHECK-LABEL: name: srl_and_eliminated
229    ; CHECK: liveins: $x10, $x11
230    ; CHECK-NEXT: {{  $}}
231    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
232    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
233    ; CHECK-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 47
234    ; CHECK-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY1]], [[ANDI]]
235    ; CHECK-NEXT: $x10 = COPY [[SRL]]
236    ; CHECK-NEXT: PseudoRET implicit $x10
237    %0:gprb(s32) = COPY $x10
238    %1:gprb(s32) = COPY $x11
239    %2:gprb(s32) = G_CONSTANT i32 15
240    %3:gprb(s32) = G_CONSTANT i32 47
241    %4:gprb(s32) = G_AND %0, %3
242    %5:gprb(s32) = G_AND %4, %2
243    %6:gprb(s32) = G_LSHR %1, %5(s32)
244    $x10 = COPY %6(s32)
245    PseudoRET implicit $x10
246...
247