xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/load-rv32.mir (revision eff60d83b0533954eda153fbbabb3e99d46bde94) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -run-pass=instruction-select %s -o - \
3# RUN:   -disable-gisel-legality-check | FileCheck %s
4
5---
6name:            load_i8
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:            |
11  bb.0:
12    liveins: $x10
13
14    ; CHECK-LABEL: name: load_i8
15    ; CHECK: liveins: $x10
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18    ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
19    ; CHECK-NEXT: $x10 = COPY [[LBU]]
20    ; CHECK-NEXT: PseudoRET implicit $x10
21    %0:gprb(p0) = COPY $x10
22    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s8))
23    $x10 = COPY %1(s32)
24    PseudoRET implicit $x10
25
26...
27---
28name:            load_i16
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32body:            |
33  bb.0:
34    liveins: $x10
35
36    ; CHECK-LABEL: name: load_i16
37    ; CHECK: liveins: $x10
38    ; CHECK-NEXT: {{  $}}
39    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
40    ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
41    ; CHECK-NEXT: $x10 = COPY [[LH]]
42    ; CHECK-NEXT: PseudoRET implicit $x10
43    %0:gprb(p0) = COPY $x10
44    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s16))
45    $x10 = COPY %1(s32)
46    PseudoRET implicit $x10
47
48...
49---
50name:            load_i8_i16
51legalized:       true
52regBankSelected: true
53tracksRegLiveness: true
54body:            |
55  bb.0:
56    liveins: $x10
57
58    ; CHECK-LABEL: name: load_i8_i16
59    ; CHECK: liveins: $x10
60    ; CHECK-NEXT: {{  $}}
61    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
62    ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
63    ; CHECK-NEXT: $x10 = COPY [[LBU]]
64    ; CHECK-NEXT: PseudoRET implicit $x10
65    %0:gprb(p0) = COPY $x10
66    %1:gprb(s16) = G_LOAD %0(p0) :: (load (s8))
67    %2:gprb(s32) = G_ANYEXT %1
68    $x10 = COPY %2(s32)
69    PseudoRET implicit $x10
70
71...
72---
73name:            load_i16_i16
74legalized:       true
75regBankSelected: true
76tracksRegLiveness: true
77body:            |
78  bb.0:
79    liveins: $x10
80
81    ; CHECK-LABEL: name: load_i16_i16
82    ; CHECK: liveins: $x10
83    ; CHECK-NEXT: {{  $}}
84    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
85    ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
86    ; CHECK-NEXT: $x10 = COPY [[LH]]
87    ; CHECK-NEXT: PseudoRET implicit $x10
88    %0:gprb(p0) = COPY $x10
89    %1:gprb(s16) = G_LOAD %0(p0) :: (load (s16))
90    %2:gprb(s32) = G_ANYEXT %1
91    $x10 = COPY %2(s32)
92    PseudoRET implicit $x10
93
94...
95---
96name:            load_i32
97legalized:       true
98regBankSelected: true
99tracksRegLiveness: true
100body:            |
101  bb.0:
102    liveins: $x10
103
104    ; CHECK-LABEL: name: load_i32
105    ; CHECK: liveins: $x10
106    ; CHECK-NEXT: {{  $}}
107    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
108    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (s32))
109    ; CHECK-NEXT: $x10 = COPY [[LW]]
110    ; CHECK-NEXT: PseudoRET implicit $x10
111    %0:gprb(p0) = COPY $x10
112    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
113    $x10 = COPY %1(s32)
114    PseudoRET implicit $x10
115
116...
117---
118name:            zextload_i8
119legalized:       true
120regBankSelected: true
121tracksRegLiveness: true
122body:            |
123  bb.0:
124    liveins: $x10
125
126    ; CHECK-LABEL: name: zextload_i8
127    ; CHECK: liveins: $x10
128    ; CHECK-NEXT: {{  $}}
129    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
130    ; CHECK-NEXT: [[LBU:%[0-9]+]]:gpr = LBU [[COPY]], 0 :: (load (s8))
131    ; CHECK-NEXT: $x10 = COPY [[LBU]]
132    ; CHECK-NEXT: PseudoRET implicit $x10
133    %0:gprb(p0) = COPY $x10
134    %1:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s8))
135    $x10 = COPY %1(s32)
136    PseudoRET implicit $x10
137
138...
139---
140name:            zextload_i16
141legalized:       true
142regBankSelected: true
143tracksRegLiveness: true
144body:            |
145  bb.0:
146    liveins: $x10
147
148    ; CHECK-LABEL: name: zextload_i16
149    ; CHECK: liveins: $x10
150    ; CHECK-NEXT: {{  $}}
151    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
152    ; CHECK-NEXT: [[LHU:%[0-9]+]]:gpr = LHU [[COPY]], 0 :: (load (s16))
153    ; CHECK-NEXT: $x10 = COPY [[LHU]]
154    ; CHECK-NEXT: PseudoRET implicit $x10
155    %0:gprb(p0) = COPY $x10
156    %1:gprb(s32) = G_ZEXTLOAD %0(p0) :: (load (s16))
157    $x10 = COPY %1(s32)
158    PseudoRET implicit $x10
159
160...
161---
162name:            sextload_i8
163legalized:       true
164regBankSelected: true
165tracksRegLiveness: true
166body:            |
167  bb.0:
168    liveins: $x10
169
170    ; CHECK-LABEL: name: sextload_i8
171    ; CHECK: liveins: $x10
172    ; CHECK-NEXT: {{  $}}
173    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
174    ; CHECK-NEXT: [[LB:%[0-9]+]]:gpr = LB [[COPY]], 0 :: (load (s8))
175    ; CHECK-NEXT: $x10 = COPY [[LB]]
176    ; CHECK-NEXT: PseudoRET implicit $x10
177    %0:gprb(p0) = COPY $x10
178    %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s8))
179    $x10 = COPY %1(s32)
180    PseudoRET implicit $x10
181
182...
183---
184name:            sextload_i16
185legalized:       true
186regBankSelected: true
187tracksRegLiveness: true
188body:            |
189  bb.0:
190    liveins: $x10
191
192    ; CHECK-LABEL: name: sextload_i16
193    ; CHECK: liveins: $x10
194    ; CHECK-NEXT: {{  $}}
195    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
196    ; CHECK-NEXT: [[LH:%[0-9]+]]:gpr = LH [[COPY]], 0 :: (load (s16))
197    ; CHECK-NEXT: $x10 = COPY [[LH]]
198    ; CHECK-NEXT: PseudoRET implicit $x10
199    %0:gprb(p0) = COPY $x10
200    %1:gprb(s32) = G_SEXTLOAD %0(p0) :: (load (s16))
201    $x10 = COPY %1(s32)
202    PseudoRET implicit $x10
203
204...
205---
206name:            load_p0
207legalized:       true
208regBankSelected: true
209tracksRegLiveness: true
210body:            |
211  bb.0:
212    liveins: $x10
213
214    ; CHECK-LABEL: name: load_p0
215    ; CHECK: liveins: $x10
216    ; CHECK-NEXT: {{  $}}
217    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
218    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 0 :: (load (p0))
219    ; CHECK-NEXT: $x10 = COPY [[LW]]
220    ; CHECK-NEXT: PseudoRET implicit $x10
221    %0:gprb(p0) = COPY $x10
222    %1:gprb(p0) = G_LOAD %0(p0) :: (load (p0))
223    $x10 = COPY %1(p0)
224    PseudoRET implicit $x10
225
226...
227---
228name:            load_fi_i32
229legalized:       true
230regBankSelected: true
231tracksRegLiveness: true
232
233stack:
234  - { id: 0, offset: 0, size: 4, alignment: 4 }
235
236body:            |
237  bb.0:
238    ; CHECK-LABEL: name: load_fi_i32
239    ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 0 :: (load (s32))
240    ; CHECK-NEXT: $x10 = COPY [[LW]]
241    ; CHECK-NEXT: PseudoRET implicit $x10
242    %0:gprb(p0) = G_FRAME_INDEX %stack.0
243    %1:gprb(s32) = G_LOAD %0(p0) :: (load (s32))
244    $x10 = COPY %1(s32)
245    PseudoRET implicit $x10
246
247...
248---
249name:            load_fi_gep_i32
250legalized:       true
251regBankSelected: true
252tracksRegLiveness: true
253
254stack:
255  - { id: 0, offset: 0, size: 8, alignment: 4 }
256
257body:            |
258  bb.0:
259    ; CHECK-LABEL: name: load_fi_gep_i32
260    ; CHECK: [[LW:%[0-9]+]]:gpr = LW %stack.0, 4 :: (load (s32))
261    ; CHECK-NEXT: $x10 = COPY [[LW]]
262    ; CHECK-NEXT: PseudoRET implicit $x10
263    %0:gprb(p0) = G_FRAME_INDEX %stack.0
264    %1:gprb(s32) = G_CONSTANT i32 4
265    %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
266    %3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
267    $x10 = COPY %3(s32)
268    PseudoRET implicit $x10
269
270...
271---
272name:            load_gep_i32
273legalized:       true
274regBankSelected: true
275tracksRegLiveness: true
276body:            |
277  bb.0:
278    liveins: $x10
279
280    ; CHECK-LABEL: name: load_gep_i32
281    ; CHECK: liveins: $x10
282    ; CHECK-NEXT: {{  $}}
283    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
284    ; CHECK-NEXT: [[LW:%[0-9]+]]:gpr = LW [[COPY]], 4 :: (load (s32))
285    ; CHECK-NEXT: $x10 = COPY [[LW]]
286    ; CHECK-NEXT: PseudoRET implicit $x10
287    %0:gprb(p0) = COPY $x10
288    %1:gprb(s32) = G_CONSTANT i32 4
289    %2:gprb(p0) = G_PTR_ADD %0(p0), %1(s32)
290    %3:gprb(s32) = G_LOAD %2(p0) :: (load (s32))
291    $x10 = COPY %3(s32)
292    PseudoRET implicit $x10
293
294...
295