1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=riscv32 -run-pass=regbankselect \ 3# RUN: -simplify-mir -verify-machineinstrs %s \ 4# RUN: -o - | FileCheck -check-prefix=RV32I %s 5 6--- 7name: load_i8 8legalized: true 9tracksRegLiveness: true 10body: | 11 bb.0: 12 liveins: $x10 13 14 ; RV32I-LABEL: name: load_i8 15 ; RV32I: liveins: $x10 16 ; RV32I-NEXT: {{ $}} 17 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 18 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s8)) 19 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32) 20 ; RV32I-NEXT: PseudoRET implicit $x10 21 %0:_(p0) = COPY $x10 22 %3:_(s32) = G_LOAD %0(p0) :: (load (s8)) 23 $x10 = COPY %3(s32) 24 PseudoRET implicit $x10 25 26... 27--- 28name: load_i16 29legalized: true 30tracksRegLiveness: true 31body: | 32 bb.0: 33 liveins: $x10 34 35 ; RV32I-LABEL: name: load_i16 36 ; RV32I: liveins: $x10 37 ; RV32I-NEXT: {{ $}} 38 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 39 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s16)) 40 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32) 41 ; RV32I-NEXT: PseudoRET implicit $x10 42 %0:_(p0) = COPY $x10 43 %3:_(s32) = G_LOAD %0(p0) :: (load (s16)) 44 $x10 = COPY %3(s32) 45 PseudoRET implicit $x10 46 47... 48--- 49name: load_i32 50legalized: true 51tracksRegLiveness: true 52body: | 53 bb.0: 54 liveins: $x10 55 56 ; RV32I-LABEL: name: load_i32 57 ; RV32I: liveins: $x10 58 ; RV32I-NEXT: {{ $}} 59 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 60 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(s32) = G_LOAD [[COPY]](p0) :: (load (s32)) 61 ; RV32I-NEXT: $x10 = COPY [[LOAD]](s32) 62 ; RV32I-NEXT: PseudoRET implicit $x10 63 %0:_(p0) = COPY $x10 64 %3:_(s32) = G_LOAD %0(p0) :: (load (s32)) 65 $x10 = COPY %3(s32) 66 PseudoRET implicit $x10 67 68... 69--- 70name: load_ptr 71legalized: true 72tracksRegLiveness: true 73body: | 74 bb.0: 75 liveins: $x10 76 77 ; RV32I-LABEL: name: load_ptr 78 ; RV32I: liveins: $x10 79 ; RV32I-NEXT: {{ $}} 80 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 81 ; RV32I-NEXT: [[LOAD:%[0-9]+]]:gprb(p0) = G_LOAD [[COPY]](p0) :: (load (p0)) 82 ; RV32I-NEXT: $x10 = COPY [[LOAD]](p0) 83 ; RV32I-NEXT: PseudoRET implicit $x10 84 %0:_(p0) = COPY $x10 85 %3:_(p0) = G_LOAD %0(p0) :: (load (p0)) 86 $x10 = COPY %3(p0) 87 PseudoRET implicit $x10 88 89... 90--- 91name: zextload_i8 92legalized: true 93tracksRegLiveness: true 94body: | 95 bb.0: 96 liveins: $x10 97 98 ; RV32I-LABEL: name: zextload_i8 99 ; RV32I: liveins: $x10 100 ; RV32I-NEXT: {{ $}} 101 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 102 ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8)) 103 ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) 104 ; RV32I-NEXT: PseudoRET implicit $x10 105 %0:_(p0) = COPY $x10 106 %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s8)) 107 $x10 = COPY %1(s32) 108 PseudoRET implicit $x10 109 110... 111--- 112name: zextload_i16 113legalized: true 114tracksRegLiveness: true 115body: | 116 bb.0: 117 liveins: $x10 118 119 ; RV32I-LABEL: name: zextload_i16 120 ; RV32I: liveins: $x10 121 ; RV32I-NEXT: {{ $}} 122 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 123 ; RV32I-NEXT: [[ZEXTLOAD:%[0-9]+]]:gprb(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16)) 124 ; RV32I-NEXT: $x10 = COPY [[ZEXTLOAD]](s32) 125 ; RV32I-NEXT: PseudoRET implicit $x10 126 %0:_(p0) = COPY $x10 127 %1:_(s32) = G_ZEXTLOAD %0(p0) :: (load (s16)) 128 $x10 = COPY %1(s32) 129 PseudoRET implicit $x10 130 131... 132--- 133name: sextload_i8 134legalized: true 135tracksRegLiveness: true 136body: | 137 bb.0: 138 liveins: $x10 139 140 ; RV32I-LABEL: name: sextload_i8 141 ; RV32I: liveins: $x10 142 ; RV32I-NEXT: {{ $}} 143 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 144 ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8)) 145 ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32) 146 ; RV32I-NEXT: PseudoRET implicit $x10 147 %0:_(p0) = COPY $x10 148 %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s8)) 149 $x10 = COPY %1(s32) 150 PseudoRET implicit $x10 151 152... 153--- 154name: sextload_i16 155legalized: true 156tracksRegLiveness: true 157body: | 158 bb.0: 159 liveins: $x10 160 161 ; RV32I-LABEL: name: sextload_i16 162 ; RV32I: liveins: $x10 163 ; RV32I-NEXT: {{ $}} 164 ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10 165 ; RV32I-NEXT: [[SEXTLOAD:%[0-9]+]]:gprb(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16)) 166 ; RV32I-NEXT: $x10 = COPY [[SEXTLOAD]](s32) 167 ; RV32I-NEXT: PseudoRET implicit $x10 168 %0:_(p0) = COPY $x10 169 %1:_(s32) = G_SEXTLOAD %0(p0) :: (load (s16)) 170 $x10 = COPY %1(s32) 171 PseudoRET implicit $x10 172 173... 174