xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu_m-rv64.mir (revision 615e28e6271025cc3dbdf8c04e9902a5dd8b2b0c) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv64 -mattr=+m -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
3# RUN: | FileCheck -check-prefix=RV64I %s
4
5---
6name:            sdiv_i32
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0.entry:
12    liveins: $x10, $x11
13
14    ; RV64I-LABEL: name: sdiv_i32
15    ; RV64I: liveins: $x10, $x11
16    ; RV64I-NEXT: {{  $}}
17    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19    ; RV64I-NEXT: [[DIVW:%[0-9]+]]:gpr = DIVW [[COPY]], [[COPY1]]
20    ; RV64I-NEXT: $x10 = COPY [[DIVW]]
21    ; RV64I-NEXT: PseudoRET implicit $x10
22    %0:gprb(s64) = COPY $x10
23    %1:gprb(s64) = COPY $x11
24    %2:gprb(s64) = G_DIVW %0, %1
25    $x10 = COPY %2(s64)
26    PseudoRET implicit $x10
27
28...
29---
30name:            udiv_i32
31legalized:       true
32regBankSelected: true
33tracksRegLiveness: true
34body:             |
35  bb.0.entry:
36    liveins: $x10, $x11
37
38    ; RV64I-LABEL: name: udiv_i32
39    ; RV64I: liveins: $x10, $x11
40    ; RV64I-NEXT: {{  $}}
41    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
42    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
43    ; RV64I-NEXT: [[DIVUW:%[0-9]+]]:gpr = DIVUW [[COPY]], [[COPY1]]
44    ; RV64I-NEXT: $x10 = COPY [[DIVUW]]
45    ; RV64I-NEXT: PseudoRET implicit $x10
46    %0:gprb(s64) = COPY $x10
47    %1:gprb(s64) = COPY $x11
48    %2:gprb(s64) = G_DIVUW %0, %1
49    $x10 = COPY %2(s64)
50    PseudoRET implicit $x10
51
52...
53---
54name:            urem_i32
55legalized:       true
56regBankSelected: true
57tracksRegLiveness: true
58body:             |
59  bb.0.entry:
60    liveins: $x10, $x11
61
62    ; RV64I-LABEL: name: urem_i32
63    ; RV64I: liveins: $x10, $x11
64    ; RV64I-NEXT: {{  $}}
65    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
66    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
67    ; RV64I-NEXT: [[REMUW:%[0-9]+]]:gpr = REMUW [[COPY]], [[COPY1]]
68    ; RV64I-NEXT: $x10 = COPY [[REMUW]]
69    ; RV64I-NEXT: PseudoRET implicit $x10
70    %0:gprb(s64) = COPY $x10
71    %1:gprb(s64) = COPY $x11
72    %2:gprb(s64) = G_REMUW %0, %1
73    $x10 = COPY %2(s64)
74    PseudoRET implicit $x10
75
76...
77---
78name:            mul_i64
79legalized:       true
80regBankSelected: true
81tracksRegLiveness: true
82body:             |
83  bb.0.entry:
84    liveins: $x10, $x11
85
86    ; RV64I-LABEL: name: mul_i64
87    ; RV64I: liveins: $x10, $x11
88    ; RV64I-NEXT: {{  $}}
89    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
90    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
91    ; RV64I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY1]]
92    ; RV64I-NEXT: $x10 = COPY [[MUL]]
93    ; RV64I-NEXT: PseudoRET implicit $x10
94    %0:gprb(s64) = COPY $x10
95    %1:gprb(s64) = COPY $x11
96    %2:gprb(s64) = G_MUL %0, %1
97    $x10 = COPY %2(s64)
98    PseudoRET implicit $x10
99
100...
101---
102name:            sdiv_i64
103legalized:       true
104regBankSelected: true
105tracksRegLiveness: true
106body:             |
107  bb.0.entry:
108    liveins: $x10, $x11
109
110    ; RV64I-LABEL: name: sdiv_i64
111    ; RV64I: liveins: $x10, $x11
112    ; RV64I-NEXT: {{  $}}
113    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
114    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
115    ; RV64I-NEXT: [[DIV:%[0-9]+]]:gpr = DIV [[COPY]], [[COPY1]]
116    ; RV64I-NEXT: $x10 = COPY [[DIV]]
117    ; RV64I-NEXT: PseudoRET implicit $x10
118    %0:gprb(s64) = COPY $x10
119    %1:gprb(s64) = COPY $x11
120    %2:gprb(s64) = G_SDIV %0, %1
121    $x10 = COPY %2(s64)
122    PseudoRET implicit $x10
123
124...
125---
126name:            srem_i64
127legalized:       true
128regBankSelected: true
129tracksRegLiveness: true
130body:             |
131  bb.0.entry:
132    liveins: $x10, $x11
133
134    ; RV64I-LABEL: name: srem_i64
135    ; RV64I: liveins: $x10, $x11
136    ; RV64I-NEXT: {{  $}}
137    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
138    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
139    ; RV64I-NEXT: [[REM:%[0-9]+]]:gpr = REM [[COPY]], [[COPY1]]
140    ; RV64I-NEXT: $x10 = COPY [[REM]]
141    ; RV64I-NEXT: PseudoRET implicit $x10
142    %0:gprb(s64) = COPY $x10
143    %1:gprb(s64) = COPY $x11
144    %2:gprb(s64) = G_SREM %0, %1
145    $x10 = COPY %2(s64)
146    PseudoRET implicit $x10
147
148...
149---
150name:            smulh_i64
151legalized:       true
152regBankSelected: true
153tracksRegLiveness: true
154body:             |
155  bb.0.entry:
156    liveins: $x10, $x11
157
158    ; RV64I-LABEL: name: smulh_i64
159    ; RV64I: liveins: $x10, $x11
160    ; RV64I-NEXT: {{  $}}
161    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
162    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
163    ; RV64I-NEXT: [[MULH:%[0-9]+]]:gpr = MULH [[COPY]], [[COPY1]]
164    ; RV64I-NEXT: $x10 = COPY [[MULH]]
165    ; RV64I-NEXT: PseudoRET implicit $x10
166    %0:gprb(s64) = COPY $x10
167    %1:gprb(s64) = COPY $x11
168    %2:gprb(s64) = G_SMULH %0, %1
169    $x10 = COPY %2(s64)
170    PseudoRET implicit $x10
171
172...
173---
174name:            udiv_i64
175legalized:       true
176regBankSelected: true
177tracksRegLiveness: true
178body:             |
179  bb.0.entry:
180    liveins: $x10, $x11
181
182    ; RV64I-LABEL: name: udiv_i64
183    ; RV64I: liveins: $x10, $x11
184    ; RV64I-NEXT: {{  $}}
185    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
186    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
187    ; RV64I-NEXT: [[DIVU:%[0-9]+]]:gpr = DIVU [[COPY]], [[COPY1]]
188    ; RV64I-NEXT: $x10 = COPY [[DIVU]]
189    ; RV64I-NEXT: PseudoRET implicit $x10
190    %0:gprb(s64) = COPY $x10
191    %1:gprb(s64) = COPY $x11
192    %2:gprb(s64) = G_UDIV %0, %1
193    $x10 = COPY %2(s64)
194    PseudoRET implicit $x10
195
196...
197---
198name:            urem_i64
199legalized:       true
200regBankSelected: true
201tracksRegLiveness: true
202body:             |
203  bb.0.entry:
204    liveins: $x10, $x11
205
206    ; RV64I-LABEL: name: urem_i64
207    ; RV64I: liveins: $x10, $x11
208    ; RV64I-NEXT: {{  $}}
209    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
210    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
211    ; RV64I-NEXT: [[REMU:%[0-9]+]]:gpr = REMU [[COPY]], [[COPY1]]
212    ; RV64I-NEXT: $x10 = COPY [[REMU]]
213    ; RV64I-NEXT: PseudoRET implicit $x10
214    %0:gprb(s64) = COPY $x10
215    %1:gprb(s64) = COPY $x11
216    %2:gprb(s64) = G_UREM %0, %1
217    $x10 = COPY %2(s64)
218    PseudoRET implicit $x10
219
220...
221---
222name:            mul_i128
223legalized:       true
224regBankSelected: true
225tracksRegLiveness: true
226body:             |
227  bb.0.entry:
228    liveins: $x10, $x11, $x12, $x13
229
230    ; RV64I-LABEL: name: mul_i128
231    ; RV64I: liveins: $x10, $x11, $x12, $x13
232    ; RV64I-NEXT: {{  $}}
233    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
234    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
235    ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
236    ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
237    ; RV64I-NEXT: [[MUL:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY2]]
238    ; RV64I-NEXT: [[MUL1:%[0-9]+]]:gpr = MUL [[COPY1]], [[COPY2]]
239    ; RV64I-NEXT: [[MUL2:%[0-9]+]]:gpr = MUL [[COPY]], [[COPY3]]
240    ; RV64I-NEXT: [[MULHU:%[0-9]+]]:gpr = MULHU [[COPY]], [[COPY2]]
241    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[MUL1]], [[MUL2]]
242    ; RV64I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[ADD]], [[MULHU]]
243    ; RV64I-NEXT: $x10 = COPY [[MUL]]
244    ; RV64I-NEXT: $x11 = COPY [[ADD1]]
245    ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11
246    %0:gprb(s64) = COPY $x10
247    %1:gprb(s64) = COPY $x11
248    %2:gprb(s64) = COPY $x12
249    %3:gprb(s64) = COPY $x13
250    %4:gprb(s64) = G_MUL %0, %2
251    %5:gprb(s64) = G_MUL %1, %2
252    %6:gprb(s64) = G_MUL %0, %3
253    %7:gprb(s64) = G_UMULH %0, %2
254    %8:gprb(s64) = G_ADD %5, %6
255    %9:gprb(s64) = G_ADD %8, %7
256    $x10 = COPY %4(s64)
257    $x11 = COPY %9(s64)
258    PseudoRET implicit $x10, implicit $x11
259
260...
261