xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/alu-rv32.mir (revision b904166aa0cf9a00440076911056ed81d01dfe59) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv32 -mattr=+m -run-pass=regbankselect \
3# RUN:   -simplify-mir -verify-machineinstrs %s \
4# RUN:   -o - | FileCheck -check-prefix=RV32I %s
5
6---
7name:            add_i32
8legalized:       true
9tracksRegLiveness: true
10body:             |
11  bb.0.entry:
12    liveins: $x10, $x11
13
14    ; RV32I-LABEL: name: add_i32
15    ; RV32I: liveins: $x10, $x11
16    ; RV32I-NEXT: {{  $}}
17    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
18    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
19    ; RV32I-NEXT: [[ADD:%[0-9]+]]:gprb(s32) = G_ADD [[COPY]], [[COPY1]]
20    ; RV32I-NEXT: $x10 = COPY [[ADD]](s32)
21    ; RV32I-NEXT: PseudoRET implicit $x10
22    %0:_(s32) = COPY $x10
23    %1:_(s32) = COPY $x11
24    %2:_(s32) = G_ADD %0, %1
25    $x10 = COPY %2(s32)
26    PseudoRET implicit $x10
27
28...
29---
30name:            sub_i32
31legalized:       true
32tracksRegLiveness: true
33body:             |
34  bb.0.entry:
35    liveins: $x10, $x11
36
37    ; RV32I-LABEL: name: sub_i32
38    ; RV32I: liveins: $x10, $x11
39    ; RV32I-NEXT: {{  $}}
40    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
41    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
42    ; RV32I-NEXT: [[SUB:%[0-9]+]]:gprb(s32) = G_SUB [[COPY]], [[COPY1]]
43    ; RV32I-NEXT: $x10 = COPY [[SUB]](s32)
44    ; RV32I-NEXT: PseudoRET implicit $x10
45    %0:_(s32) = COPY $x10
46    %1:_(s32) = COPY $x11
47    %2:_(s32) = G_SUB %0, %1
48    $x10 = COPY %2(s32)
49    PseudoRET implicit $x10
50
51...
52---
53name:            shl_i32
54legalized:       true
55tracksRegLiveness: true
56body:             |
57  bb.0.entry:
58    liveins: $x10, $x11
59
60    ; RV32I-LABEL: name: shl_i32
61    ; RV32I: liveins: $x10, $x11
62    ; RV32I-NEXT: {{  $}}
63    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
64    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
65    ; RV32I-NEXT: [[SHL:%[0-9]+]]:gprb(s32) = G_SHL [[COPY]], [[COPY1]](s32)
66    ; RV32I-NEXT: $x10 = COPY [[SHL]](s32)
67    ; RV32I-NEXT: PseudoRET implicit $x10
68    %0:_(s32) = COPY $x10
69    %1:_(s32) = COPY $x11
70    %2:_(s32) = G_SHL %0, %1
71    $x10 = COPY %2(s32)
72    PseudoRET implicit $x10
73
74...
75---
76name:            ashr_i32
77legalized:       true
78tracksRegLiveness: true
79body:             |
80  bb.0.entry:
81    liveins: $x10, $x11
82
83    ; RV32I-LABEL: name: ashr_i32
84    ; RV32I: liveins: $x10, $x11
85    ; RV32I-NEXT: {{  $}}
86    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
87    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
88    ; RV32I-NEXT: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
89    ; RV32I-NEXT: $x10 = COPY [[ASHR]](s32)
90    ; RV32I-NEXT: PseudoRET implicit $x10
91    %0:_(s32) = COPY $x10
92    %1:_(s32) = COPY $x11
93    %2:_(s32) = G_ASHR %0, %1
94    $x10 = COPY %2(s32)
95    PseudoRET implicit $x10
96
97...
98---
99name:            lshr_i32
100legalized:       true
101tracksRegLiveness: true
102body:             |
103  bb.0.entry:
104    liveins: $x10, $x11
105
106    ; RV32I-LABEL: name: lshr_i32
107    ; RV32I: liveins: $x10, $x11
108    ; RV32I-NEXT: {{  $}}
109    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
110    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
111    ; RV32I-NEXT: [[LSHR:%[0-9]+]]:gprb(s32) = G_LSHR [[COPY]], [[COPY1]](s32)
112    ; RV32I-NEXT: $x10 = COPY [[LSHR]](s32)
113    ; RV32I-NEXT: PseudoRET implicit $x10
114    %0:_(s32) = COPY $x10
115    %1:_(s32) = COPY $x11
116    %2:_(s32) = G_LSHR %0, %1
117    $x10 = COPY %2(s32)
118    PseudoRET implicit $x10
119
120...
121---
122name:            and_i32
123legalized:       true
124tracksRegLiveness: true
125body:             |
126  bb.0.entry:
127    liveins: $x10, $x11
128
129    ; RV32I-LABEL: name: and_i32
130    ; RV32I: liveins: $x10, $x11
131    ; RV32I-NEXT: {{  $}}
132    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
133    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
134    ; RV32I-NEXT: [[AND:%[0-9]+]]:gprb(s32) = G_AND [[COPY]], [[COPY1]]
135    ; RV32I-NEXT: $x10 = COPY [[AND]](s32)
136    ; RV32I-NEXT: PseudoRET implicit $x10
137    %0:_(s32) = COPY $x10
138    %1:_(s32) = COPY $x11
139    %2:_(s32) = G_AND %0, %1
140    $x10 = COPY %2(s32)
141    PseudoRET implicit $x10
142
143...
144---
145name:            or_i32
146legalized:       true
147tracksRegLiveness: true
148body:             |
149  bb.0.entry:
150    liveins: $x10, $x11
151
152    ; RV32I-LABEL: name: or_i32
153    ; RV32I: liveins: $x10, $x11
154    ; RV32I-NEXT: {{  $}}
155    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
156    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
157    ; RV32I-NEXT: [[OR:%[0-9]+]]:gprb(s32) = G_OR [[COPY]], [[COPY1]]
158    ; RV32I-NEXT: $x10 = COPY [[OR]](s32)
159    ; RV32I-NEXT: PseudoRET implicit $x10
160    %0:_(s32) = COPY $x10
161    %1:_(s32) = COPY $x11
162    %2:_(s32) = G_OR %0, %1
163    $x10 = COPY %2(s32)
164    PseudoRET implicit $x10
165
166...
167---
168name:            xor_i32
169legalized:       true
170tracksRegLiveness: true
171body:             |
172  bb.0.entry:
173    liveins: $x10, $x11
174
175    ; RV32I-LABEL: name: xor_i32
176    ; RV32I: liveins: $x10, $x11
177    ; RV32I-NEXT: {{  $}}
178    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
179    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
180    ; RV32I-NEXT: [[XOR:%[0-9]+]]:gprb(s32) = G_XOR [[COPY]], [[COPY1]]
181    ; RV32I-NEXT: $x10 = COPY [[XOR]](s32)
182    ; RV32I-NEXT: PseudoRET implicit $x10
183    %0:_(s32) = COPY $x10
184    %1:_(s32) = COPY $x11
185    %2:_(s32) = G_XOR %0, %1
186    $x10 = COPY %2(s32)
187    PseudoRET implicit $x10
188
189...
190---
191name:            mul_i32
192legalized:       true
193tracksRegLiveness: true
194body:             |
195  bb.0.entry:
196    liveins: $x10, $x11
197
198    ; RV32I-LABEL: name: mul_i32
199    ; RV32I: liveins: $x10, $x11
200    ; RV32I-NEXT: {{  $}}
201    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
202    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
203    ; RV32I-NEXT: [[MUL:%[0-9]+]]:gprb(s32) = G_MUL [[COPY]], [[COPY1]]
204    ; RV32I-NEXT: $x10 = COPY [[MUL]](s32)
205    ; RV32I-NEXT: PseudoRET implicit $x10
206    %0:_(s32) = COPY $x10
207    %1:_(s32) = COPY $x11
208    %2:_(s32) = G_MUL %0, %1
209    $x10 = COPY %2(s32)
210    PseudoRET implicit $x10
211
212...
213---
214name:            sdiv_i32
215legalized:       true
216tracksRegLiveness: true
217body:             |
218  bb.0.entry:
219    liveins: $x10, $x11
220
221    ; RV32I-LABEL: name: sdiv_i32
222    ; RV32I: liveins: $x10, $x11
223    ; RV32I-NEXT: {{  $}}
224    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
225    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
226    ; RV32I-NEXT: [[SDIV:%[0-9]+]]:gprb(s32) = G_SDIV [[COPY]], [[COPY1]]
227    ; RV32I-NEXT: $x10 = COPY [[SDIV]](s32)
228    ; RV32I-NEXT: PseudoRET implicit $x10
229    %0:_(s32) = COPY $x10
230    %1:_(s32) = COPY $x11
231    %2:_(s32) = G_SDIV %0, %1
232    $x10 = COPY %2(s32)
233    PseudoRET implicit $x10
234
235...
236---
237name:            srem_i32
238legalized:       true
239tracksRegLiveness: true
240body:             |
241  bb.0.entry:
242    liveins: $x10, $x11
243
244    ; RV32I-LABEL: name: srem_i32
245    ; RV32I: liveins: $x10, $x11
246    ; RV32I-NEXT: {{  $}}
247    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
248    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
249    ; RV32I-NEXT: [[SREM:%[0-9]+]]:gprb(s32) = G_SREM [[COPY]], [[COPY1]]
250    ; RV32I-NEXT: $x10 = COPY [[SREM]](s32)
251    ; RV32I-NEXT: PseudoRET implicit $x10
252    %0:_(s32) = COPY $x10
253    %1:_(s32) = COPY $x11
254    %2:_(s32) = G_SREM %0, %1
255    $x10 = COPY %2(s32)
256    PseudoRET implicit $x10
257
258...
259---
260name:            smulh_i32
261legalized:       true
262tracksRegLiveness: true
263body:             |
264  bb.0.entry:
265    liveins: $x10, $x11
266
267    ; RV32I-LABEL: name: smulh_i32
268    ; RV32I: liveins: $x10, $x11
269    ; RV32I-NEXT: {{  $}}
270    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
271    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
272    ; RV32I-NEXT: [[SMULH:%[0-9]+]]:gprb(s32) = G_SMULH [[COPY]], [[COPY1]]
273    ; RV32I-NEXT: $x10 = COPY [[SMULH]](s32)
274    ; RV32I-NEXT: PseudoRET implicit $x10
275    %0:_(s32) = COPY $x10
276    %1:_(s32) = COPY $x11
277    %2:_(s32) = G_SMULH %0, %1
278    $x10 = COPY %2(s32)
279    PseudoRET implicit $x10
280
281...
282---
283name:            udiv_i32
284legalized:       true
285tracksRegLiveness: true
286body:             |
287  bb.0.entry:
288    liveins: $x10, $x11
289
290    ; RV32I-LABEL: name: udiv_i32
291    ; RV32I: liveins: $x10, $x11
292    ; RV32I-NEXT: {{  $}}
293    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
294    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
295    ; RV32I-NEXT: [[UDIV:%[0-9]+]]:gprb(s32) = G_UDIV [[COPY]], [[COPY1]]
296    ; RV32I-NEXT: $x10 = COPY [[UDIV]](s32)
297    ; RV32I-NEXT: PseudoRET implicit $x10
298    %0:_(s32) = COPY $x10
299    %1:_(s32) = COPY $x11
300    %2:_(s32) = G_UDIV %0, %1
301    $x10 = COPY %2(s32)
302    PseudoRET implicit $x10
303
304...
305---
306name:            urem_i32
307legalized:       true
308tracksRegLiveness: true
309body:             |
310  bb.0.entry:
311    liveins: $x10, $x11
312
313    ; RV32I-LABEL: name: urem_i32
314    ; RV32I: liveins: $x10, $x11
315    ; RV32I-NEXT: {{  $}}
316    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
317    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
318    ; RV32I-NEXT: [[UREM:%[0-9]+]]:gprb(s32) = G_UREM [[COPY]], [[COPY1]]
319    ; RV32I-NEXT: $x10 = COPY [[UREM]](s32)
320    ; RV32I-NEXT: PseudoRET implicit $x10
321    %0:_(s32) = COPY $x10
322    %1:_(s32) = COPY $x11
323    %2:_(s32) = G_UREM %0, %1
324    $x10 = COPY %2(s32)
325    PseudoRET implicit $x10
326
327...
328---
329name:            umulh_i32
330legalized:       true
331tracksRegLiveness: true
332body:             |
333  bb.0.entry:
334    liveins: $x10, $x11
335
336    ; RV32I-LABEL: name: umulh_i32
337    ; RV32I: liveins: $x10, $x11
338    ; RV32I-NEXT: {{  $}}
339    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
340    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
341    ; RV32I-NEXT: [[UMULH:%[0-9]+]]:gprb(s32) = G_UMULH [[COPY]], [[COPY1]]
342    ; RV32I-NEXT: $x10 = COPY [[UMULH]](s32)
343    ; RV32I-NEXT: PseudoRET implicit $x10
344    %0:_(s32) = COPY $x10
345    %1:_(s32) = COPY $x11
346    %2:_(s32) = G_UMULH %0, %1
347    $x10 = COPY %2(s32)
348    PseudoRET implicit $x10
349
350...
351---
352name:            icmp_i32
353legalized:       true
354tracksRegLiveness: true
355body:             |
356  bb.0.entry:
357    liveins: $x10, $x11
358
359    ; RV32I-LABEL: name: icmp_i32
360    ; RV32I: liveins: $x10, $x11
361    ; RV32I-NEXT: {{  $}}
362    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
363    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
364    ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
365    ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32)
366    ; RV32I-NEXT: PseudoRET implicit $x10
367    %0:_(s32) = COPY $x10
368    %1:_(s32) = COPY $x11
369    %2:_(s32) = G_ICMP intpred(eq), %0(s32), %1
370    $x10 = COPY %2(s32)
371    PseudoRET implicit $x10
372
373...
374---
375name:            icmp_ptr
376legalized:       true
377tracksRegLiveness: true
378body:             |
379  bb.0.entry:
380    liveins: $x10, $x11
381
382    ; RV32I-LABEL: name: icmp_ptr
383    ; RV32I: liveins: $x10, $x11
384    ; RV32I-NEXT: {{  $}}
385    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
386    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(p0) = COPY $x11
387    ; RV32I-NEXT: [[ICMP:%[0-9]+]]:gprb(s32) = G_ICMP intpred(eq), [[COPY]](p0), [[COPY1]]
388    ; RV32I-NEXT: $x10 = COPY [[ICMP]](s32)
389    ; RV32I-NEXT: PseudoRET implicit $x10
390    %0:_(p0) = COPY $x10
391    %1:_(p0) = COPY $x11
392    %2:_(s32) = G_ICMP intpred(eq), %0(p0), %1
393    $x10 = COPY %2(s32)
394    PseudoRET implicit $x10
395
396...
397---
398name:            gep
399legalized:       true
400tracksRegLiveness: true
401body:             |
402  bb.0.entry:
403    liveins: $x10, $x11
404
405    ; RV32I-LABEL: name: gep
406    ; RV32I: liveins: $x10, $x11
407    ; RV32I-NEXT: {{  $}}
408    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
409    ; RV32I-NEXT: [[COPY1:%[0-9]+]]:gprb(s32) = COPY $x11
410    ; RV32I-NEXT: [[PTR_ADD:%[0-9]+]]:gprb(p0) = G_PTR_ADD [[COPY]], [[COPY1]](s32)
411    ; RV32I-NEXT: $x10 = COPY [[PTR_ADD]](p0)
412    ; RV32I-NEXT: PseudoRET implicit $x10
413    %0:_(p0) = COPY $x10
414    %1:_(s32) = COPY $x11
415    %2:_(p0) = G_PTR_ADD %0, %1(s32)
416    $x10 = COPY %2(p0)
417    PseudoRET implicit $x10
418
419...
420---
421name:            ptrtoint
422legalized:       true
423tracksRegLiveness: true
424body:             |
425  bb.0.entry:
426    liveins: $x10
427
428    ; RV32I-LABEL: name: ptrtoint
429    ; RV32I: liveins: $x10
430    ; RV32I-NEXT: {{  $}}
431    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(p0) = COPY $x10
432    ; RV32I-NEXT: [[PTRTOINT:%[0-9]+]]:gprb(s32) = G_PTRTOINT [[COPY]](p0)
433    ; RV32I-NEXT: $x10 = COPY [[PTRTOINT]](s32)
434    ; RV32I-NEXT: PseudoRET implicit $x10
435    %0:_(p0) = COPY $x10
436    %1:_(s32) = G_PTRTOINT %0(p0)
437    $x10 = COPY %1(s32)
438    PseudoRET implicit $x10
439
440...
441---
442name:            inttoprt
443legalized:       true
444tracksRegLiveness: true
445body:             |
446  bb.0.entry:
447    liveins: $x10
448
449    ; RV32I-LABEL: name: inttoprt
450    ; RV32I: liveins: $x10
451    ; RV32I-NEXT: {{  $}}
452    ; RV32I-NEXT: [[COPY:%[0-9]+]]:gprb(s32) = COPY $x10
453    ; RV32I-NEXT: [[INTTOPTR:%[0-9]+]]:gprb(p0) = G_INTTOPTR [[COPY]](s32)
454    ; RV32I-NEXT: $x10 = COPY [[INTTOPTR]](p0)
455    ; RV32I-NEXT: PseudoRET implicit $x10
456    %0:_(s32) = COPY $x10
457    %1:_(p0) = G_INTTOPTR %0(s32)
458    $x10 = COPY %1(p0)
459    PseudoRET implicit $x10
460
461...
462