xref: /llvm-project/llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu-rv64.mir (revision d1e17a3f23a30815030b784d813141a469b3d7fb) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=riscv64 -run-pass=instruction-select -simplify-mir -verify-machineinstrs %s -o - \
3# RUN: | FileCheck -check-prefix=RV64I %s
4
5---
6name:            sll_i32
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0.entry:
12    liveins: $x10, $x11
13
14    ; RV64I-LABEL: name: sll_i32
15    ; RV64I: liveins: $x10, $x11
16    ; RV64I-NEXT: {{  $}}
17    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
18    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
19    ; RV64I-NEXT: [[SLLW:%[0-9]+]]:gpr = SLLW [[COPY]], [[COPY1]]
20    ; RV64I-NEXT: $x10 = COPY [[SLLW]]
21    ; RV64I-NEXT: PseudoRET implicit $x10
22    %0:gprb(s64) = COPY $x10
23    %1:gprb(s64) = COPY $x11
24    %2:gprb(s64) = G_SLLW %0, %1
25    $x10 = COPY %2(s64)
26    PseudoRET implicit $x10
27
28...
29---
30name:            slli_i32
31legalized:       true
32regBankSelected: true
33tracksRegLiveness: true
34body:             |
35  bb.0.entry:
36    liveins: $x10
37
38    ; RV64I-LABEL: name: slli_i32
39    ; RV64I: liveins: $x10
40    ; RV64I-NEXT: {{  $}}
41    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
42    ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 31
43    ; RV64I-NEXT: $x10 = COPY [[SLLI]]
44    ; RV64I-NEXT: PseudoRET implicit $x10
45    %0:gprb(s64) = COPY $x10
46    %1:gprb(s64) = G_CONSTANT i64 31
47    %2:gprb(s64) = G_SHL %0, %1
48    $x10 = COPY %2(s64)
49    PseudoRET implicit $x10
50
51...
52---
53name:            sra_i32
54legalized:       true
55regBankSelected: true
56tracksRegLiveness: true
57body:             |
58  bb.0.entry:
59    liveins: $x10, $x11
60
61    ; RV64I-LABEL: name: sra_i32
62    ; RV64I: liveins: $x10, $x11
63    ; RV64I-NEXT: {{  $}}
64    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
65    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
66    ; RV64I-NEXT: [[SRAW:%[0-9]+]]:gpr = SRAW [[COPY]], [[COPY1]]
67    ; RV64I-NEXT: $x10 = COPY [[SRAW]]
68    ; RV64I-NEXT: PseudoRET implicit $x10
69    %0:gprb(s64) = COPY $x10
70    %1:gprb(s64) = COPY $x11
71    %2:gprb(s64) = G_SRAW %0, %1
72    $x10 = COPY %2(s64)
73    PseudoRET implicit $x10
74
75...
76---
77name:            srai_i32
78legalized:       true
79regBankSelected: true
80tracksRegLiveness: true
81body:             |
82  bb.0.entry:
83    liveins: $x10
84
85    ; RV64I-LABEL: name: srai_i32
86    ; RV64I: liveins: $x10
87    ; RV64I-NEXT: {{  $}}
88    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
89    ; RV64I-NEXT: [[SRAIW:%[0-9]+]]:gpr = SRAIW [[COPY]], 31
90    ; RV64I-NEXT: $x10 = COPY [[SRAIW]]
91    ; RV64I-NEXT: PseudoRET implicit $x10
92    %0:gprb(s64) = COPY $x10
93    %1:gprb(s64) = G_CONSTANT i64 31
94    %2:gprb(s64) = G_SEXT_INREG %0, 32
95    %3:gprb(s64) = G_ASHR %2, %1(s64)
96    $x10 = COPY %3(s64)
97    PseudoRET implicit $x10
98
99...
100---
101name:            srl_i32
102legalized:       true
103regBankSelected: true
104tracksRegLiveness: true
105body:             |
106  bb.0.entry:
107    liveins: $x10, $x11
108
109    ; RV64I-LABEL: name: srl_i32
110    ; RV64I: liveins: $x10, $x11
111    ; RV64I-NEXT: {{  $}}
112    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
113    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
114    ; RV64I-NEXT: [[SRLW:%[0-9]+]]:gpr = SRLW [[COPY]], [[COPY1]]
115    ; RV64I-NEXT: $x10 = COPY [[SRLW]]
116    ; RV64I-NEXT: PseudoRET implicit $x10
117    %0:gprb(s64) = COPY $x10
118    %1:gprb(s64) = COPY $x11
119    %2:gprb(s64) = G_SRLW %0, %1
120    $x10 = COPY %2(s64)
121    PseudoRET implicit $x10
122
123...
124---
125name:            srli_i32
126legalized:       true
127regBankSelected: true
128tracksRegLiveness: true
129body:             |
130  bb.0.entry:
131    liveins: $x10
132
133    ; RV64I-LABEL: name: srli_i32
134    ; RV64I: liveins: $x10
135    ; RV64I-NEXT: {{  $}}
136    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
137    ; RV64I-NEXT: [[SRLIW:%[0-9]+]]:gpr = SRLIW [[COPY]], 31
138    ; RV64I-NEXT: $x10 = COPY [[SRLIW]]
139    ; RV64I-NEXT: PseudoRET implicit $x10
140    %0:gprb(s64) = COPY $x10
141    %1:gprb(s64) = G_CONSTANT i64 31
142    %2:gprb(s64) = G_CONSTANT i64 4294967295
143    %3:gprb(s64) = G_AND %0, %2
144    %4:gprb(s64) = G_LSHR %3, %1(s64)
145    $x10 = COPY %4(s64)
146    PseudoRET implicit $x10
147
148...
149---
150name:            add_i64
151legalized:       true
152regBankSelected: true
153tracksRegLiveness: true
154body:             |
155  bb.0.entry:
156    liveins: $x10, $x11
157
158    ; RV64I-LABEL: name: add_i64
159    ; RV64I: liveins: $x10, $x11
160    ; RV64I-NEXT: {{  $}}
161    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
162    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
163    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY1]]
164    ; RV64I-NEXT: $x10 = COPY [[ADD]]
165    ; RV64I-NEXT: PseudoRET implicit $x10
166    %0:gprb(s64) = COPY $x10
167    %1:gprb(s64) = COPY $x11
168    %2:gprb(s64) = G_ADD %0, %1
169    $x10 = COPY %2(s64)
170    PseudoRET implicit $x10
171
172...
173---
174name:            addi_i64
175legalized:       true
176regBankSelected: true
177tracksRegLiveness: true
178body:             |
179  bb.0.entry:
180    liveins: $x10
181
182    ; RV64I-LABEL: name: addi_i64
183    ; RV64I: liveins: $x10
184    ; RV64I-NEXT: {{  $}}
185    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
186    ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI [[COPY]], 1234
187    ; RV64I-NEXT: $x10 = COPY [[ADDI]]
188    ; RV64I-NEXT: PseudoRET implicit $x10
189    %0:gprb(s64) = COPY $x10
190    %1:gprb(s64) = G_CONSTANT i64 1234
191    %2:gprb(s64) = G_ADD %0, %1
192    $x10 = COPY %2(s64)
193    PseudoRET implicit $x10
194
195...
196---
197name:            sub_i64
198legalized:       true
199regBankSelected: true
200tracksRegLiveness: true
201body:             |
202  bb.0.entry:
203    liveins: $x10, $x11
204
205    ; RV64I-LABEL: name: sub_i64
206    ; RV64I: liveins: $x10, $x11
207    ; RV64I-NEXT: {{  $}}
208    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
209    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
210    ; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY1]]
211    ; RV64I-NEXT: $x10 = COPY [[SUB]]
212    ; RV64I-NEXT: PseudoRET implicit $x10
213    %0:gprb(s64) = COPY $x10
214    %1:gprb(s64) = COPY $x11
215    %2:gprb(s64) = G_SUB %0, %1
216    $x10 = COPY %2(s64)
217    PseudoRET implicit $x10
218
219...
220---
221name:            subi_i64
222legalized:       true
223regBankSelected: true
224tracksRegLiveness: true
225body:             |
226  bb.0.entry:
227    liveins: $x10
228
229    ; RV64I-LABEL: name: subi_i64
230    ; RV64I: liveins: $x10
231    ; RV64I-NEXT: {{  $}}
232    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
233    ; RV64I-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI $x0, -1234
234    ; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[ADDI]]
235    ; RV64I-NEXT: $x10 = COPY [[SUB]]
236    ; RV64I-NEXT: PseudoRET implicit $x10
237    %0:gprb(s64) = COPY $x10
238    %1:gprb(s64) = G_CONSTANT i64 -1234
239    %2:gprb(s64) = G_SUB %0, %1
240    $x10 = COPY %2(s64)
241    PseudoRET implicit $x10
242
243...
244---
245name:            sll_i64
246legalized:       true
247regBankSelected: true
248tracksRegLiveness: true
249body:             |
250  bb.0.entry:
251    liveins: $x10, $x11
252
253    ; RV64I-LABEL: name: sll_i64
254    ; RV64I: liveins: $x10, $x11
255    ; RV64I-NEXT: {{  $}}
256    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
257    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
258    ; RV64I-NEXT: [[SLL:%[0-9]+]]:gpr = SLL [[COPY]], [[COPY1]]
259    ; RV64I-NEXT: $x10 = COPY [[SLL]]
260    ; RV64I-NEXT: PseudoRET implicit $x10
261    %0:gprb(s64) = COPY $x10
262    %1:gprb(s64) = COPY $x11
263    %2:gprb(s64) = G_SHL %0, %1
264    $x10 = COPY %2(s64)
265    PseudoRET implicit $x10
266
267...
268---
269name:            slli_i64
270legalized:       true
271regBankSelected: true
272tracksRegLiveness: true
273body:             |
274  bb.0.entry:
275    liveins: $x10
276
277    ; RV64I-LABEL: name: slli_i64
278    ; RV64I: liveins: $x10
279    ; RV64I-NEXT: {{  $}}
280    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
281    ; RV64I-NEXT: [[SLLI:%[0-9]+]]:gpr = SLLI [[COPY]], 63
282    ; RV64I-NEXT: $x10 = COPY [[SLLI]]
283    ; RV64I-NEXT: PseudoRET implicit $x10
284    %0:gprb(s64) = COPY $x10
285    %1:gprb(s64) = G_CONSTANT i64 63
286    %2:gprb(s64) = G_SHL %0, %1
287    $x10 = COPY %2(s64)
288    PseudoRET implicit $x10
289
290...
291---
292name:            sra_i64
293legalized:       true
294regBankSelected: true
295tracksRegLiveness: true
296body:             |
297  bb.0.entry:
298    liveins: $x10, $x11
299
300    ; RV64I-LABEL: name: sra_i64
301    ; RV64I: liveins: $x10, $x11
302    ; RV64I-NEXT: {{  $}}
303    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
304    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
305    ; RV64I-NEXT: [[SRA:%[0-9]+]]:gpr = SRA [[COPY]], [[COPY1]]
306    ; RV64I-NEXT: $x10 = COPY [[SRA]]
307    ; RV64I-NEXT: PseudoRET implicit $x10
308    %0:gprb(s64) = COPY $x10
309    %1:gprb(s64) = COPY $x11
310    %2:gprb(s64) = G_ASHR %0, %1
311    $x10 = COPY %2(s64)
312    PseudoRET implicit $x10
313
314...
315---
316name:            srai_i64
317legalized:       true
318regBankSelected: true
319tracksRegLiveness: true
320body:             |
321  bb.0.entry:
322    liveins: $x10
323
324    ; RV64I-LABEL: name: srai_i64
325    ; RV64I: liveins: $x10
326    ; RV64I-NEXT: {{  $}}
327    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
328    ; RV64I-NEXT: [[SRAI:%[0-9]+]]:gpr = SRAI [[COPY]], 63
329    ; RV64I-NEXT: $x10 = COPY [[SRAI]]
330    ; RV64I-NEXT: PseudoRET implicit $x10
331    %0:gprb(s64) = COPY $x10
332    %1:gprb(s64) = G_CONSTANT i64 63
333    %2:gprb(s64) = G_ASHR %0, %1
334    $x10 = COPY %2(s64)
335    PseudoRET implicit $x10
336
337...
338---
339name:            lshr_i64
340legalized:       true
341regBankSelected: true
342tracksRegLiveness: true
343body:             |
344  bb.0.entry:
345    liveins: $x10, $x11
346
347    ; RV64I-LABEL: name: lshr_i64
348    ; RV64I: liveins: $x10, $x11
349    ; RV64I-NEXT: {{  $}}
350    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
351    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
352    ; RV64I-NEXT: [[SRL:%[0-9]+]]:gpr = SRL [[COPY]], [[COPY1]]
353    ; RV64I-NEXT: $x10 = COPY [[SRL]]
354    ; RV64I-NEXT: PseudoRET implicit $x10
355    %0:gprb(s64) = COPY $x10
356    %1:gprb(s64) = COPY $x11
357    %2:gprb(s64) = G_LSHR %0, %1
358    $x10 = COPY %2(s64)
359    PseudoRET implicit $x10
360
361...
362---
363name:            srli_i64
364legalized:       true
365regBankSelected: true
366tracksRegLiveness: true
367body:             |
368  bb.0.entry:
369    liveins: $x10
370
371    ; RV64I-LABEL: name: srli_i64
372    ; RV64I: liveins: $x10
373    ; RV64I-NEXT: {{  $}}
374    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
375    ; RV64I-NEXT: [[SRLI:%[0-9]+]]:gpr = SRLI [[COPY]], 63
376    ; RV64I-NEXT: $x10 = COPY [[SRLI]]
377    ; RV64I-NEXT: PseudoRET implicit $x10
378    %0:gprb(s64) = COPY $x10
379    %1:gprb(s64) = G_CONSTANT i64 63
380    %2:gprb(s64) = G_LSHR %0, %1
381    $x10 = COPY %2(s64)
382    PseudoRET implicit $x10
383
384...
385---
386name:            and_i64
387legalized:       true
388regBankSelected: true
389tracksRegLiveness: true
390body:             |
391  bb.0.entry:
392    liveins: $x10, $x11
393
394    ; RV64I-LABEL: name: and_i64
395    ; RV64I: liveins: $x10, $x11
396    ; RV64I-NEXT: {{  $}}
397    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
398    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
399    ; RV64I-NEXT: [[AND:%[0-9]+]]:gpr = AND [[COPY]], [[COPY1]]
400    ; RV64I-NEXT: $x10 = COPY [[AND]]
401    ; RV64I-NEXT: PseudoRET implicit $x10
402    %0:gprb(s64) = COPY $x10
403    %1:gprb(s64) = COPY $x11
404    %2:gprb(s64) = G_AND %0, %1
405    $x10 = COPY %2(s64)
406    PseudoRET implicit $x10
407
408...
409---
410name:            andi_i64
411legalized:       true
412regBankSelected: true
413tracksRegLiveness: true
414body:             |
415  bb.0.entry:
416    liveins: $x10
417
418    ; RV64I-LABEL: name: andi_i64
419    ; RV64I: liveins: $x10
420    ; RV64I-NEXT: {{  $}}
421    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
422    ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[COPY]], 1234
423    ; RV64I-NEXT: $x10 = COPY [[ANDI]]
424    ; RV64I-NEXT: PseudoRET implicit $x10
425    %0:gprb(s64) = COPY $x10
426    %1:gprb(s64) = G_CONSTANT i64 1234
427    %2:gprb(s64) = G_AND %0, %1
428    $x10 = COPY %2(s64)
429    PseudoRET implicit $x10
430
431...
432---
433name:            or_i64
434legalized:       true
435regBankSelected: true
436tracksRegLiveness: true
437body:             |
438  bb.0.entry:
439    liveins: $x10, $x11
440
441    ; RV64I-LABEL: name: or_i64
442    ; RV64I: liveins: $x10, $x11
443    ; RV64I-NEXT: {{  $}}
444    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
445    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
446    ; RV64I-NEXT: [[OR:%[0-9]+]]:gpr = OR [[COPY]], [[COPY1]]
447    ; RV64I-NEXT: $x10 = COPY [[OR]]
448    ; RV64I-NEXT: PseudoRET implicit $x10
449    %0:gprb(s64) = COPY $x10
450    %1:gprb(s64) = COPY $x11
451    %2:gprb(s64) = G_OR %0, %1
452    $x10 = COPY %2(s64)
453    PseudoRET implicit $x10
454
455...
456---
457name:            ori_i64
458legalized:       true
459regBankSelected: true
460tracksRegLiveness: true
461body:             |
462  bb.0.entry:
463    liveins: $x10
464
465    ; RV64I-LABEL: name: ori_i64
466    ; RV64I: liveins: $x10
467    ; RV64I-NEXT: {{  $}}
468    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
469    ; RV64I-NEXT: [[ORI:%[0-9]+]]:gpr = ORI [[COPY]], 1234
470    ; RV64I-NEXT: $x10 = COPY [[ORI]]
471    ; RV64I-NEXT: PseudoRET implicit $x10
472    %0:gprb(s64) = COPY $x10
473    %1:gprb(s64) = G_CONSTANT i64 1234
474    %2:gprb(s64) = G_OR %0, %1
475    $x10 = COPY %2(s64)
476    PseudoRET implicit $x10
477
478...
479---
480name:            xor_i64
481legalized:       true
482regBankSelected: true
483tracksRegLiveness: true
484body:             |
485  bb.0.entry:
486    liveins: $x10, $x11
487
488    ; RV64I-LABEL: name: xor_i64
489    ; RV64I: liveins: $x10, $x11
490    ; RV64I-NEXT: {{  $}}
491    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
492    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
493    ; RV64I-NEXT: [[XOR:%[0-9]+]]:gpr = XOR [[COPY]], [[COPY1]]
494    ; RV64I-NEXT: $x10 = COPY [[XOR]]
495    ; RV64I-NEXT: PseudoRET implicit $x10
496    %0:gprb(s64) = COPY $x10
497    %1:gprb(s64) = COPY $x11
498    %2:gprb(s64) = G_XOR %0, %1
499    $x10 = COPY %2(s64)
500    PseudoRET implicit $x10
501
502...
503---
504name:            xori_i64
505legalized:       true
506regBankSelected: true
507tracksRegLiveness: true
508body:             |
509  bb.0.entry:
510    liveins: $x10
511
512    ; RV64I-LABEL: name: xori_i64
513    ; RV64I: liveins: $x10
514    ; RV64I-NEXT: {{  $}}
515    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
516    ; RV64I-NEXT: [[XORI:%[0-9]+]]:gpr = XORI [[COPY]], 1234
517    ; RV64I-NEXT: $x10 = COPY [[XORI]]
518    ; RV64I-NEXT: PseudoRET implicit $x10
519    %0:gprb(s64) = COPY $x10
520    %1:gprb(s64) = G_CONSTANT i64 1234
521    %2:gprb(s64) = G_XOR %0, %1
522    $x10 = COPY %2(s64)
523    PseudoRET implicit $x10
524
525...
526---
527name:            add_i128
528legalized:       true
529regBankSelected: true
530tracksRegLiveness: true
531body:             |
532  bb.0.entry:
533    liveins: $x10, $x11, $x12, $x13
534
535    ; RV64I-LABEL: name: add_i128
536    ; RV64I: liveins: $x10, $x11, $x12, $x13
537    ; RV64I-NEXT: {{  $}}
538    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
539    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
540    ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
541    ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
542    ; RV64I-NEXT: [[ADD:%[0-9]+]]:gpr = ADD [[COPY]], [[COPY2]]
543    ; RV64I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[ADD]], [[COPY2]]
544    ; RV64I-NEXT: [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY3]]
545    ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
546    ; RV64I-NEXT: [[ADD2:%[0-9]+]]:gpr = ADD [[ADD1]], [[ANDI]]
547    ; RV64I-NEXT: $x10 = COPY [[ADD]]
548    ; RV64I-NEXT: $x11 = COPY [[ADD2]]
549    ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11
550    %0:gprb(s64) = COPY $x10
551    %1:gprb(s64) = COPY $x11
552    %2:gprb(s64) = COPY $x12
553    %3:gprb(s64) = COPY $x13
554    %4:gprb(s64) = G_ADD %0, %2
555    %5:gprb(s64) = G_ICMP intpred(ult), %4(s64), %2
556    %6:gprb(s64) = G_ADD %1, %3
557    %7:gprb(s64) = G_CONSTANT i64 1
558    %8:gprb(s64) = G_AND %5, %7
559    %9:gprb(s64) = G_ADD %6, %8
560    $x10 = COPY %4(s64)
561    $x11 = COPY %9(s64)
562    PseudoRET implicit $x10, implicit $x11
563
564...
565---
566name:            sub_i128
567legalized:       true
568regBankSelected: true
569tracksRegLiveness: true
570body:             |
571  bb.0.entry:
572    liveins: $x10, $x11, $x12, $x13
573
574    ; RV64I-LABEL: name: sub_i128
575    ; RV64I: liveins: $x10, $x11, $x12, $x13
576    ; RV64I-NEXT: {{  $}}
577    ; RV64I-NEXT: [[COPY:%[0-9]+]]:gpr = COPY $x10
578    ; RV64I-NEXT: [[COPY1:%[0-9]+]]:gpr = COPY $x11
579    ; RV64I-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $x12
580    ; RV64I-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY $x13
581    ; RV64I-NEXT: [[SUB:%[0-9]+]]:gpr = SUB [[COPY]], [[COPY2]]
582    ; RV64I-NEXT: [[SLTU:%[0-9]+]]:gpr = SLTU [[COPY]], [[COPY2]]
583    ; RV64I-NEXT: [[SUB1:%[0-9]+]]:gpr = SUB [[COPY1]], [[COPY3]]
584    ; RV64I-NEXT: [[ANDI:%[0-9]+]]:gpr = ANDI [[SLTU]], 1
585    ; RV64I-NEXT: [[SUB2:%[0-9]+]]:gpr = SUB [[SUB1]], [[ANDI]]
586    ; RV64I-NEXT: $x10 = COPY [[SUB]]
587    ; RV64I-NEXT: $x11 = COPY [[SUB2]]
588    ; RV64I-NEXT: PseudoRET implicit $x10, implicit $x11
589    %0:gprb(s64) = COPY $x10
590    %1:gprb(s64) = COPY $x11
591    %2:gprb(s64) = COPY $x12
592    %3:gprb(s64) = COPY $x13
593    %4:gprb(s64) = G_SUB %0, %2
594    %5:gprb(s64) = G_ICMP intpred(ult), %0(s64), %2
595    %6:gprb(s64) = G_SUB %1, %3
596    %7:gprb(s64) = G_CONSTANT i64 1
597    %8:gprb(s64) = G_AND %5, %7
598    %9:gprb(s64) = G_SUB %6, %8
599    $x10 = COPY %4(s64)
600    $x11 = COPY %9(s64)
601    PseudoRET implicit $x10, implicit $x11
602
603...
604