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Searched refs:ras (Results 1 – 25 of 80) sorted by relevance

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/openbsd-src/sys/dev/pci/drm/amd/amdgpu/
H A Damdgpu_mca.c77 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp0_ras_sw_init() local
79 if (!adev->mca.mp0.ras) in amdgpu_mca_mp0_ras_sw_init()
82 ras = adev->mca.mp0.ras; in amdgpu_mca_mp0_ras_sw_init()
84 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mca_mp0_ras_sw_init()
90 strlcpy(ras->ras_block.ras_comm.name, "mca.mp0", in amdgpu_mca_mp0_ras_sw_init()
91 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_mca_mp0_ras_sw_init()
92 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MCA; in amdgpu_mca_mp0_ras_sw_init()
93 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mca_mp0_ras_sw_init()
94 adev->mca.mp0.ras_if = &ras->ras_block.ras_comm; in amdgpu_mca_mp0_ras_sw_init()
102 struct amdgpu_mca_ras_block *ras; in amdgpu_mca_mp1_ras_sw_init() local
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H A Damdgpu_umc.c91 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
92 adev->umc.ras->ras_block.hw_ops->query_ras_error_count) in amdgpu_umc_do_page_retirement()
93 adev->umc.ras->ras_block.hw_ops->query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
95 if (adev->umc.ras && adev->umc.ras->ras_block.hw_ops && in amdgpu_umc_do_page_retirement()
96 adev->umc.ras->ras_block.hw_ops->query_ras_error_address && in amdgpu_umc_do_page_retirement()
112 adev->umc.ras->ras_block.hw_ops->query_ras_error_address(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
115 if (adev->umc.ras && in amdgpu_umc_do_page_retirement()
116 adev->umc.ras->ecc_info_query_ras_error_count) in amdgpu_umc_do_page_retirement()
117 adev->umc.ras->ecc_info_query_ras_error_count(adev, ras_error_status); in amdgpu_umc_do_page_retirement()
119 if (adev->umc.ras && in amdgpu_umc_do_page_retirement()
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H A Damdgpu_hdp.c29 struct amdgpu_hdp_ras *ras; in amdgpu_hdp_ras_sw_init() local
31 if (!adev->hdp.ras) in amdgpu_hdp_ras_sw_init()
34 ras = adev->hdp.ras; in amdgpu_hdp_ras_sw_init()
35 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_hdp_ras_sw_init()
41 strlcpy(ras->ras_block.ras_comm.name, "hdp", in amdgpu_hdp_ras_sw_init()
42 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_hdp_ras_sw_init()
43 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP; in amdgpu_hdp_ras_sw_init()
44 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_hdp_ras_sw_init()
45 adev->hdp.ras_if = &ras->ras_block.ras_comm; in amdgpu_hdp_ras_sw_init()
H A Damdgpu_mmhub.c27 struct amdgpu_mmhub_ras *ras; in amdgpu_mmhub_ras_sw_init() local
29 if (!adev->mmhub.ras) in amdgpu_mmhub_ras_sw_init()
32 ras = adev->mmhub.ras; in amdgpu_mmhub_ras_sw_init()
33 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_mmhub_ras_sw_init()
39 strlcpy(ras->ras_block.ras_comm.name, "mmhub", in amdgpu_mmhub_ras_sw_init()
40 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_mmhub_ras_sw_init()
41 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__MMHUB; in amdgpu_mmhub_ras_sw_init()
42 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_mmhub_ras_sw_init()
43 adev->mmhub.ras_if = &ras->ras_block.ras_comm; in amdgpu_mmhub_ras_sw_init()
H A Damdgpu_nbio.c28 struct amdgpu_nbio_ras *ras; in amdgpu_nbio_ras_sw_init() local
30 if (!adev->nbio.ras) in amdgpu_nbio_ras_sw_init()
33 ras = adev->nbio.ras; in amdgpu_nbio_ras_sw_init()
34 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_nbio_ras_sw_init()
40 strlcpy(ras->ras_block.ras_comm.name, "pcie_bif", in amdgpu_nbio_ras_sw_init()
41 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_nbio_ras_sw_init()
42 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__PCIE_BIF; in amdgpu_nbio_ras_sw_init()
43 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_nbio_ras_sw_init()
44 adev->nbio.ras_if = &ras->ras_block.ras_comm; in amdgpu_nbio_ras_sw_init()
H A Damdgpu_sdma.c316 struct amdgpu_sdma_ras *ras = NULL; in amdgpu_sdma_ras_sw_init() local
321 if (!adev->sdma.ras) in amdgpu_sdma_ras_sw_init()
324 ras = adev->sdma.ras; in amdgpu_sdma_ras_sw_init()
326 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_sdma_ras_sw_init()
332 strlcpy(ras->ras_block.ras_comm.name, "sdma", in amdgpu_sdma_ras_sw_init()
333 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_sdma_ras_sw_init()
334 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__SDMA; in amdgpu_sdma_ras_sw_init()
335 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_sdma_ras_sw_init()
336 adev->sdma.ras_if = &ras->ras_block.ras_comm; in amdgpu_sdma_ras_sw_init()
339 if (!ras->ras_block.ras_late_init) in amdgpu_sdma_ras_sw_init()
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H A Damdgpu_jpeg.c277 struct amdgpu_jpeg_ras *ras; in amdgpu_jpeg_ras_sw_init() local
279 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
282 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
283 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_jpeg_ras_sw_init()
289 strlcpy(ras->ras_block.ras_comm.name, "jpeg", in amdgpu_jpeg_ras_sw_init()
290 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_jpeg_ras_sw_init()
291 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__JPEG; in amdgpu_jpeg_ras_sw_init()
292 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__POISON; in amdgpu_jpeg_ras_sw_init()
293 adev->jpeg.ras_if = &ras->ras_block.ras_comm; in amdgpu_jpeg_ras_sw_init()
295 if (!ras->ras_block.ras_late_init) in amdgpu_jpeg_ras_sw_init()
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H A Damdgpu_ras.c47 static const char *RAS_FS_NAME = "ras";
85 /* ras block link */
185 dev_warn(adev->dev, " echo 1 > /sys/kernel/debug/dri/0/ras/ras_eeprom_reset\n"); in amdgpu_reserve_page_direct()
415 * echo "disable <block>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
416 * echo "enable <block> <error>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
417 * echo "inject <block> <error> <sub-block> <address> <value> <mask>" > /sys/kernel/debug/dri/<N>/ras/ras_ctrl
440 * echo inject umc ue 0x0 0x0 0x0 > /sys/kernel/debug/dri/0/ras/ras_ctrl
441 * echo inject umc ce 0 0 0 3 > /sys/kernel/debug/dri/0/ras/ras_ctrl
442 * echo disable umc > /sys/kernel/debug/dri/0/ras/ras_ctrl
446 * To check disable/enable, see "ras" feature
991 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_get_ecc_info() local
2045 struct amdgpu_ras *ras = amdgpu_ras_do_recovery() local
3006 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_global_ras_isr() local
3165 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_is_supported() local
3192 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); amdgpu_ras_reset_gpu() local
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H A Damdgpu_ras_eeprom.c426 if (adev->umc.ras && in amdgpu_ras_eeprom_reset_table()
427 adev->umc.ras->set_eeprom_table_version) in amdgpu_ras_eeprom_reset_table()
428 adev->umc.ras->set_eeprom_table_version(hdr); in amdgpu_ras_eeprom_reset_table()
720 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_eeprom_update_header() local
728 control->ras_num_recs >= ras->bad_page_cnt_threshold) { in amdgpu_ras_eeprom_update_header()
731 control->ras_num_recs, ras->bad_page_cnt_threshold); in amdgpu_ras_eeprom_update_header()
780 control->ras_num_recs < ras->bad_page_cnt_threshold) in amdgpu_ras_eeprom_update_header()
781 control->tbl_rai.health_percent = ((ras->bad_page_cnt_threshold - in amdgpu_ras_eeprom_update_header()
783 ras->bad_page_cnt_threshold; in amdgpu_ras_eeprom_update_header()
1004 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in amdgpu_ras_debugfs_eeprom_size_read() local
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H A Daldebaran.c365 if (tmp_adev->sdma.ras && in aldebaran_mode2_restore_hwcontext()
366 tmp_adev->sdma.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
367 r = tmp_adev->sdma.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
368 &tmp_adev->sdma.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
375 if (tmp_adev->gfx.ras && in aldebaran_mode2_restore_hwcontext()
376 tmp_adev->gfx.ras->ras_block.ras_late_init) { in aldebaran_mode2_restore_hwcontext()
377 r = tmp_adev->gfx.ras->ras_block.ras_late_init(tmp_adev, in aldebaran_mode2_restore_hwcontext()
378 &tmp_adev->gfx.ras->ras_block.ras_comm); in aldebaran_mode2_restore_hwcontext()
H A Dumc_v6_7.c101 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_correctable_error_count() local
109 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_correctable_error_count()
116 if (ras->umc_ecc.record_ce_addr_supported) { in umc_v6_7_ecc_info_query_correctable_error_count()
121 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_ceumc_addr; in umc_v6_7_ecc_info_query_correctable_error_count()
143 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_querry_uncorrectable_error_count() local
150 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_querry_uncorrectable_error_count()
228 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v6_7_ecc_info_query_error_address() local
232 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v6_7_ecc_info_query_error_address()
244 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v6_7_ecc_info_query_error_address()
H A Damdgpu_gfx.c826 struct amdgpu_gfx_ras *ras = NULL; in amdgpu_gfx_ras_sw_init()
828 /* adev->gfx.ras is NULL, which means gfx does not in amdgpu_gfx_ras_sw_init()
829 * support ras function, then do nothing here. in amdgpu_gfx_ras_sw_init()
831 if (!adev->gfx.ras) in amdgpu_gfx_ras_sw_init()
834 ras = adev->gfx.ras; in amdgpu_gfx_ras_sw_init()
836 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_gfx_ras_sw_init()
838 dev_err(adev->dev, "Failed to register gfx ras block!\n"); in amdgpu_gfx_ras_sw_init()
842 strlcpy(ras->ras_block.ras_comm.name, "gfx", in amdgpu_gfx_ras_sw_init()
843 sizeof(ras in amdgpu_gfx_ras_sw_init()
823 struct amdgpu_gfx_ras *ras = NULL; amdgpu_gfx_ras_sw_init() local
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H A Dumc_v8_10.c341 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_correctable_error_count() local
349 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_correctable_error_count()
362 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_uncorrectable_error_count() local
370 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_uncorrectable_error_count()
410 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_10_ecc_info_query_error_address() local
417 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_10_ecc_info_query_error_address()
430 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_10_ecc_info_query_error_address()
H A Dumc_v8_7.c56 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_correctable_error_count() local
63 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_correctable_error_count()
75 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_querry_uncorrectable_error_count() local
80 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_querry_uncorrectable_error_count()
137 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in umc_v8_7_ecc_info_query_error_address() local
140 mc_umc_status = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_status; in umc_v8_7_ecc_info_query_error_address()
152 err_addr = ras->umc_ecc.ecc[eccinfo_table_idx].mca_umc_addr; in umc_v8_7_ecc_info_query_error_address()
H A Damdgpu_xgmi.c915 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_ras_late_init()
1081 adev->gmc.xgmi.ras->ras_block.hw_ops->reset_ras_error_count(adev); in amdgpu_xgmi_query_ras_error_count()
1131 struct amdgpu_xgmi_ras *ras; in amdgpu_xgmi_ras_sw_init() local
1133 if (!adev->gmc.xgmi.ras) in amdgpu_xgmi_ras_sw_init()
1136 ras = adev->gmc.xgmi.ras; in amdgpu_xgmi_ras_sw_init()
1137 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_xgmi_ras_sw_init()
1143 strlcpy(ras->ras_block.ras_comm.name, "xgmi_wafl", in amdgpu_xgmi_ras_sw_init()
1144 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_xgmi_ras_sw_init()
1145 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__XGMI_WAFL; in amdgpu_xgmi_ras_sw_init()
1146 ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE; in amdgpu_xgmi_ras_sw_init()
[all …]
H A Dgmc_v9_0.c1470 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1479 adev->umc.ras = &umc_v6_1_ras; in gmc_v9_0_set_umc_funcs()
1489 adev->umc.ras = &umc_v6_7_ras; in gmc_v9_0_set_umc_funcs()
1522 adev->mmhub.ras = &mmhub_v1_0_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1525 adev->mmhub.ras = &mmhub_v9_4_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1528 adev->mmhub.ras = &mmhub_v1_7_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1531 adev->mmhub.ras = &mmhub_v1_8_ras; in gmc_v9_0_set_mmhub_ras_funcs()
1534 /* mmhub ras is not available */ in gmc_v9_0_set_mmhub_ras_funcs()
1549 adev->hdp.ras = &hdp_v4_0_ras; in gmc_v9_0_set_hdp_ras_funcs()
1560 mca->mp0.ras in gmc_v9_0_set_mca_ras_funcs()
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H A Dgfx_v11_0_3.c94 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in gfx_v11_0_3_poison_consumption_handler() local
96 ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE2_RESET; in gfx_v11_0_3_poison_consumption_handler()
H A Damdgpu_vcn.c1226 struct amdgpu_vcn_ras *ras; in amdgpu_vcn_ras_sw_init()
1228 if (!adev->vcn.ras) in amdgpu_vcn_ras_sw_init()
1231 ras = adev->vcn.ras; in amdgpu_vcn_ras_sw_init()
1232 err = amdgpu_ras_register_ras_block(adev, &ras->ras_block); in amdgpu_vcn_ras_sw_init()
1234 dev_err(adev->dev, "Failed to register vcn ras block!\n"); in amdgpu_vcn_ras_sw_init()
1238 strlcpy(ras->ras_block.ras_comm.name, "vcn", in amdgpu_vcn_ras_sw_init()
1239 sizeof(ras->ras_block.ras_comm.name)); in amdgpu_vcn_ras_sw_init()
1240 ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__VCN; in amdgpu_vcn_ras_sw_init()
1241 ras in amdgpu_vcn_ras_sw_init()
1227 struct amdgpu_vcn_ras *ras; amdgpu_vcn_ras_sw_init() local
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H A Dsoc15.c484 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_baco_reset() local
488 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
496 if (ras && adev->ras_enabled) in soc15_asic_baco_reset()
507 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in soc15_asic_reset_method() local
541 if (ras && adev->ras_enabled && in soc15_asic_reset_method()
1304 if (adev->nbio.ras && in soc15_common_hw_fini()
1305 adev->nbio.ras->init_ras_controller_interrupt) in soc15_common_hw_fini()
1307 if (adev->nbio.ras && in soc15_common_hw_fini()
1308 adev->nbio.ras->init_ras_err_event_athub_interrupt) in soc15_common_hw_fini()
H A Damdgpu_hdp.h43 struct amdgpu_hdp_ras *ras; member
H A Damdgpu_mca.h30 struct amdgpu_mca_ras_block *ras; member
H A Damdgpu_mmhub.h71 struct amdgpu_mmhub_ras *ras; member
/openbsd-src/libexec/snmpd/snmpd_metrics/
H A Dpf.c363 pfta_get_addr(struct pfr_astats *ras, int tblidx) in pfta_get_addr() argument
387 if ((memcmp(&as->pfras_a.pfra_ip4addr, &ras->pfras_a.pfra_ip4addr, in pfta_get_addr()
389 && (as->pfras_a.pfra_net == ras->pfras_a.pfra_net)) in pfta_get_addr()
398 bcopy(as, ras, sizeof(struct pfr_astats)); in pfta_get_addr()
405 pfta_get_nextaddr(struct pfr_astats *ras, int *tblidx) in pfta_get_nextaddr() argument
430 &ras->pfras_a.pfra_ip4addr, in pfta_get_nextaddr()
434 ras->pfras_a.pfra_net) in pfta_get_nextaddr()
437 ras->pfras_a.pfra_net) in pfta_get_nextaddr()
454 bcopy(as, ras, sizeof(struct pfr_astats)); in pfta_get_nextaddr()
463 pfta_get_first(struct pfr_astats *ras) in pfta_get_first() argument
[all …]
/openbsd-src/sys/dev/pci/drm/amd/pm/powerplay/hwmgr/
H A Dvega20_baco.c76 struct amdgpu_ras *ras = amdgpu_ras_get_context(adev); in vega20_baco_set_state() local
87 if (!ras || !adev->ras_enabled) { in vega20_baco_set_state()
/openbsd-src/gnu/usr.bin/binutils/gdb/testsuite/gdb.cp/
H A Dref-types.cc37 short (&ras)[4] = as; in main() local

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