15ca02815Sjsg /* 25ca02815Sjsg * Copyright (C) 2021 Advanced Micro Devices, Inc. 35ca02815Sjsg * 45ca02815Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 55ca02815Sjsg * copy of this software and associated documentation files (the "Software"), 65ca02815Sjsg * to deal in the Software without restriction, including without limitation 75ca02815Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 85ca02815Sjsg * and/or sell copies of the Software, and to permit persons to whom the 95ca02815Sjsg * Software is furnished to do so, subject to the following conditions: 105ca02815Sjsg * 115ca02815Sjsg * The above copyright notice and this permission notice shall be included 125ca02815Sjsg * in all copies or substantial portions of the Software. 135ca02815Sjsg * 145ca02815Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 155ca02815Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 165ca02815Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 175ca02815Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 185ca02815Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 195ca02815Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 205ca02815Sjsg */ 215ca02815Sjsg #ifndef __AMDGPU_MCA_H__ 225ca02815Sjsg #define __AMDGPU_MCA_H__ 235ca02815Sjsg 241bb76ff1Sjsg struct amdgpu_mca_ras_block { 251bb76ff1Sjsg struct amdgpu_ras_block_object ras_block; 265ca02815Sjsg }; 275ca02815Sjsg 285ca02815Sjsg struct amdgpu_mca_ras { 295ca02815Sjsg struct ras_common_if *ras_if; 301bb76ff1Sjsg struct amdgpu_mca_ras_block *ras; 315ca02815Sjsg }; 325ca02815Sjsg 335ca02815Sjsg struct amdgpu_mca { 345ca02815Sjsg struct amdgpu_mca_ras mp0; 355ca02815Sjsg struct amdgpu_mca_ras mp1; 365ca02815Sjsg struct amdgpu_mca_ras mpio; 375ca02815Sjsg }; 385ca02815Sjsg 395ca02815Sjsg void amdgpu_mca_query_correctable_error_count(struct amdgpu_device *adev, 405ca02815Sjsg uint64_t mc_status_addr, 415ca02815Sjsg unsigned long *error_count); 425ca02815Sjsg 435ca02815Sjsg void amdgpu_mca_query_uncorrectable_error_count(struct amdgpu_device *adev, 445ca02815Sjsg uint64_t mc_status_addr, 455ca02815Sjsg unsigned long *error_count); 465ca02815Sjsg 475ca02815Sjsg void amdgpu_mca_reset_error_count(struct amdgpu_device *adev, 485ca02815Sjsg uint64_t mc_status_addr); 495ca02815Sjsg 505ca02815Sjsg void amdgpu_mca_query_ras_error_count(struct amdgpu_device *adev, 515ca02815Sjsg uint64_t mc_status_addr, 525ca02815Sjsg void *ras_error_status); 53*f005ef32Sjsg int amdgpu_mca_mp0_ras_sw_init(struct amdgpu_device *adev); 54*f005ef32Sjsg int amdgpu_mca_mp1_ras_sw_init(struct amdgpu_device *adev); 55*f005ef32Sjsg int amdgpu_mca_mpio_ras_sw_init(struct amdgpu_device *adev); 565ca02815Sjsg #endif 57