1c349dbc7Sjsg /* 2c349dbc7Sjsg * Copyright (C) 2019 Advanced Micro Devices, Inc. 3c349dbc7Sjsg * 4c349dbc7Sjsg * Permission is hereby granted, free of charge, to any person obtaining a 5c349dbc7Sjsg * copy of this software and associated documentation files (the "Software"), 6c349dbc7Sjsg * to deal in the Software without restriction, including without limitation 7c349dbc7Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8c349dbc7Sjsg * and/or sell copies of the Software, and to permit persons to whom the 9c349dbc7Sjsg * Software is furnished to do so, subject to the following conditions: 10c349dbc7Sjsg * 11c349dbc7Sjsg * The above copyright notice and this permission notice shall be included 12c349dbc7Sjsg * in all copies or substantial portions of the Software. 13c349dbc7Sjsg * 14c349dbc7Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15c349dbc7Sjsg * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16c349dbc7Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17c349dbc7Sjsg * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18c349dbc7Sjsg * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19c349dbc7Sjsg * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20c349dbc7Sjsg */ 21c349dbc7Sjsg #ifndef __AMDGPU_MMHUB_H__ 22c349dbc7Sjsg #define __AMDGPU_MMHUB_H__ 23c349dbc7Sjsg 24*f005ef32Sjsg enum amdgpu_mmhub_ras_memory_id { 25*f005ef32Sjsg AMDGPU_MMHUB_WGMI_PAGEMEM = 0, 26*f005ef32Sjsg AMDGPU_MMHUB_RGMI_PAGEMEM = 1, 27*f005ef32Sjsg AMDGPU_MMHUB_WDRAM_PAGEMEM = 2, 28*f005ef32Sjsg AMDGPU_MMHUB_RDRAM_PAGEMEM = 3, 29*f005ef32Sjsg AMDGPU_MMHUB_WIO_CMDMEM = 4, 30*f005ef32Sjsg AMDGPU_MMHUB_RIO_CMDMEM = 5, 31*f005ef32Sjsg AMDGPU_MMHUB_WGMI_CMDMEM = 6, 32*f005ef32Sjsg AMDGPU_MMHUB_RGMI_CMDMEM = 7, 33*f005ef32Sjsg AMDGPU_MMHUB_WDRAM_CMDMEM = 8, 34*f005ef32Sjsg AMDGPU_MMHUB_RDRAM_CMDMEM = 9, 35*f005ef32Sjsg AMDGPU_MMHUB_MAM_DMEM0 = 10, 36*f005ef32Sjsg AMDGPU_MMHUB_MAM_DMEM1 = 11, 37*f005ef32Sjsg AMDGPU_MMHUB_MAM_DMEM2 = 12, 38*f005ef32Sjsg AMDGPU_MMHUB_MAM_DMEM3 = 13, 39*f005ef32Sjsg AMDGPU_MMHUB_WRET_TAGMEM = 19, 40*f005ef32Sjsg AMDGPU_MMHUB_RRET_TAGMEM = 20, 41*f005ef32Sjsg AMDGPU_MMHUB_WIO_DATAMEM = 21, 42*f005ef32Sjsg AMDGPU_MMHUB_WGMI_DATAMEM = 22, 43*f005ef32Sjsg AMDGPU_MMHUB_WDRAM_DATAMEM = 23, 44*f005ef32Sjsg AMDGPU_MMHUB_MEMORY_BLOCK_LAST, 45*f005ef32Sjsg }; 46*f005ef32Sjsg 471bb76ff1Sjsg struct amdgpu_mmhub_ras { 481bb76ff1Sjsg struct amdgpu_ras_block_object ras_block; 495ca02815Sjsg }; 505ca02815Sjsg 515ca02815Sjsg struct amdgpu_mmhub_funcs { 52ad8b1aafSjsg u64 (*get_fb_location)(struct amdgpu_device *adev); 531bb76ff1Sjsg u64 (*get_mc_fb_offset)(struct amdgpu_device *adev); 54ad8b1aafSjsg void (*init)(struct amdgpu_device *adev); 55ad8b1aafSjsg int (*gart_enable)(struct amdgpu_device *adev); 56ad8b1aafSjsg void (*set_fault_enable_default)(struct amdgpu_device *adev, 57ad8b1aafSjsg bool value); 58ad8b1aafSjsg void (*gart_disable)(struct amdgpu_device *adev); 59ad8b1aafSjsg int (*set_clockgating)(struct amdgpu_device *adev, 60ad8b1aafSjsg enum amd_clockgating_state state); 611bb76ff1Sjsg void (*get_clockgating)(struct amdgpu_device *adev, u64 *flags); 62ad8b1aafSjsg void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 63ad8b1aafSjsg uint64_t page_table_base); 64ad8b1aafSjsg void (*update_power_gating)(struct amdgpu_device *adev, 65ad8b1aafSjsg bool enable); 66c349dbc7Sjsg }; 67c349dbc7Sjsg 68c349dbc7Sjsg struct amdgpu_mmhub { 69c349dbc7Sjsg struct ras_common_if *ras_if; 70c349dbc7Sjsg const struct amdgpu_mmhub_funcs *funcs; 711bb76ff1Sjsg struct amdgpu_mmhub_ras *ras; 72c349dbc7Sjsg }; 73c349dbc7Sjsg 74*f005ef32Sjsg int amdgpu_mmhub_ras_sw_init(struct amdgpu_device *adev); 75*f005ef32Sjsg 76c349dbc7Sjsg #endif 77c349dbc7Sjsg 78