1*f005ef32Sjsg /*
2*f005ef32Sjsg * Copyright 2023 Advanced Micro Devices, Inc.
3*f005ef32Sjsg *
4*f005ef32Sjsg * Permission is hereby granted, free of charge, to any person obtaining a
5*f005ef32Sjsg * copy of this software and associated documentation files (the "Software"),
6*f005ef32Sjsg * to deal in the Software without restriction, including without limitation
7*f005ef32Sjsg * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*f005ef32Sjsg * and/or sell copies of the Software, and to permit persons to whom the
9*f005ef32Sjsg * Software is furnished to do so, subject to the following conditions:
10*f005ef32Sjsg *
11*f005ef32Sjsg * The above copyright notice and this permission notice shall be included in
12*f005ef32Sjsg * all copies or substantial portions of the Software.
13*f005ef32Sjsg *
14*f005ef32Sjsg * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*f005ef32Sjsg * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*f005ef32Sjsg * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*f005ef32Sjsg * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*f005ef32Sjsg * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*f005ef32Sjsg * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*f005ef32Sjsg * OTHER DEALINGS IN THE SOFTWARE.
21*f005ef32Sjsg *
22*f005ef32Sjsg */
23*f005ef32Sjsg #include "amdgpu.h"
24*f005ef32Sjsg #include "amdgpu_ras.h"
25*f005ef32Sjsg
amdgpu_hdp_ras_sw_init(struct amdgpu_device * adev)26*f005ef32Sjsg int amdgpu_hdp_ras_sw_init(struct amdgpu_device *adev)
27*f005ef32Sjsg {
28*f005ef32Sjsg int err;
29*f005ef32Sjsg struct amdgpu_hdp_ras *ras;
30*f005ef32Sjsg
31*f005ef32Sjsg if (!adev->hdp.ras)
32*f005ef32Sjsg return 0;
33*f005ef32Sjsg
34*f005ef32Sjsg ras = adev->hdp.ras;
35*f005ef32Sjsg err = amdgpu_ras_register_ras_block(adev, &ras->ras_block);
36*f005ef32Sjsg if (err) {
37*f005ef32Sjsg dev_err(adev->dev, "Failed to register hdp ras block!\n");
38*f005ef32Sjsg return err;
39*f005ef32Sjsg }
40*f005ef32Sjsg
41*f005ef32Sjsg strlcpy(ras->ras_block.ras_comm.name, "hdp",
42*f005ef32Sjsg sizeof(ras->ras_block.ras_comm.name));
43*f005ef32Sjsg ras->ras_block.ras_comm.block = AMDGPU_RAS_BLOCK__HDP;
44*f005ef32Sjsg ras->ras_block.ras_comm.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;
45*f005ef32Sjsg adev->hdp.ras_if = &ras->ras_block.ras_comm;
46*f005ef32Sjsg
47*f005ef32Sjsg /* hdp ras follows amdgpu_ras_block_late_init_default for late init */
48*f005ef32Sjsg return 0;
49*f005ef32Sjsg }
50