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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; in getUnconditionalBranch()
30 return STI.isPositionIndependent() ? Mips::B : Mips::J; in getUnconditionalBranch()
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || in isLoadFromStackSlot()
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { in isLoadFromStackSlot()
71 if ((Opc == Mips in isStoreToStackSlot()
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H A DMipsInstrInfo.cpp1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
9 // This file contains the Mips implementation of the TargetInstrInfo class.
41 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP), in MipsInstrInfo()
61 BuildMI(MBB, MI, DL, get(Mips::NOP)); in insertNoop()
70 Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM; in insertNop()
72 Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL; in insertNop()
73 return BuildMI(MBB, MI, DL, get(Opc), Mips::ZERO) in insertNop()
74 .addReg(Mips in insertNop()
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H A DMipsExpandPseudo.cpp16 // spills between ll and sc. These stores cause some MIPS implementations to
21 #include "Mips.h"
30 #define DEBUG_TYPE "mips-pseudo"
49 return "Mips pseudo instruction expansion pass"; in getPassName()
84 unsigned ZERO = Mips::ZERO; in expandAtomicCmpSwapSubword()
85 unsigned BNE = Mips::BNE; in expandAtomicCmpSwapSubword()
86 unsigned BEQ = Mips::BEQ; in expandAtomicCmpSwapSubword()
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips in expandAtomicCmpSwapSubword()
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H A DMips16InstrInfo.cpp43 : MipsInstrInfo(STI, Mips::Bimm16) {} in Mips16InstrInfo()
75 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
76 Mips::GPR32RegClass.contains(SrcReg)) in copyPhysReg()
77 Opc = Mips::MoveR3216; in copyPhysReg()
78 else if (Mips::GPR32RegClass.contains(DestReg) && in copyPhysReg()
79 Mips::CPU16RegsRegClass.contains(SrcReg)) in copyPhysReg()
80 Opc = Mips::Move32R16; in copyPhysReg()
81 else if ((SrcReg == Mips::HI0) && in copyPhysReg()
82 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
83 Opc = Mips in copyPhysReg()
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H A DMipsRegisterInfo.cpp1 //===- MipsRegisterInfo.cpp - MIPS Register Information -------------------===//
9 // This file contains the MIPS implementation of the TargetRegisterInfo class.
15 #include "Mips.h"
37 #define DEBUG_TYPE "mips-reg-info"
42 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {} in MipsRegisterInfo()
44 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; } in getPICCallReg()
54 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in getPointerRegClass()
56 return &Mips::GPRMM16RegClass; in getPointerRegClass()
58 return ABI.ArePtrs64bit() ? &Mips::SP64RegClass : &Mips::SP32RegClass; in getPointerRegClass()
60 return ABI.ArePtrs64bit() ? &Mips::GP64RegClass : &Mips::GP32RegClass; in getPointerRegClass()
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H A DMicroMipsSizeReduction.cpp13 #include "Mips.h"
214 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUR1SP_MM),
216 {RT_OneInstr, OpCodes(Mips::ADDiu, Mips::ADDIUSP_MM), ReduceADDIUToADDIUSP,
218 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUR1SP_MM),
220 {RT_OneInstr, OpCodes(Mips::ADDiu_MM, Mips::ADDIUSP_MM),
222 {RT_OneInstr, OpCodes(Mips::ADDu, Mips::ADDU16_MM),
225 {RT_OneInstr, OpCodes(Mips::ADDu_MM, Mips::ADDU16_MM),
228 {RT_OneInstr, OpCodes(Mips::LBu, Mips::LBU16_MM), ReduceLXUtoLXU16,
230 {RT_OneInstr, OpCodes(Mips::LBu_MM, Mips::LBU16_MM), ReduceLXUtoLXU16,
232 {RT_OneInstr, OpCodes(Mips::LEA_ADDiu, Mips::ADDIUR1SP_MM),
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H A DMipsInstructionSelector.cpp10 /// Mips.
23 #define DEBUG_TYPE "mips-isel"
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID; in isRegInGprb()
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID; in isRegInFprb()
128 return &Mips::GPR32RegClass; in getRegClassForTypeOnBank()
136 return &Mips::FGR32RegClass; in getRegClassForTypeOnBank()
137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass; in getRegClassForTypeOnBank()
150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips in materialize32BitImm()
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H A DMipsSERegisterInfo.cpp15 #include "Mips.h"
39 #define DEBUG_TYPE "mips-reg-info"
56 return &Mips::GPR32RegClass; in intRegClass()
59 return &Mips::GPR64RegClass; in intRegClass()
68 case Mips::LD_B: in getLoadStoreOffsetSizeInBits()
69 case Mips::ST_B: in getLoadStoreOffsetSizeInBits()
71 case Mips::LD_H: in getLoadStoreOffsetSizeInBits()
72 case Mips::ST_H: in getLoadStoreOffsetSizeInBits()
74 case Mips::LD_W: in getLoadStoreOffsetSizeInBits()
75 case Mips::ST_W: in getLoadStoreOffsetSizeInBits()
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H A DMipsRegisterBankInfo.cpp9 /// This file implements the targeting of the RegisterBankInfo class for Mips.
26 namespace Mips { namespace
71 } // end namespace Mips
81 using namespace Mips; in getRegBankFromRegClass()
84 case Mips::GPR32RegClassID: in getRegBankFromRegClass()
85 case Mips::CPU16Regs_and_GPRMM16ZeroRegClassID: in getRegBankFromRegClass()
86 case Mips::GPRMM16MovePPairFirstRegClassID: in getRegBankFromRegClass()
87 case Mips::CPU16Regs_and_GPRMM16MovePPairSecondRegClassID: in getRegBankFromRegClass()
88 case Mips::GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClassID: in getRegBankFromRegClass()
89 case Mips in getRegBankFromRegClass()
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H A DMips16ISelLowering.cpp24 #define DEBUG_TYPE "mips-lower"
30 "pseudos for Mips 16"),
125 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass); in Mips16TargetLowering()
169 case Mips::SelBeqZ: in EmitInstrWithCustomInserter()
170 return emitSel16(Mips::BeqzRxImm16, MI, BB); in EmitInstrWithCustomInserter()
171 case Mips::SelBneZ: in EmitInstrWithCustomInserter()
172 return emitSel16(Mips::BnezRxImm16, MI, BB); in EmitInstrWithCustomInserter()
173 case Mips::SelTBteqZCmpi: in EmitInstrWithCustomInserter()
174 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB); in EmitInstrWithCustomInserter()
175 case Mips::SelTBteqZSlti: in EmitInstrWithCustomInserter()
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H A DMipsSEFrameLowering.cpp50 if (Mips::ACC64RegClass.contains(Src)) in getMFHiLoOpc()
51 return std::make_pair((unsigned)Mips::PseudoMFHI, in getMFHiLoOpc()
52 (unsigned)Mips::PseudoMFLO); in getMFHiLoOpc()
54 if (Mips::ACC64DSPRegClass.contains(Src)) in getMFHiLoOpc()
55 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP); in getMFHiLoOpc()
57 if (Mips::ACC128RegClass.contains(Src)) in getMFHiLoOpc()
58 return std::make_pair((unsigned)Mips::PseudoMFHI64, in getMFHiLoOpc()
59 (unsigned)Mips::PseudoMFLO64); in getMFHiLoOpc()
117 case Mips in expandInstr()
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H A DMipsBranchExpansion.cpp79 #include "Mips.h"
108 #define DEBUG_TYPE "mips-branch-expansion"
114 SkipLongBranch("skip-mips-long-branch", cl::init(false),
115 cl::desc("MIPS: Skip branch expansion pass."), cl::Hidden);
118 ForceLongBranch("force-mips-long-branch", cl::init(false),
119 cl::desc("MIPS: Expand all branches to long format."),
144 return "Mips Branch Expansion Pass"; in getPassName()
384 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR; in buildProperJumpMI()
385 unsigned JIC = ABI.IsN64() ? Mips in buildProperJumpMI()
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H A DMipsFastISel.cpp1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
10 /// This file defines the MIPS-specific support for the FastISel class.
74 #define DEBUG_TYPE "mips-fastisel"
300 Opc = Mips::AND; in emitLogicalOp()
303 Opc = Mips::OR; in emitLogicalOp()
306 Opc = Mips::XOR; in emitLogicalOp()
324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp()
340 Register ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca()
341 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::LEA_ADDiu), in fastMaterializeAlloca()
354 const TargetRegisterClass *RC = &Mips in materializeInt()
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H A DMipsMachineFunction.cpp1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
23 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
44 return Mips::CPU16RegsRegClass; in getGlobalBaseRegClass()
47 return Mips::GPRMM16RegClass; in getGlobalBaseRegClass()
50 return Mips::GPR64RegClass; in getGlobalBaseRegClass()
52 return Mips::GPR32RegClass; in getGlobalBaseRegClass()
82 RC = (ABI.IsN64()) ? &Mips::GPR64RegClass : &Mips::GPR32RegClass; in initGlobalBaseReg()
88 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
89 MBB.addLiveIn(Mips::T9_64); in initGlobalBaseReg()
95 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
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H A DMipsAsmPrinter.cpp1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
10 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
20 #include "Mips.h"
71 #define DEBUG_TYPE "mips-asm-printer"
120 TmpInst0.setOpcode(Mips::JALR64); in emitPseudoIndirectBranch()
125 TmpInst0.setOpcode(Mips::JRC16_MMR6); in emitPseudoIndirectBranch()
127 TmpInst0.setOpcode(Mips::JALR); in emitPseudoIndirectBranch()
132 TmpInst0.setOpcode(Mips::JR_MM); in emitPseudoIndirectBranch()
135 TmpInst0.setOpcode(Mips::JR); in emitPseudoIndirectBranch()
141 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips in emitPseudoIndirectBranch()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsABIInfo.cpp1 //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
10 #include "Mips.h"
21 EmitJalrReloc("mips-jalr-reloc", cl::Hidden,
22 cl::desc("MIPS: Emit R_{MICRO}MIPS_JALR relocation with jalr"),
26 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
29 Mips::A0_64, Mips
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H A DMipsAsmBackend.cpp1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
49 case Mips::fixup_Mips_LO16: in adjustFixupValue()
50 case Mips::fixup_Mips_GPREL16: in adjustFixupValue()
51 case Mips::fixup_Mips_GPOFF_HI: in adjustFixupValue()
52 case Mips::fixup_Mips_GPOFF_LO: in adjustFixupValue()
53 case Mips::fixup_Mips_GOT_PAGE: in adjustFixupValue()
54 case Mips::fixup_Mips_GOT_OFST: in adjustFixupValue()
55 case Mips::fixup_Mips_GOT_DISP: in adjustFixupValue()
56 case Mips::fixup_Mips_GOT_LO16: in adjustFixupValue()
57 case Mips in adjustFixupValue()
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H A DMipsMCCodeEmitter.cpp1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
75 case Mips::DSLL: in LowerLargeShift()
76 Inst.setOpcode(Mips::DSLL32); in LowerLargeShift()
78 case Mips::DSRL: in LowerLargeShift()
79 Inst.setOpcode(Mips::DSRL32); in LowerLargeShift()
81 case Mips::DSRA: in LowerLargeShift()
82 Inst.setOpcode(Mips::DSRA32); in LowerLargeShift()
84 case Mips::DROTR: in LowerLargeShift()
85 Inst.setOpcode(Mips::DROTR32); in LowerLargeShift()
100 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC || in LowerCompactBranch()
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H A DMipsNaClELFStreamer.cpp1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
9 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
19 #include "Mips.h"
33 #define DEBUG_TYPE "mips-mc-nacl"
37 const unsigned IndirectBranchMaskReg = Mips::T6;
38 const unsigned LoadStoreStackMaskReg = Mips::T7;
59 if (MI.getOpcode() == Mips::JALR) { in isIndirectJump()
63 return MI.getOperand(0).getReg() == Mips::ZERO; in isIndirectJump()
65 return MI.getOpcode() == Mips::JR; in isIndirectJump()
70 && MI.getOperand(0).getReg() == Mips in isStackPointerFirstOperand()
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H A DMipsInstPrinter.cpp1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
9 // This class prints an Mips MCInst to a .s file.
14 #include "Mips.h"
37 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
86 case Mips::RDHWR: in printInst()
87 case Mips::RDHWR64: in printInst()
91 case Mips::Save16: in printInst()
96 case Mips::SaveX16: in printInst()
101 case Mips::Restore16: in printInst()
106 case Mips::RestoreX16: in printInst()
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H A DMipsABIFlagsSection.h1 //===- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -------*- C++ -*-===//
29 // The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
32 Mips::AFL_REG GPRSize = Mips::AFL_REG_NONE;
34 Mips::AFL_REG CPR1Size = Mips::AFL_REG_NONE;
36 Mips::AFL_REG CPR2Size = Mips::AFL_REG_NONE;
38 Mips::AFL_EXT ISAExtension = Mips::AFL_EXT_NONE;
67 Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG; in getFlags1Value()
127 GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32; in setGPRSizeFromPredicates()
133 CPR1Size = Mips::AFL_REG_NONE; in setCPR1SizeFromPredicates()
135 CPR1Size = Mips::AFL_REG_128; in setCPR1SizeFromPredicates()
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H A DMipsELFObjectWriter.cpp1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===//
31 #define DEBUG_TYPE "mips-elf-object-writer"
139 /// R_(MIPS|MICROMIPS|MIPS16)_HI16 for all symbols and
140 /// R_(MIPS|MICROMIPS|MIPS16)_GOT16 for local symbols only.
231 "MIPS does not support one byte relocations"); in getRelocType()
233 case Mips::fixup_Mips_16: in getRelocType()
236 case Mips::fixup_Mips_32: in getRelocType()
239 case Mips::fixup_Mips_64: in getRelocType()
248 case Mips::fixup_Mips_Branch_PCRel: in getRelocType()
249 case Mips in getRelocType()
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
63 #define DEBUG_TYPE "mips-asm-parser"
123 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
124 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
125 Mips::FeatureMips4_32, Mips
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/freebsd-src/contrib/llvm-project/llvm/lib/Target/Mips/Disassembler/
H A DMipsDisassembler.cpp1 //===- MipsDisassembler.cpp - Disassembler for Mips -----------------------===//
9 // This file is part of the Mips Disassembler.
14 #include "Mips.h"
34 #define DEBUG_TYPE "mips-disassembler"
47 IsMicroMips(STI.hasFeature(Mips::FeatureMicroMips)), in MipsDisassembler()
50 bool hasMips2() const { return STI.hasFeature(Mips::FeatureMips2); } in hasMips2()
51 bool hasMips3() const { return STI.hasFeature(Mips::FeatureMips3); } in hasMips3()
52 bool hasMips32() const { return STI.hasFeature(Mips::FeatureMips32); } in hasMips32()
55 return STI.hasFeature(Mips::FeatureMips32r6); in hasMips32r6()
58 bool isFP64() const { return STI.hasFeature(Mips::FeatureFP64Bit); } in isFP64()
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/freebsd-src/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/
H A DMips.cpp1 //===--- Mips.cpp - Tools Implementations -----------------------*- C++ -*-===//
9 #include "Mips.h"
24 void mips::getMipsCPUAndABI(const ArgList &Args, const llvm::Triple &Triple, in getMipsCPUAndABI()
29 // MIPS32r6 is the default for mips(el)?-img-linux-gnu and MIPS64r6 is the in getMipsCPUAndABI()
46 // MIPS2 is the default for mips(el)?-unknown-freebsd. in getMipsCPUAndABI()
59 // Convert a GNU style Mips ABI name to the name in getMipsCPUAndABI()
60 // accepted by LLVM Mips backend. in getMipsCPUAndABI()
72 case llvm::Triple::mips: in getMipsCPUAndABI()
126 std::string mips::getMipsABILibSuffix(const ArgList &Args, in getMipsABILibSuffix()
129 tools::mips in getMipsABILibSuffix()
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