Lines Matching full:mips
1 //===- MipsFastISel.cpp - Mips FastISel implementation --------------------===//
10 /// This file defines the MIPS-specific support for the FastISel class.
74 #define DEBUG_TYPE "mips-fastisel"
300 Opc = Mips::AND;
303 Opc = Mips::OR;
306 Opc = Mips::XOR;
324 Register ResultReg = createResultReg(&Mips::GPR32RegClass);
340 Register ResultReg = createResultReg(&Mips::GPR32RegClass);
341 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::LEA_ADDiu),
354 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
364 unsigned Opc = Mips::ADDiu;
365 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
368 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
376 emitInst(Mips::LUi, TmpReg).addImm(Hi);
377 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
379 emitInst(Mips::LUi, ResultReg).addImm(Hi);
389 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
391 unsigned TempReg = materialize32BitInt(Imm, &Mips::GPR32RegClass);
392 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
395 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
397 unsigned TempReg1 = materialize32BitInt(Imm >> 32, &Mips::GPR32RegClass);
399 materialize32BitInt(Imm & 0xFFFFFFFF, &Mips::GPR32RegClass);
400 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
410 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
417 emitInst(Mips::LW, DestReg)
423 emitInst(Mips::ADDiu, TempReg)
432 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
434 emitInst(Mips::LW, DestReg)
648 Register TempReg = createResultReg(&Mips::GPR32RegClass);
649 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
650 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
654 Register TempReg = createResultReg(&Mips::GPR32RegClass);
655 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
656 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
660 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
663 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
666 Register TempReg = createResultReg(&Mips::GPR32RegClass);
667 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
668 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
672 Register TempReg = createResultReg(&Mips::GPR32RegClass);
673 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
674 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
678 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
681 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
684 Register TempReg = createResultReg(&Mips::GPR32RegClass);
685 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
686 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
690 Register TempReg = createResultReg(&Mips::GPR32RegClass);
691 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
692 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
710 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
711 CondMovOpc = Mips::MOVT_I;
714 Opc = IsFloat ? Mips::C_EQ_S : Mips::C_EQ_D32;
715 CondMovOpc = Mips::MOVF_I;
718 Opc = IsFloat ? Mips::C_OLT_S : Mips::C_OLT_D32;
719 CondMovOpc = Mips::MOVT_I;
722 Opc = IsFloat ? Mips::C_OLE_S : Mips::C_OLE_D32;
723 CondMovOpc = Mips::MOVT_I;
726 Opc = IsFloat ? Mips::C_ULE_S : Mips::C_ULE_D32;
727 CondMovOpc = Mips::MOVF_I;
730 Opc = IsFloat ? Mips::C_ULT_S : Mips::C_ULT_D32;
731 CondMovOpc = Mips::MOVF_I;
736 Register RegWithZero = createResultReg(&Mips::GPR32RegClass);
737 Register RegWithOne = createResultReg(&Mips::GPR32RegClass);
738 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
739 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
740 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
744 .addReg(Mips::FCC0)
759 ResultReg = createResultReg(&Mips::GPR32RegClass);
760 Opc = Mips::LW;
763 ResultReg = createResultReg(&Mips::GPR32RegClass);
764 Opc = Mips::LHu;
767 ResultReg = createResultReg(&Mips::GPR32RegClass);
768 Opc = Mips::LBu;
773 ResultReg = createResultReg(&Mips::FGR32RegClass);
774 Opc = Mips::LWC1;
779 ResultReg = createResultReg(&Mips::AFGR64RegClass);
780 Opc = Mips::LDC1;
813 Opc = Mips::SB;
816 Opc = Mips::SH;
819 Opc = Mips::SW;
824 Opc = Mips::SWC1;
829 Opc = Mips::SDC1;
953 ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
970 BuildMI(*BrBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::BGTZ))
979 Register ResultReg = createResultReg(&Mips::GPR32RegClass);
1003 Register DestReg = createResultReg(&Mips::AFGR64RegClass);
1004 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1025 CondMovOpc = Mips::MOVN_I_I;
1026 RC = &Mips::GPR32RegClass;
1028 CondMovOpc = Mips::MOVN_I_S;
1029 RC = &Mips::FGR32RegClass;
1031 CondMovOpc = Mips::MOVN_I_D32;
1032 RC = &Mips::AFGR64RegClass;
1045 Register ZExtCondReg = createResultReg(&Mips::GPR32RegClass);
1080 Register DestReg = createResultReg(&Mips::FGR32RegClass);
1084 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1118 Register DestReg = createResultReg(&Mips::GPR32RegClass);
1119 Register TempReg = createResultReg(&Mips::FGR32RegClass);
1120 unsigned Opc = (SrcVT == MVT::f32) ? Mips::TRUNC_W_S : Mips::TRUNC_W_D32;
1124 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1143 emitInst(Mips::ADJCALLSTACKDOWN).addImm(16).addImm(0);
1154 VA.convertToReg(Mips::F12);
1157 VA.convertToReg(Mips::D6_64);
1159 VA.convertToReg(Mips::D6);
1164 VA.convertToReg(Mips::F14);
1167 VA.convertToReg(Mips::D7_64);
1169 VA.convertToReg(Mips::D7);
1178 VA.convertToReg(Mips::A0);
1181 VA.convertToReg(Mips::A1);
1184 VA.convertToReg(Mips::A2);
1187 VA.convertToReg(Mips::A3);
1228 llvm_unreachable("Mips does not use custom args.");
1233 // from the AArch64 port and should be essentially fine for Mips too.
1254 Addr.setReg(Mips::SP);
1273 emitInst(Mips::ADJCALLSTACKUP).addImm(16).addImm(0);
1325 std::array<MCPhysReg, 4> GPR32ArgRegs = {{Mips::A0, Mips::A1, Mips::A2,
1326 Mips::A3}};
1327 std::array<MCPhysReg, 2> FGR32ArgRegs = {{Mips::F12, Mips::F14}};
1328 std::array<MCPhysReg, 2> AFGR64ArgRegs = {{Mips::D6, Mips::D7}};
1383 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1403 Allocation.emplace_back(&Mips::GPR32RegClass, *NextGPR32++);
1420 Allocation.emplace_back(&Mips::FGR32RegClass, *NextFGR32++);
1439 Allocation.emplace_back(&Mips::AFGR64RegClass, *NextAFGR64++);
1551 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1553 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Mips::JALR),
1554 Mips::RA).addReg(Mips::T9);
1594 Register DestReg = createResultReg(&Mips::GPR32RegClass);
1599 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1605 R = createResultReg(&Mips::GPR32RegClass);
1609 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1610 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1611 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[1]).addImm(0xFF);
1612 emitInst(Mips::OR, DestReg).addReg(TempReg[0]).addReg(TempReg[2]);
1618 Register TempReg = createResultReg(&Mips::GPR32RegClass);
1619 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1620 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1626 R = createResultReg(&Mips::GPR32RegClass);
1631 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1632 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1633 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1634 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1636 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1637 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1639 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1640 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1641 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1765 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
1815 Register ResultReg = createResultReg(&Mips::GPR32RegClass);
1836 Register TempReg = createResultReg(&Mips::GPR32RegClass);
1837 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1838 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1848 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1851 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1884 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1904 unsigned DestReg = createResultReg(&Mips::GPR32RegClass);
1924 DivOpc = Mips::SDIV;
1928 DivOpc = Mips::UDIV;
1938 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1940 Register ResultReg = createResultReg(&Mips::GPR32RegClass);
1945 ? Mips::MFHI
1946 : Mips::MFLO;
1959 Register ResultReg = createResultReg(&Mips::GPR32RegClass);
1971 Register TempReg = createResultReg(&Mips::GPR32RegClass);
1990 Opcode = Mips::SLL;
1993 Opcode = Mips::SRA;
1996 Opcode = Mips::SRL;
2013 Opcode = Mips::SLLV;
2016 Opcode = Mips::SRAV;
2019 Opcode = Mips::SRLV;
2097 Register TempReg = createResultReg(&Mips::GPR32RegClass);
2108 materialize32BitInt(Addr.getOffset(), &Mips::GPR32RegClass);
2109 Register DestReg = createResultReg(&Mips::GPR32RegClass);
2110 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2125 if (MachineInstOpcode == Mips::MUL) {
2133 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2134 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
2143 FastISel *Mips::createFastISel(FunctionLoweringInfo &funcInfo,