Lines Matching full:mips
29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM;
30 return STI.isPositionIndependent() ? Mips::B : Mips::J;
49 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
71 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
91 if (Mips::GPR32RegClass.contains(SrcReg)) {
93 Opc = Mips::MOVE16_MM;
95 Opc = Mips::OR, ZeroReg = Mips::ZERO;
96 } else if (Mips::CCRRegClass.contains(SrcReg))
97 Opc = Mips::CFC1;
98 else if (Mips::FGR32RegClass.contains(SrcReg))
99 Opc = Mips::MFC1;
100 else if (Mips::HI32RegClass.contains(SrcReg)) {
101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
103 } else if (Mips::LO32RegClass.contains(SrcReg)) {
104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
106 } else if (Mips::HI32DSPRegClass.contains(SrcReg))
107 Opc = Mips::MFHI_DSP;
108 else if (Mips::LO32DSPRegClass.contains(SrcReg))
109 Opc = Mips::MFLO_DSP;
110 else if (Mips::DSPCCRegClass.contains(SrcReg)) {
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
115 else if (Mips::MSACtrlRegClass.contains(SrcReg))
116 Opc = Mips::CFCMSA;
118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
119 if (Mips::CCRRegClass.contains(DestReg))
120 Opc = Mips::CTC1;
121 else if (Mips::FGR32RegClass.contains(DestReg))
122 Opc = Mips::MTC1;
123 else if (Mips::HI32RegClass.contains(DestReg))
124 Opc = Mips::MTHI, DestReg = 0;
125 else if (Mips::LO32RegClass.contains(DestReg))
126 Opc = Mips::MTLO, DestReg = 0;
127 else if (Mips::HI32DSPRegClass.contains(DestReg))
128 Opc = Mips::MTHI_DSP;
129 else if (Mips::LO32DSPRegClass.contains(DestReg))
130 Opc = Mips::MTLO_DSP;
131 else if (Mips::DSPCCRegClass.contains(DestReg)) {
132 BuildMI(MBB, I, DL, get(Mips::WRDSP))
136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
137 BuildMI(MBB, I, DL, get(Mips::CTCMSA))
143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
144 Opc = Mips::FMOV_S;
145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
146 Opc = Mips::FMOV_D32;
147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
148 Opc = Mips::FMOV_D64;
149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
150 if (Mips::GPR64RegClass.contains(SrcReg))
151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
152 else if (Mips::HI64RegClass.contains(SrcReg))
153 Opc = Mips::MFHI64, SrcReg = 0;
154 else if (Mips::LO64RegClass.contains(SrcReg))
155 Opc = Mips::MFLO64, SrcReg = 0;
156 else if (Mips::FGR64RegClass.contains(SrcReg))
157 Opc = Mips::DMFC1;
159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
160 if (Mips::HI64RegClass.contains(DestReg))
161 Opc = Mips::MTHI64, DestReg = 0;
162 else if (Mips::LO64RegClass.contains(DestReg))
163 Opc = Mips::MTLO64, DestReg = 0;
164 else if (Mips::FGR64RegClass.contains(DestReg))
165 Opc = Mips::DMTC1;
167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
168 if (Mips::MSA128BRegClass.contains(SrcReg))
169 Opc = Mips::MOVE_V;
190 case Mips::OR_MM:
191 case Mips::OR:
192 if (MI.getOperand(2).getReg() == Mips::ZERO)
195 case Mips::OR64:
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
203 /// We check for the common case of 'or', as it's MIPS' preferred instruction
205 /// Other move instructions for MIPS are directly identifiable.
224 if (Mips::GPR32RegClass.hasSubClassEq(RC))
225 Opc = Mips::SW;
226 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
227 Opc = Mips::SD;
228 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
229 Opc = Mips::STORE_ACC64;
230 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
231 Opc = Mips::STORE_ACC64DSP;
232 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
233 Opc = Mips::STORE_ACC128;
234 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
235 Opc = Mips::STORE_CCOND_DSP;
236 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
237 Opc = Mips::SWC1;
238 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
239 Opc = Mips::SDC1;
240 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
241 Opc = Mips::SDC164;
243 Opc = Mips::ST_B;
246 Opc = Mips::ST_H;
249 Opc = Mips::ST_W;
252 Opc = Mips::ST_D;
253 else if (Mips::LO32RegClass.hasSubClassEq(RC))
254 Opc = Mips::SW;
255 else if (Mips::LO64RegClass.hasSubClassEq(RC))
256 Opc = Mips::SD;
257 else if (Mips::HI32RegClass.hasSubClassEq(RC))
258 Opc = Mips::SW;
259 else if (Mips::HI64RegClass.hasSubClassEq(RC))
260 Opc = Mips::SD;
261 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
262 Opc = Mips::SWDSP;
268 if (Mips::HI32RegClass.hasSubClassEq(RC)) {
269 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
270 SrcReg = Mips::K0;
271 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
272 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
273 SrcReg = Mips::K0_64;
274 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
275 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
276 SrcReg = Mips::K0;
277 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
278 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
279 SrcReg = Mips::K0_64;
299 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
300 DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
302 if (Mips::GPR32RegClass.hasSubClassEq(RC))
303 Opc = Mips::LW;
304 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
305 Opc = Mips::LD;
306 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
307 Opc = Mips::LOAD_ACC64;
308 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
309 Opc = Mips::LOAD_ACC64DSP;
310 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
311 Opc = Mips::LOAD_ACC128;
312 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
313 Opc = Mips::LOAD_CCOND_DSP;
314 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
315 Opc = Mips::LWC1;
316 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
317 Opc = Mips::LDC1;
318 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
319 Opc = Mips::LDC164;
321 Opc = Mips::LD_B;
324 Opc = Mips::LD_H;
327 Opc = Mips::LD_W;
330 Opc = Mips::LD_D;
331 else if (Mips::HI32RegClass.hasSubClassEq(RC))
332 Opc = Mips::LW;
333 else if (Mips::HI64RegClass.hasSubClassEq(RC))
334 Opc = Mips::LD;
335 else if (Mips::LO32RegClass.hasSubClassEq(RC))
336 Opc = Mips::LW;
337 else if (Mips::LO64RegClass.hasSubClassEq(RC))
338 Opc = Mips::LD;
339 else if (Mips::DSPRRegClass.hasSubClassEq(RC))
340 Opc = Mips::LWDSP;
352 unsigned Reg = Mips::K0;
353 unsigned LdOp = Mips::MTLO;
354 if (DestReg == Mips::HI0)
355 LdOp = Mips::MTHI;
358 Reg = Mips::K0_64;
359 if (DestReg == Mips::HI0_64)
360 LdOp = Mips::MTHI64;
362 LdOp = Mips::MTLO64;
381 case Mips::RetRA:
384 case Mips::ERet:
387 case Mips::PseudoMFHI:
388 expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
390 case Mips::PseudoMFHI_MM:
391 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM);
393 case Mips::PseudoMFLO:
394 expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
396 case Mips::PseudoMFLO_MM:
397 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM);
399 case Mips::PseudoMFHI64:
400 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
402 case Mips::PseudoMFLO64:
403 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
405 case Mips::PseudoMTLOHI:
406 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
408 case Mips::PseudoMTLOHI64:
409 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
411 case Mips::PseudoMTLOHI_DSP:
412 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
414 case Mips::PseudoMTLOHI_MM:
415 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_MM, Mips::MTHI_MM, false);
417 case Mips::PseudoCVT_S_W:
418 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
420 case Mips::PseudoCVT_D32_W:
421 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W;
422 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false);
424 case Mips::PseudoCVT_S_L:
425 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
427 case Mips::PseudoCVT_D64_W:
428 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W;
429 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true);
431 case Mips::PseudoCVT_D64_L:
432 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
434 case Mips::BuildPairF64:
437 case Mips::BuildPairF64_64:
440 case Mips::ExtractElementF64:
443 case Mips::ExtractElementF64_64:
446 case Mips::MIPSeh_return32:
447 case Mips::MIPSeh_return64:
457 /// operand (\see lib/Target/Mips/MipsBranchExpansion.cpp).
462 case Mips::BBIT0:
463 case Mips::BBIT1:
464 case Mips::BBIT032:
465 case Mips::BBIT132:
475 case Mips::BEQ: return Mips::BNE;
476 case Mips::BEQ_MM: return Mips::BNE_MM;
477 case Mips::BNE: return Mips::BEQ;
478 case Mips::BNE_MM: return Mips::BEQ_MM;
479 case Mips::BGTZ: return Mips::BLEZ;
480 case Mips::BGEZ: return Mips::BLTZ;
481 case Mips::BLTZ: return Mips::BGEZ;
482 case Mips::BLEZ: return Mips::BGTZ;
483 case Mips::BGTZ_MM: return Mips::BLEZ_MM;
484 case Mips::BGEZ_MM: return Mips::BLTZ_MM;
485 case Mips::BLTZ_MM: return Mips::BGEZ_MM;
486 case Mips::BLEZ_MM: return Mips::BGTZ_MM;
487 case Mips::BEQ64: return Mips::BNE64;
488 case Mips::BNE64: return Mips::BEQ64;
489 case Mips::BGTZ64: return Mips::BLEZ64;
490 case Mips::BGEZ64: return Mips::BLTZ64;
491 case Mips::BLTZ64: return Mips::BGEZ64;
492 case Mips::BLEZ64: return Mips::BGTZ64;
493 case Mips::BC1T: return Mips::BC1F;
494 case Mips::BC1F: return Mips::BC1T;
495 case Mips::BC1T_MM: return Mips::BC1F_MM;
496 case Mips::BC1F_MM: return Mips::BC1T_MM;
497 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM;
498 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM;
499 case Mips::BEQZC_MM: return Mips::BNEZC_MM;
500 case Mips::BNEZC_MM: return Mips::BEQZC_MM;
501 case Mips::BEQZC: return Mips::BNEZC;
502 case Mips::BNEZC: return Mips::BEQZC;
503 case Mips::BLEZC: return Mips::BGTZC;
504 case Mips::BGEZC: return Mips::BLTZC;
505 case Mips::BGEC: return Mips::BLTC;
506 case Mips::BGTZC: return Mips::BLEZC;
507 case Mips::BLTZC: return Mips::BGEZC;
508 case Mips::BLTC: return Mips::BGEC;
509 case Mips::BGEUC: return Mips::BLTUC;
510 case Mips::BLTUC: return Mips::BGEUC;
511 case Mips::BEQC: return Mips::BNEC;
512 case Mips::BNEC: return Mips::BEQC;
513 case Mips::BC1EQZ: return Mips::BC1NEZ;
514 case Mips::BC1NEZ: return Mips::BC1EQZ;
515 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6;
516 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6;
517 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6;
518 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6;
519 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6;
520 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6;
521 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6;
522 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6;
523 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6;
524 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6;
525 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6;
526 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6;
527 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6;
528 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6;
529 case Mips::BEQZC64: return Mips::BNEZC64;
530 case Mips::BNEZC64: return Mips::BEQZC64;
531 case Mips::BEQC64: return Mips::BNEC64;
532 case Mips::BNEC64: return Mips::BEQC64;
533 case Mips::BGEC64: return Mips::BLTC64;
534 case Mips::BGEUC64: return Mips::BLTUC64;
535 case Mips::BLTC64: return Mips::BGEC64;
536 case Mips::BLTUC64: return Mips::BGEUC64;
537 case Mips::BGTZC64: return Mips::BLEZC64;
538 case Mips::BGEZC64: return Mips::BLTZC64;
539 case Mips::BLTZC64: return Mips::BGEZC64;
540 case Mips::BLEZC64: return Mips::BGTZC64;
541 case Mips::BBIT0: return Mips::BBIT1;
542 case Mips::BBIT1: return Mips::BBIT0;
543 case Mips::BBIT032: return Mips::BBIT132;
544 case Mips::BBIT132: return Mips::BBIT032;
545 case Mips::BZ_B: return Mips::BNZ_B;
546 case Mips::BZ_H: return Mips::BNZ_H;
547 case Mips::BZ_W: return Mips::BNZ_W;
548 case Mips::BZ_D: return Mips::BNZ_D;
549 case Mips::BZ_V: return Mips::BNZ_V;
550 case Mips::BNZ_B: return Mips::BZ_B;
551 case Mips::BNZ_H: return Mips::BZ_H;
552 case Mips::BNZ_W: return Mips::BZ_W;
553 case Mips::BNZ_D: return Mips::BZ_D;
554 case Mips::BNZ_V: return Mips::BZ_V;
595 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
596 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
598 &Mips::GPR64RegClass : &Mips::GPR32RegClass;
630 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE ||
631 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ ||
632 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 ||
633 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
634 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T ||
635 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J ||
636 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM ||
637 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC ||
638 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC ||
639 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC ||
640 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC ||
641 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 ||
642 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 ||
643 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 ||
644 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 ||
645 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC ||
646 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 ||
647 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 ||
648 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 ||
649 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 ||
650 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 ||
651 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 ||
652 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 ||
653 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0;
661 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
662 .addReg(Mips::RA_64, RegState::Undef);
664 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
665 .addReg(Mips::RA, RegState::Undef);
676 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
717 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
718 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
742 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
745 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
761 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
764 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
772 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
786 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM)
787 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)),
791 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
799 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
818 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
826 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
842 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM)
843 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)),
850 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
861 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
862 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
863 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
864 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;