Lines Matching full:mips
1 //===- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer --------------------===//
10 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
20 #include "Mips.h"
71 #define DEBUG_TYPE "mips-asm-printer"
120 TmpInst0.setOpcode(Mips::JALR64);
125 TmpInst0.setOpcode(Mips::JRC16_MMR6);
127 TmpInst0.setOpcode(Mips::JALR);
132 TmpInst0.setOpcode(Mips::JR_MM);
135 TmpInst0.setOpcode(Mips::JR);
141 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
204 if (InConstantPool && Opc != Mips::CONSTPOOL_ENTRY) {
208 if (Opc == Mips::CONSTPOOL_ENTRY) {
236 case Mips::PATCHABLE_FUNCTION_ENTER:
239 case Mips::PATCHABLE_FUNCTION_EXIT:
242 case Mips::PATCHABLE_TAIL_CALL:
264 if (I->getOpcode() == Mips::PseudoReturn ||
265 I->getOpcode() == Mips::PseudoReturn64 ||
266 I->getOpcode() == Mips::PseudoIndirectBranch ||
267 I->getOpcode() == Mips::PseudoIndirectBranch64 ||
268 I->getOpcode() == Mips::TAILCALLREG ||
269 I->getOpcode() == Mips::TAILCALLREG64) {
293 // Mips Asm Directives
338 unsigned CPURegSize = TRI->getRegSizeInBits(Mips::GPR32RegClass) / 8;
339 unsigned FGR32RegSize = TRI->getRegSizeInBits(Mips::FGR32RegClass) / 8;
340 unsigned AFGR64RegSize = TRI->getRegSizeInBits(Mips::AFGR64RegClass) / 8;
350 if (Mips::FGR32RegClass.contains(Reg)) {
353 } else if (Mips::AFGR64RegClass.contains(Reg)) {
357 } else if (Mips::GPR32RegClass.contains(Reg))
397 default: llvm_unreachable("Unknown Mips ABI");
571 if (w != Mips::NoRegister) {
698 case Mips::SWM32_MM:
699 case Mips::LWM32_MM:
723 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm());
748 // Compute MIPS architecture attributes based on the default subtarget
764 // For the moment, I'm only correcting enough to make MIPS-IV work.
825 I.setOpcode(Mips::JAL);
848 if (Opcode == Mips::MTC1) {
888 unsigned MovOpc = ToFP ? Mips::MTC1 : Mips::MFC1;
891 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
894 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F14, LE);
897 EmitInstrRegReg(STI, MovOpc, Mips::A0, Mips::F12);
898 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
901 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
904 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
905 EmitMovFPIntPair(STI, MovOpc, Mips::A2, Mips::A3, Mips::F14, Mips::F15, LE);
908 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F12, Mips::F13, LE);
909 EmitInstrRegReg(STI, MovOpc, Mips::A2, Mips::F14);
921 unsigned MovOpc = Mips::MFC1;
924 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0);
927 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
930 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
933 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE);
934 EmitMovFPIntPair(STI, MovOpc, Mips::A0, Mips::A1, Mips::F2, Mips::F3, LE);
1063 EmitInstrRegRegReg(*STI, Mips::OR, Mips::S2, Mips::RA, Mips::ZERO);
1078 EmitInstrReg(*STI, Mips::JR, Mips::S2);
1180 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::BEQ)
1181 .addReg(Mips::ZERO)
1182 .addReg(Mips::ZERO)
1186 EmitToStreamer(*OutStreamer, MCInstBuilder(Mips::SLL)
1187 .addReg(Mips::ZERO)
1188 .addReg(Mips::ZERO)
1195 MCInstBuilder(Mips::ADDiu)
1196 .addReg(Mips::T9)
1197 .addReg(Mips::T9)
1264 return (Opcode == Mips::LONG_BRANCH_LUi
1265 || Opcode == Mips::LONG_BRANCH_LUi2Op
1266 || Opcode == Mips::LONG_BRANCH_LUi2Op_64
1267 || Opcode == Mips::LONG_BRANCH_ADDiu
1268 || Opcode == Mips::LONG_BRANCH_ADDiu2Op
1269 || Opcode == Mips::LONG_BRANCH_DADDiu
1270 || Opcode == Mips::LONG_BRANCH_DADDiu2Op);