Lines Matching full:mips
79 #include "Mips.h"
108 #define DEBUG_TYPE "mips-branch-expansion"
114 SkipLongBranch("skip-mips-long-branch", cl::init(false),
115 cl::desc("MIPS: Skip branch expansion pass."), cl::Hidden);
118 ForceLongBranch("force-mips-long-branch", cl::init(false),
119 cl::desc("MIPS: Expand all branches to long format."),
144 return "Mips Branch Expansion Pass";
384 unsigned JR = ABI.IsN64() ? Mips::JR64 : Mips::JR;
385 unsigned JIC = ABI.IsN64() ? Mips::JIC64 : Mips::JIC;
386 unsigned JR_HB = ABI.IsN64() ? Mips::JR_HB64 : Mips::JR_HB;
387 unsigned JR_HB_R6 = ABI.IsN64() ? Mips::JR_HB64_R6 : Mips::JR_HB_R6;
395 if (JumpOp == Mips::JIC && STI->inMicroMipsMode())
396 JumpOp = Mips::JIC_MMR6;
398 unsigned ATReg = ABI.IsN64() ? Mips::AT_64 : Mips::AT;
434 ? STI->inMicroMipsMode() ? Mips::BALC_MMR6 : Mips::BALC
435 : STI->inMicroMipsMode() ? Mips::BAL_BR_MM : Mips::BAL_BR;
469 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
470 .addReg(Mips::SP)
472 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW))
473 .addReg(Mips::RA)
474 .addReg(Mips::SP)
493 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
500 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
501 .addReg(Mips::AT)
515 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
516 .addReg(Mips::RA)
517 .addReg(Mips::AT);
518 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
519 .addReg(Mips::SP)
530 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
531 .addReg(Mips::SP)
538 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
539 .addReg(Mips::SP)
592 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
593 .addReg(Mips::SP_64)
595 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD))
596 .addReg(Mips::RA_64)
597 .addReg(Mips::SP_64)
599 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
600 Mips::AT_64)
601 .addReg(Mips::ZERO_64)
604 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
605 .addReg(Mips::AT_64)
611 BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
612 .addReg(Mips::AT_64)
626 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
627 .addReg(Mips::RA_64)
628 .addReg(Mips::AT_64);
629 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
630 .addReg(Mips::SP_64)
636 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::DADDiu),
637 Mips::SP_64)
638 .addReg(Mips::SP_64)
641 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
642 .addReg(Mips::SP_64)
663 if (STI->hasMips32r6() && TII->isBranchOffsetInRange(Mips::BC, I.Offset)) {
670 TII->get(STI->inMicroMipsMode() ? Mips::BC_MMR6 : Mips::BC))
679 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::J)).addMBB(TgtMBB);
688 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op_64),
689 Mips::AT_64)
691 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
692 Mips::AT_64)
693 .addReg(Mips::AT_64)
695 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
696 .addReg(Mips::AT_64)
698 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
699 Mips::AT_64)
700 .addReg(Mips::AT_64)
702 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
703 .addReg(Mips::AT_64)
705 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
706 Mips::AT_64)
707 .addReg(Mips::AT_64)
710 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op),
711 Mips::AT)
713 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_ADDiu2Op),
714 Mips::AT)
715 .addReg(Mips::AT)
736 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
738 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
739 .addReg(Mips::V0)
741 MBB.removeLiveIn(Mips::V0);
767 std::next(Iit)->getOpcode() != Mips::NOP) {