Lines Matching full:mips
1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
63 #define DEBUG_TYPE "mips-asm-parser"
123 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
124 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
125 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5,
126 Mips::FeatureMips5_32r2, Mips::FeatureMips32, Mips::FeatureMips32r2,
127 Mips::FeatureMips32r3, Mips::FeatureMips32r5, Mips::FeatureMips32r6,
128 Mips::FeatureMips64, Mips::FeatureMips64r2, Mips::FeatureMips64r3,
129 Mips::FeatureMips64r5, Mips::FeatureMips64r6, Mips::FeatureCnMips,
130 Mips::FeatureCnMipsP, Mips::FeatureFP64Bit, Mips::FeatureGP64Bit,
131 Mips::FeatureNaN2008
577 return getSTI().hasFeature(Mips::FeatureGP64Bit);
581 return getSTI().hasFeature(Mips::FeatureFP64Bit);
602 return getSTI().hasFeature(Mips::FeatureFPXX);
606 return !(getSTI().hasFeature(Mips::FeatureNoOddSPReg));
610 return getSTI().hasFeature(Mips::FeatureMicroMips);
614 return getSTI().hasFeature(Mips::FeatureMips1);
618 return getSTI().hasFeature(Mips::FeatureMips2);
622 return getSTI().hasFeature(Mips::FeatureMips3);
626 return getSTI().hasFeature(Mips::FeatureMips4);
630 return getSTI().hasFeature(Mips::FeatureMips5);
634 return getSTI().hasFeature(Mips::FeatureMips32);
638 return getSTI().hasFeature(Mips::FeatureMips64);
642 return getSTI().hasFeature(Mips::FeatureMips32r2);
646 return getSTI().hasFeature(Mips::FeatureMips64r2);
650 return (getSTI().hasFeature(Mips::FeatureMips32r3));
654 return (getSTI().hasFeature(Mips::FeatureMips64r3));
658 return (getSTI().hasFeature(Mips::FeatureMips32r5));
662 return (getSTI().hasFeature(Mips::FeatureMips64r5));
666 return getSTI().hasFeature(Mips::FeatureMips32r6);
670 return getSTI().hasFeature(Mips::FeatureMips64r6);
674 return getSTI().hasFeature(Mips::FeatureDSP);
678 return getSTI().hasFeature(Mips::FeatureDSPR2);
682 return getSTI().hasFeature(Mips::FeatureDSPR3);
686 return getSTI().hasFeature(Mips::FeatureMSA);
690 return (getSTI().hasFeature(Mips::FeatureCnMips));
694 return (getSTI().hasFeature(Mips::FeatureCnMipsP));
702 return getSTI().hasFeature(Mips::FeatureMips16);
706 return getSTI().hasFeature(Mips::FeatureUseTCCInDIV);
710 return getSTI().hasFeature(Mips::FeatureSoftFloat);
713 return getSTI().hasFeature(Mips::FeatureMT);
717 return getSTI().hasFeature(Mips::FeatureCRC);
721 return getSTI().hasFeature(Mips::FeatureVirt);
725 return getSTI().hasFeature(Mips::FeatureGINV);
807 /// MipsOperand - Instances of this class represent a parsed Mips machine
922 unsigned ClassID = Mips::GPR32RegClassID;
930 unsigned ClassID = Mips::GPR32RegClassID;
938 unsigned ClassID = Mips::GPR64RegClassID;
949 return RegIdx.RegInfo->getRegClass(Mips::AFGR64RegClassID)
957 return RegIdx.RegInfo->getRegClass(Mips::FGR64RegClassID)
965 return RegIdx.RegInfo->getRegClass(Mips::FGR32RegClassID)
973 return RegIdx.RegInfo->getRegClass(Mips::FCCRegClassID)
983 unsigned ClassID = Mips::MSA128BRegClassID;
991 unsigned ClassID = Mips::MSACtrlRegClassID;
999 unsigned ClassID = Mips::COP0RegClassID;
1007 unsigned ClassID = Mips::COP2RegClassID;
1015 unsigned ClassID = Mips::COP3RegClassID;
1023 unsigned ClassID = Mips::ACC64DSPRegClassID;
1031 unsigned ClassID = Mips::HI32DSPRegClassID;
1039 unsigned ClassID = Mips::LO32DSPRegClassID;
1047 unsigned ClassID = Mips::CCRRegClassID;
1055 unsigned ClassID = Mips::HWRegsRegClassID;
1385 && getMemBase()->isRegIdx() && (getMemBase()->getGPR32Reg() == Mips::SP);
1391 && (getMemBase()->getGPR32Reg() == Mips::SP);
1397 && (getMemBase()->getGPR32Reg() == Mips::GP);
1430 if (!((R0 == Mips::S0 && R1 == Mips::RA) ||
1431 (R0 == Mips::S0_64 && R1 == Mips::RA_64)))
1762 case Mips::BEQ_MM:
1763 case Mips::BNE_MM:
1764 case Mips::BLTZ_MM:
1765 case Mips::BGEZ_MM:
1766 case Mips::BLEZ_MM:
1767 case Mips::BGTZ_MM:
1768 case Mips::JRC16_MM:
1769 case Mips::JALS_MM:
1770 case Mips::JALRS_MM:
1771 case Mips::JALRS16_MM:
1772 case Mips::BGEZALS_MM:
1773 case Mips::BLTZALS_MM:
1775 case Mips::J_MM:
1888 case Mips::BBIT0:
1889 case Mips::BBIT032:
1890 case Mips::BBIT1:
1891 case Mips::BBIT132:
1895 case Mips::BEQ:
1896 case Mips::BNE:
1897 case Mips::BEQ_MM:
1898 case Mips::BNE_MM:
1909 case Mips::BGEZ:
1910 case Mips::BGTZ:
1911 case Mips::BLEZ:
1912 case Mips::BLTZ:
1913 case Mips::BGEZAL:
1914 case Mips::BLTZAL:
1915 case Mips::BC1F:
1916 case Mips::BC1T:
1917 case Mips::BGEZ_MM:
1918 case Mips::BGTZ_MM:
1919 case Mips::BLEZ_MM:
1920 case Mips::BLTZ_MM:
1921 case Mips::BGEZAL_MM:
1922 case Mips::BLTZAL_MM:
1923 case Mips::BC1F_MM:
1924 case Mips::BC1T_MM:
1925 case Mips::BC1EQZC_MMR6:
1926 case Mips::BC1NEZC_MMR6:
1927 case Mips::BC2EQZC_MMR6:
1928 case Mips::BC2NEZC_MMR6:
1939 case Mips::BGEC: case Mips::BGEC_MMR6:
1940 case Mips::BLTC: case Mips::BLTC_MMR6:
1941 case Mips::BGEUC: case Mips::BGEUC_MMR6:
1942 case Mips::BLTUC: case Mips::BLTUC_MMR6:
1943 case Mips::BEQC: case Mips::BEQC_MMR6:
1944 case Mips::BNEC: case Mips::BNEC_MMR6:
1954 case Mips::BLEZC: case Mips::BLEZC_MMR6:
1955 case Mips::BGEZC: case Mips::BGEZC_MMR6:
1956 case Mips::BGTZC: case Mips::BGTZC_MMR6:
1957 case Mips::BLTZC: case Mips::BLTZC_MMR6:
1967 case Mips::BEQZC: case Mips::BEQZC_MMR6:
1968 case Mips::BNEZC: case Mips::BNEZC_MMR6:
1978 case Mips::BEQZ16_MM:
1979 case Mips::BEQZC16_MMR6:
1980 case Mips::BNEZ16_MM:
1981 case Mips::BNEZC16_MMR6:
1996 if (hasMips32r6() && Opcode == Mips::SSNOP) {
2010 case Mips::BBIT0:
2011 case Mips::BBIT032:
2012 case Mips::BBIT1:
2013 case Mips::BBIT132:
2020 if (Imm < 0 || Imm > (Opcode == Mips::BBIT0 ||
2021 Opcode == Mips::BBIT1 ? 63 : 31))
2024 Inst.setOpcode(Opcode == Mips::BBIT0 ? Mips::BBIT032
2025 : Mips::BBIT132);
2030 case Mips::SEQi:
2031 case Mips::SNEi:
2046 // The MIPS backend models most of the divison instructions and macros as
2055 case Mips::SDivIMacro:
2056 case Mips::UDivIMacro:
2057 case Mips::DSDivIMacro:
2058 case Mips::DUDivIMacro:
2060 if (Inst.getOperand(1).getReg() == Mips::ZERO ||
2061 Inst.getOperand(1).getReg() == Mips::ZERO_64)
2067 case Mips::DSDIV:
2068 case Mips::SDIV:
2069 case Mips::UDIV:
2070 case Mips::DUDIV:
2071 case Mips::UDIV_MM:
2072 case Mips::SDIV_MM:
2076 case Mips::SDivMacro:
2077 case Mips::DSDivMacro:
2078 case Mips::UDivMacro:
2079 case Mips::DUDivMacro:
2080 case Mips::DIV:
2081 case Mips::DIVU:
2082 case Mips::DDIV:
2083 case Mips::DDIVU:
2084 case Mips::DIVU_MMR6:
2085 case Mips::DIV_MMR6:
2086 if (Inst.getOperand(SecondOp).getReg() == Mips::ZERO ||
2087 Inst.getOperand(SecondOp).getReg() == Mips::ZERO_64) {
2088 if (Inst.getOperand(FirstOp).getReg() == Mips::ZERO ||
2089 Inst.getOperand(FirstOp).getReg() == Mips::ZERO_64)
2098 if ((Opcode == Mips::J || Opcode == Mips::J_MM) && inPicMode()) {
2100 BInst.setOpcode(inMicroMipsMode() ? Mips::BEQ_MM : Mips::BEQ);
2101 BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2102 BInst.addOperand(MCOperand::createReg(Mips::ZERO));
2109 if ((Opcode == Mips::JAL || Opcode == Mips::JAL_MM) && inPicMode()) {
2123 if (expandLoadAddress(Mips::T9, Mips::NoRegister, Inst.getOperand(0),
2129 JalrInst.setOpcode(IsCpRestoreSet ? Mips::JALRS_MM : Mips::JALR_MM);
2131 JalrInst.setOpcode(Mips::JALR);
2132 JalrInst.addOperand(MCOperand::createReg(Mips::RA));
2133 JalrInst.addOperand(MCOperand::createReg(Mips::T9));
2172 if (MCID.mayLoad() && Opcode != Mips::LWP_MM) {
2185 Mips::GPRMM16RegClassID).contains(DstReg.getReg()) &&
2186 (BaseReg.getReg() == Mips::GP ||
2187 BaseReg.getReg() == Mips::GP_64)) {
2189 TOut.emitRRI(Mips::LWGP_MM, DstReg.getReg(), Mips::GP, MemOffset,
2206 case Mips::ADDIUSP_MM:
2215 case Mips::SLL16_MM:
2216 case Mips::SRL16_MM:
2224 case Mips::LI16_MM:
2232 case Mips::ADDIUR2_MM:
2241 case Mips::ANDI16_MM:
2251 case Mips::LBU16_MM:
2259 case Mips::SB16_MM:
2260 case Mips::SB16_MMR6:
2268 case Mips::LHU16_MM:
2269 case Mips::SH16_MM:
2270 case Mips::SH16_MMR6:
2278 case Mips::LW16_MM:
2279 case Mips::SW16_MM:
2280 case Mips::SW16_MMR6:
2288 case Mips::ADDIUPC_MM:
2296 case Mips::LWP_MM:
2297 case Mips::SWP_MM:
2298 if (Inst.getOperand(0).getReg() == Mips::RA)
2301 case Mips::MOVEP_MM:
2302 case Mips::MOVEP_MMR6: {
2305 bool RegPair = ((R0 == Mips::A1 && R1 == Mips::A2) ||
2306 (R0 == Mips::A1 && R1 == Mips::A3) ||
2307 (R0 == Mips::A2 && R1 == Mips::A3) ||
2308 (R0 == Mips::A0 && R1 == Mips::S5) ||
2309 (R0 == Mips::A0 && R1 == Mips::S6) ||
2310 (R0 == Mips::A0 && R1 == Mips::A1) ||
2311 (R0 == Mips::A0 && R1 == Mips::A2) ||
2312 (R0 == Mips::A0 && R1 == Mips::A3));
2404 if ((Opcode == Mips::JalOneReg || Opcode == Mips::JalTwoReg ||
2441 case Mips::LoadImm32:
2443 case Mips::LoadImm64:
2445 case Mips::LoadAddrImm32:
2446 case Mips::LoadAddrImm64:
2451 return expandLoadAddress(Inst.getOperand(0).getReg(), Mips::NoRegister,
2453 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
2457 case Mips::LoadAddrReg32:
2458 case Mips::LoadAddrReg64:
2466 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
2470 case Mips::B_MM_Pseudo:
2471 case Mips::B_MMR6_Pseudo:
2474 case Mips::SWM_MM:
2475 case Mips::LWM_MM:
2478 case Mips::JalOneReg:
2479 case Mips::JalTwoReg:
2481 case Mips::BneImm:
2482 case Mips::BeqImm:
2483 case Mips::BEQLImmMacro:
2484 case Mips::BNELImmMacro:
2486 case Mips::BLT:
2487 case Mips::BLE:
2488 case Mips::BGE:
2489 case Mips::BGT:
2490 case Mips::BLTU:
2491 case Mips::BLEU:
2492 case Mips::BGEU:
2493 case Mips::BGTU:
2494 case Mips::BLTL:
2495 case Mips::BLEL:
2496 case Mips::BGEL:
2497 case Mips::BGTL:
2498 case Mips::BLTUL:
2499 case Mips::BLEUL:
2500 case Mips::BGEUL:
2501 case Mips::BGTUL:
2502 case Mips::BLTImmMacro:
2503 case Mips::BLEImmMacro:
2504 case Mips::BGEImmMacro:
2505 case Mips::BGTImmMacro:
2506 case Mips::BLTUImmMacro:
2507 case Mips::BLEUImmMacro:
2508 case Mips::BGEUImmMacro:
2509 case Mips::BGTUImmMacro:
2510 case Mips::BLTLImmMacro:
2511 case Mips::BLELImmMacro:
2512 case Mips::BGELImmMacro:
2513 case Mips::BGTLImmMacro:
2514 case Mips::BLTULImmMacro:
2515 case Mips::BLEULImmMacro:
2516 case Mips::BGEULImmMacro:
2517 case Mips::BGTULImmMacro:
2519 case Mips::SDivMacro:
2520 case Mips::SDivIMacro:
2521 case Mips::SRemMacro:
2522 case Mips::SRemIMacro:
2525 case Mips::DSDivMacro:
2526 case Mips::DSDivIMacro:
2527 case Mips::DSRemMacro:
2528 case Mips::DSRemIMacro:
2531 case Mips::UDivMacro:
2532 case Mips::UDivIMacro:
2533 case Mips::URemMacro:
2534 case Mips::URemIMacro:
2537 case Mips::DUDivMacro:
2538 case Mips::DUDivIMacro:
2539 case Mips::DURemMacro:
2540 case Mips::DURemIMacro:
2543 case Mips::PseudoTRUNC_W_S:
2546 case Mips::PseudoTRUNC_W_D32:
2549 case Mips::PseudoTRUNC_W_D:
2553 case Mips::LoadImmSingleGPR:
2556 case Mips::LoadImmSingleFGR:
2559 case Mips::LoadImmDoubleGPR:
2562 case Mips::LoadImmDoubleFGR:
2565 case Mips::LoadImmDoubleFGR_32:
2569 case Mips::Ulh:
2571 case Mips::Ulhu:
2573 case Mips::Ush:
2575 case Mips::Ulw:
2576 case Mips::Usw:
2578 case Mips::NORImm:
2579 case Mips::NORImm64:
2581 case Mips::SGE:
2582 case Mips::SGEU:
2584 case Mips::SGEImm:
2585 case Mips::SGEUImm:
2586 case Mips::SGEImm64:
2587 case Mips::SGEUImm64:
2589 case Mips::SGTImm:
2590 case Mips::SGTUImm:
2591 case Mips::SGTImm64:
2592 case Mips::SGTUImm64:
2594 case Mips::SLE:
2595 case Mips::SLEU:
2597 case Mips::SLEImm:
2598 case Mips::SLEUImm:
2599 case Mips::SLEImm64:
2600 case Mips::SLEUImm64:
2602 case Mips::SLTImm64:
2604 Inst.setOpcode(Mips::SLTi64);
2608 case Mips::SLTUImm64:
2610 Inst.setOpcode(Mips::SLTiu64);
2614 case Mips::ADDi: case Mips::ADDi_MM:
2615 case Mips::ADDiu: case Mips::ADDiu_MM:
2616 case Mips::SLTi: case Mips::SLTi_MM:
2617 case Mips::SLTiu: case Mips::SLTiu_MM:
2627 case Mips::ANDi: case Mips::ANDi_MM: case Mips::ANDi64:
2628 case Mips::ORi: case Mips::ORi_MM: case Mips::ORi64:
2629 case Mips::XORi: case Mips::XORi_MM: case Mips::XORi64:
2639 case Mips::ROL:
2640 case Mips::ROR:
2642 case Mips::ROLImm:
2643 case Mips::RORImm:
2645 case Mips::DROL:
2646 case Mips::DROR:
2648 case Mips::DROLImm:
2649 case Mips::DRORImm:
2651 case Mips::ABSMacro:
2653 case Mips::MULImmMacro:
2654 case Mips::DMULImmMacro:
2656 case Mips::MULOMacro:
2657 case Mips::DMULOMacro:
2659 case Mips::MULOUMacro:
2660 case Mips::DMULOUMacro:
2662 case Mips::DMULMacro:
2664 case Mips::LDMacro:
2665 case Mips::SDMacro:
2667 Inst.getOpcode() == Mips::LDMacro)
2670 case Mips::SDC1_M1:
2674 case Mips::SEQMacro:
2676 case Mips::SEQIMacro:
2678 case Mips::SNEMacro:
2680 case Mips::SNEIMacro:
2682 case Mips::MFTC0: case Mips::MTTC0:
2683 case Mips::MFTGPR: case Mips::MTTGPR:
2684 case Mips::MFTLO: case Mips::MTTLO:
2685 case Mips::MFTHI: case Mips::MTTHI:
2686 case Mips::MFTACX: case Mips::MTTACX:
2687 case Mips::MFTDSP: case Mips::MTTDSP:
2688 case Mips::MFTC1: case Mips::MTTC1:
2689 case Mips::MFTHC1: case Mips::MTTHC1:
2690 case Mips::CFTC1: case Mips::CTTC1:
2692 case Mips::SaaAddr:
2693 case Mips::SaadAddr:
2709 if (Opcode == Mips::JalOneReg) {
2712 JalrInst.setOpcode(Mips::JALRS16_MM);
2715 JalrInst.setOpcode(hasMips32r6() ? Mips::JALRC16_MMR6 : Mips::JALR16_MM);
2718 JalrInst.setOpcode(Mips::JALR);
2719 JalrInst.addOperand(MCOperand::createReg(Mips::RA));
2722 } else if (Opcode == Mips::JalTwoReg) {
2725 JalrInst.setOpcode(Mips::JALRS_MM);
2727 JalrInst.setOpcode(inMicroMipsMode() ? Mips::JALR_MM : Mips::JALR);
2753 /// @param SrcReg A register to add to the immediate or Mips::NoRegister
2783 unsigned AdduOp = !Is32BitImm ? Mips::DADDu : Mips::ADDu;
2786 if (SrcReg != Mips::NoRegister)
2808 TOut.emitRRI(Mips::DADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2812 TOut.emitRRI(Mips::ADDiu, DstReg, SrcReg, ImmValue, IDLoc, STI);
2824 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI);
2839 TOut.emitRI(Mips::LUi, TmpReg, 0xffff, IDLoc, STI);
2840 TOut.emitRRI(Mips::DSRL32, TmpReg, TmpReg, 0, IDLoc, STI);
2848 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI);
2849 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
2851 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2857 TOut.emitRI(Mips::LUi, TmpReg, Bits31To16, IDLoc, STI);
2859 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, Bits15To0, IDLoc, STI);
2880 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI);
2881 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
2896 if (loadImmediate(ImmValue >> 32, TmpReg, Mips::NoRegister, true, false,
2908 TOut.emitRRI(Mips::ORi, TmpReg, TmpReg, ImmChunk, IDLoc, STI);
2933 if (loadImmediate(ImmOp.getImm(), DstRegOp.getReg(), Mips::NoRegister,
2977 bool UseSrcReg = SrcReg != Mips::NoRegister && SrcReg != Mips::ZERO &&
2978 SrcReg != Mips::ZERO_64;
3004 bool UseXGOT = STI->hasFeature(Mips::FeatureXGOT) && !IsLocalSym;
3010 if ((DstReg == Mips::T9 || DstReg == Mips::T9_64) && !UseSrcReg &&
3017 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(CallHiExpr), IDLoc,
3019 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, DstReg, GPReg,
3021 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, DstReg,
3026 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, DstReg, GPReg,
3062 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(CallHiExpr), IDLoc,
3064 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, TmpReg, TmpReg, GPReg,
3066 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, TmpReg,
3070 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3076 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
3133 TOut.emitRRX(IsPtr64 ? Mips::LD : Mips::LW, TmpReg, GPReg,
3137 TOut.emitRRX(IsPtr64 ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3141 TOut.emitRRR(IsPtr64 ? Mips::DADDu : Mips::ADDu, DstReg, TmpReg, SrcReg,
3181 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3183 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3185 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3186 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
3188 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3189 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3191 TOut.emitRRR(Mips::DADDu, DstReg, ATReg, SrcReg, IDLoc, STI);
3208 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3210 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3211 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3213 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(LoExpr),
3215 TOut.emitRRI(Mips::DSLL32, DstReg, DstReg, 0, IDLoc, STI);
3216 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, ATReg, IDLoc, STI);
3218 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3231 TOut.emitRX(Mips::LUi, DstReg, MCOperand::createExpr(HighestExpr), IDLoc,
3233 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3235 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3236 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3238 TOut.emitRRI(Mips::DSLL, DstReg, DstReg, 16, IDLoc, STI);
3239 TOut.emitRRX(Mips::DADDiu, DstReg, DstReg,
3242 TOut.emitRRR(Mips::DADDu, DstReg, DstReg, SrcReg, IDLoc, STI);
3276 TOut.emitRX(Mips::LUi, TmpReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3277 TOut.emitRRX(Mips::ADDiu, TmpReg, TmpReg, MCOperand::createExpr(LoExpr),
3281 TOut.emitRRR(Mips::ADDu, DstReg, TmpReg, SrcReg, IDLoc, STI);
3293 if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg))
3294 return Reg == (unsigned)Mips::F31 ? (unsigned)Mips::F0 : Reg + 1;
3297 case Mips::ZERO: return Mips::AT;
3298 case Mips::AT: return Mips::V0;
3299 case Mips::V0: return Mips::V1;
3300 case Mips::V1: return Mips::A0;
3301 case Mips::A0: return Mips::A1;
3302 case Mips::A1: return Mips::A2;
3303 case Mips::A2: return Mips::A3;
3304 case Mips::A3: return Mips::T0;
3305 case Mips::T0: return Mips::T1;
3306 case Mips::T1: return Mips::T2;
3307 case Mips::T2: return Mips::T3;
3308 case Mips::T3: return Mips::T4;
3309 case Mips::T4: return Mips::T5;
3310 case Mips::T5: return Mips::T6;
3311 case Mips::T6: return Mips::T7;
3312 case Mips::T7: return Mips::S0;
3313 case Mips::S0: return Mips::S1;
3314 case Mips::S1: return Mips::S2;
3315 case Mips::S2: return Mips::S3;
3316 case Mips::S3: return Mips::S4;
3317 case Mips::S4: return Mips::S5;
3318 case Mips::S5: return Mips::S6;
3319 case Mips::S6: return Mips::S7;
3320 case Mips::S7: return Mips::T8;
3321 case Mips::T8: return Mips::T9;
3322 case Mips::T9: return Mips::K0;
3323 case Mips::K0: return Mips::K1;
3324 case Mips::K1: return Mips::GP;
3325 case Mips::GP: return Mips::SP;
3326 case Mips::SP: return Mips::FP;
3327 case Mips::FP: return Mips::RA;
3328 case Mips::RA: return Mips::ZERO;
3329 case Mips::D0: return Mips::F1;
3330 case Mips::D1: return Mips::F3;
3331 case Mips::D2: return Mips::F5;
3332 case Mips::D3: return Mips::F7;
3333 case Mips::D4: return Mips::F9;
3334 case Mips::D5: return Mips::F11;
3335 case Mips::D6: return Mips::F13;
3336 case Mips::D7: return Mips::F15;
3337 case Mips::D8: return Mips::F17;
3338 case Mips::D9: return Mips::F19;
3339 case Mips::D10: return Mips::F21;
3340 case Mips::D11: return Mips::F23;
3341 case Mips::D12: return Mips::F25;
3342 case Mips::D13: return Mips::F27;
3343 case Mips::D14: return Mips::F29;
3344 case Mips::D15: return Mips::F31;
3367 TOut.emitRRX(Mips::LW, ATReg, GPReg, MCOperand::createExpr(GotExpr),
3370 TOut.emitRRX(Mips::LD, ATReg, GPReg, MCOperand::createExpr(GotExpr),
3386 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HiExpr), IDLoc, STI);
3397 TOut.emitRX(Mips::LUi, ATReg, MCOperand::createExpr(HighestExpr), IDLoc,
3399 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg,
3401 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3402 TOut.emitRRX(Mips::DADDiu, ATReg, ATReg, MCOperand::createExpr(HiExpr),
3404 TOut.emitRRI(Mips::DSLL, ATReg, ATReg, 16, IDLoc, STI);
3440 return loadImmediate(ImmOp32, FirstReg, Mips::NoRegister, true, false, IDLoc,
3459 unsigned TmpReg = Mips::ZERO;
3467 if (TmpReg != Mips::ZERO && loadImmediate(ImmOp32, TmpReg, Mips::NoRegister,
3470 TOut.emitRR(Mips::MTC1, FirstReg, TmpReg, IDLoc, STI);
3493 TOut.emitRRX(Mips::LWC1, FirstReg, TmpReg, MCOperand::createExpr(LoExpr),
3513 if (loadImmediate(ImmOp64, FirstReg, Mips::NoRegister, false, false,
3517 if (loadImmediate(Hi_32(ImmOp64), FirstReg, Mips::NoRegister, true, false,
3521 if (loadImmediate(0, nextReg(FirstReg), Mips::NoRegister, true, false,
3551 TOut.emitRRX(isABI_N64() ? Mips::DADDiu : Mips::ADDiu, TmpReg, TmpReg,
3555 TOut.emitRRI(Mips::LD, FirstReg, TmpReg, 0, IDLoc, STI);
3557 TOut.emitRRI(Mips::LW, FirstReg, TmpReg, 0, IDLoc, STI);
3558 TOut.emitRRI(Mips::LW, nextReg(FirstReg), TmpReg, 4, IDLoc, STI);
3576 unsigned TmpReg = Mips::ZERO;
3586 if (TmpReg != Mips::ZERO &&
3587 loadImmediate(ImmOp64, TmpReg, Mips::NoRegister, false, false, IDLoc,
3590 TOut.emitRR(Mips::DMTC1, FirstReg, TmpReg, IDLoc, STI);
3594 if (TmpReg != Mips::ZERO &&
3595 loadImmediate(Hi_32(ImmOp64), TmpReg, Mips::NoRegister, true, false,
3600 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3601 TOut.emitRRR(Mips::MTHC1_D32, FirstReg, FirstReg, TmpReg, IDLoc, STI);
3603 TOut.emitRR(Mips::MTC1, nextReg(FirstReg), TmpReg, IDLoc, STI);
3604 TOut.emitRR(Mips::MTC1, FirstReg, Mips::ZERO, IDLoc, STI);
3630 TOut.emitRRX(Is64FPU ? Mips::LDC164 : Mips::LDC1, FirstReg, TmpReg,
3647 Inst.setOpcode(Mips::BEQ_MM);
3648 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3649 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3657 Inst.setOpcode(hasMips32r6() ? Mips::BC16_MMR6 : Mips::B16_MM);
3664 Inst.setOpcode(Mips::BEQ_MM);
3665 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3666 Inst.addOperand(MCOperand::createReg(Mips::ZERO));
3698 case Mips::BneImm:
3699 OpCode = Mips::BNE;
3701 case Mips::BeqImm:
3702 OpCode = Mips::BEQ;
3704 case Mips::BEQLImmMacro:
3705 OpCode = Mips::BEQL;
3708 case Mips::BNELImmMacro:
3709 OpCode = Mips::BNEL;
3720 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO,
3722 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3724 TOut.emitRRX(OpCode, DstRegOp.getReg(), Mips::ZERO, MemOffsetOp, IDLoc,
3733 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, !isGP64bit(), true,
3740 TOut.emitRRI(Mips::SLL, Mips::ZERO, Mips::ZERO, 0, IDLoc, STI);
3769 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
3770 (DstRegClassID == Mips::GPR64RegClassID);
3800 if (loadImmediate(HiOffset, TmpReg, Mips::NoRegister, Is32BitImm, true,
3805 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
3806 TOut.emitRRR(ABI.ArePtrs64bit() ? Mips::DADDu : Mips::ADDu, TmpReg,
3851 TOut.emitRX(Mips::LUi, TmpReg, HighestOperand, IDLoc, STI);
3852 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HigherOperand, IDLoc, STI);
3853 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
3854 TOut.emitRRX(Mips::DADDiu, TmpReg, TmpReg, HiOperand, IDLoc, STI);
3855 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, 16, IDLoc, STI);
3856 if (BaseReg != Mips::ZERO && BaseReg != Mips::ZERO_64)
3857 TOut.emitRRR(Mips::DADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
3861 TOut.emitRX(Mips::LUi, TmpReg, HiOperand, IDLoc, STI);
3862 if (BaseReg != Mips::ZERO)
3863 TOut.emitRRR(Mips::ADDu, TmpReg, TmpReg, BaseReg, IDLoc, STI);
3896 bool IsGPR = (DstRegClassID == Mips::GPR32RegClassID) ||
3897 (DstRegClassID == Mips::GPR64RegClassID);
3937 unsigned NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM32_MM : Mips::LWM32_MM;
3945 (Inst.getOperand(OpNum - 2).getReg() == Mips::SP ||
3946 Inst.getOperand(OpNum - 2).getReg() == Mips::SP_64) &&
3947 (Inst.getOperand(OpNum - 3).getReg() == Mips::RA ||
3948 Inst.getOperand(OpNum - 3).getReg() == Mips::RA_64)) {
3951 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MMR6 : Mips::LWM16_MMR6;
3953 NewOpcode = Opcode == Mips::SWM_MM ? Mips::SWM16_MM : Mips::LWM16_MM;
3988 case Mips::BLTImmMacro:
3989 PseudoOpcode = Mips::BLT;
3991 case Mips::BLEImmMacro:
3992 PseudoOpcode = Mips::BLE;
3994 case Mips::BGEImmMacro:
3995 PseudoOpcode = Mips::BGE;
3997 case Mips::BGTImmMacro:
3998 PseudoOpcode = Mips::BGT;
4000 case Mips::BLTUImmMacro:
4001 PseudoOpcode = Mips::BLTU;
4003 case Mips::BLEUImmMacro:
4004 PseudoOpcode = Mips::BLEU;
4006 case Mips::BGEUImmMacro:
4007 PseudoOpcode = Mips::BGEU;
4009 case Mips::BGTUImmMacro:
4010 PseudoOpcode = Mips::BGTU;
4012 case Mips::BLTLImmMacro:
4013 PseudoOpcode = Mips::BLTL;
4015 case Mips::BLELImmMacro:
4016 PseudoOpcode = Mips::BLEL;
4018 case Mips::BGELImmMacro:
4019 PseudoOpcode = Mips::BGEL;
4021 case Mips::BGTLImmMacro:
4022 PseudoOpcode = Mips::BGTL;
4024 case Mips::BLTULImmMacro:
4025 PseudoOpcode = Mips::BLTUL;
4027 case Mips::BLEULImmMacro:
4028 PseudoOpcode = Mips::BLEUL;
4030 case Mips::BGEULImmMacro:
4031 PseudoOpcode = Mips::BGEUL;
4033 case Mips::BGTULImmMacro:
4034 PseudoOpcode = Mips::BGTUL;
4038 if (loadImmediate(TrgOp.getImm(), TrgReg, Mips::NoRegister, !isGP64bit(),
4044 case Mips::BLT:
4045 case Mips::BLTU:
4046 case Mips::BLTL:
4047 case Mips::BLTUL:
4051 ((PseudoOpcode == Mips::BLTU) || (PseudoOpcode == Mips::BLTUL));
4052 IsLikely = ((PseudoOpcode == Mips::BLTL) || (PseudoOpcode == Mips::BLTUL));
4053 ZeroSrcOpcode = Mips::BGTZ;
4054 ZeroTrgOpcode = Mips::BLTZ;
4056 case Mips::BLE:
4057 case Mips::BLEU:
4058 case Mips::BLEL:
4059 case Mips::BLEUL:
4063 ((PseudoOpcode == Mips::BLEU) || (PseudoOpcode == Mips::BLEUL));
4064 IsLikely = ((PseudoOpcode == Mips::BLEL) || (PseudoOpcode == Mips::BLEUL));
4065 ZeroSrcOpcode = Mips::BGEZ;
4066 ZeroTrgOpcode = Mips::BLEZ;
4068 case Mips::BGE:
4069 case Mips::BGEU:
4070 case Mips::BGEL:
4071 case Mips::BGEUL:
4075 ((PseudoOpcode == Mips::BGEU) || (PseudoOpcode == Mips::BGEUL));
4076 IsLikely = ((PseudoOpcode == Mips::BGEL) || (PseudoOpcode == Mips::BGEUL));
4077 ZeroSrcOpcode = Mips::BLEZ;
4078 ZeroTrgOpcode = Mips::BGEZ;
4080 case Mips::BGT:
4081 case Mips::BGTU:
4082 case Mips::BGTL:
4083 case Mips::BGTUL:
4087 ((PseudoOpcode == Mips::BGTU) || (PseudoOpcode == Mips::BGTUL));
4088 IsLikely = ((PseudoOpcode == Mips::BGTL) || (PseudoOpcode == Mips::BGTUL));
4089 ZeroSrcOpcode = Mips::BLTZ;
4090 ZeroTrgOpcode = Mips::BGTZ;
4096 bool IsTrgRegZero = (TrgReg == Mips::ZERO);
4097 bool IsSrcRegZero = (SrcReg == Mips::ZERO);
4102 if (PseudoOpcode == Mips::BLT) {
4103 TOut.emitRX(Mips::BLTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
4107 if (PseudoOpcode == Mips::BLE) {
4108 TOut.emitRX(Mips::BLEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
4113 if (PseudoOpcode == Mips::BGE) {
4114 TOut.emitRX(Mips::BGEZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
4119 if (PseudoOpcode == Mips::BGT) {
4120 TOut.emitRX(Mips::BGTZ, Mips::ZERO, MCOperand::createExpr(OffsetExpr),
4124 if (PseudoOpcode == Mips::BGTU) {
4125 TOut.emitRRX(Mips::BNE, Mips::ZERO, Mips::ZERO,
4132 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
4142 if ((IsSrcRegZero && PseudoOpcode == Mips::BGTU) ||
4143 (IsTrgRegZero && PseudoOpcode == Mips::BLTU)) {
4150 if ((IsSrcRegZero && PseudoOpcode == Mips::BLEU) ||
4151 (IsTrgRegZero && PseudoOpcode == Mips::BGEU)) {
4157 TOut.emitRRX(Mips::BEQ, Mips::ZERO, Mips::ZERO,
4175 TOut.emitRRX(AcceptsEquality ? Mips::BEQ : Mips::BNE,
4176 IsSrcRegZero ? TrgReg : SrcReg, Mips::ZERO,
4213 TOut.emitRRR(IsUnsigned ? Mips::SLTu : Mips::SLT, ATRegNum,
4217 TOut.emitRRX(IsLikely ? (AcceptsEquality ? Mips::BEQL : Mips::BNEL)
4218 : (AcceptsEquality ? Mips::BEQ : Mips::BNE),
4219 ATRegNum, Mips::ZERO, MCOperand::createExpr(OffsetExpr), IDLoc,
4263 DivOp = Signed ? Mips::DSDIV : Mips::DUDIV;
4264 ZeroReg = Mips::ZERO_64;
4265 SubOp = Mips::DSUB;
4267 DivOp = Signed ? Mips::SDIV : Mips::UDIV;
4268 ZeroReg = Mips::ZERO;
4269 SubOp = Mips::SUB;
4275 bool isDiv = Opcode == Mips::SDivMacro || Opcode == Mips::SDivIMacro ||
4276 Opcode == Mips::UDivMacro || Opcode == Mips::UDivIMacro ||
4277 Opcode == Mips::DSDivMacro || Opcode == Mips::DSDivIMacro ||
4278 Opcode == Mips::DUDivMacro || Opcode == Mips::DUDivIMacro;
4280 bool isRem = Opcode == Mips::SRemMacro || Opcode == Mips::SRemIMacro ||
4281 Opcode == Mips::URemMacro || Opcode == Mips::URemIMacro ||
4282 Opcode == Mips::DSRemMacro || Opcode == Mips::DSRemIMacro ||
4283 Opcode == Mips::DURemMacro || Opcode == Mips::DURemIMacro;
4292 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4294 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4299 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI);
4302 TOut.emitRRR(Mips::OR, RdReg, RsReg, Mips::ZERO, IDLoc, STI);
4308 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
4312 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4322 if (RtReg == Mips::ZERO || RtReg == Mips::ZERO_64) {
4324 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI);
4327 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4333 if (isRem && (RdReg == Mips::ZERO || RdReg == Mips::ZERO_64)) {
4344 TOut.emitRRI(Mips::TEQ, RtReg, ZeroReg, 0x7, IDLoc, STI);
4349 TOut.emitRRX(Mips::BNE, RtReg, ZeroReg, LabelOp, IDLoc, STI);
4355 TOut.emitII(Mips::BREAK, 0x7, 0, IDLoc, STI);
4361 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4372 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, -1, IDLoc, STI);
4380 TOut.emitRRX(Mips::BNE, RtReg, ATReg, LabelOpEnd, IDLoc, STI);
4383 TOut.emitRRI(Mips::ADDiu, ATReg, ZeroReg, 1, IDLoc, STI);
4386 TOut.emitRI(Mips::LUi, ATReg, (uint16_t)0x8000, IDLoc, STI);
4390 TOut.emitRRI(Mips::TEQ, RsReg, ATReg, 0x6, IDLoc, STI);
4393 TOut.emitRRX(Mips::BNE, RsReg, ATReg, LabelOpEnd, IDLoc, STI);
4395 TOut.emitII(Mips::BREAK, 0x6, 0, IDLoc, STI);
4399 TOut.emitR(isDiv ? Mips::MFLO : Mips::MFHI, RdReg, IDLoc, STI);
4420 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4421 TOut.emitRR(Mips::CFC1, ThirdReg, Mips::RA, IDLoc, STI);
4423 TOut.emitRRI(Mips::ORi, ATReg, ThirdReg, 0x3, IDLoc, STI);
4424 TOut.emitRRI(Mips::XORi, ATReg, ATReg, 0x2, IDLoc, STI);
4425 TOut.emitRR(Mips::CTC1, Mips::RA, ATReg, IDLoc, STI);
4427 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::CVT_W_D64 : Mips::CVT_W_D32)
4428 : Mips::CVT_W_S,
4430 TOut.emitRR(Mips::CTC1, Mips::RA, ThirdReg, IDLoc, STI);
4435 TOut.emitRR(IsDouble ? (Is64FPU ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32)
4436 : Mips::TRUNC_W_S,
4485 TOut.emitRRI(Signed ? Mips::LB : Mips::LBu, FirstLbuDstReg, LbuSrcReg,
4487 TOut.emitRRI(Mips::LBu, SecondLbuDstReg, LbuSrcReg, SecondOffset, IDLoc, STI);
4488 TOut.emitRRI(Mips::SLL, SllReg, SllReg, 8, IDLoc, STI);
4489 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4530 TOut.emitRRI(Mips::SB, DstReg, ATReg, FirstOffset, IDLoc, STI);
4531 TOut.emitRRI(Mips::SRL, DstReg, DstReg, 8, IDLoc, STI);
4532 TOut.emitRRI(Mips::SB, DstReg, ATReg, SecondOffset, IDLoc, STI);
4533 TOut.emitRRI(Mips::LBu, ATReg, ATReg, 0, IDLoc, STI);
4534 TOut.emitRRI(Mips::SLL, DstReg, DstReg, 8, IDLoc, STI);
4535 TOut.emitRRR(Mips::OR, DstReg, DstReg, ATReg, IDLoc, STI);
4537 TOut.emitRRI(Mips::SB, DstReg, SrcReg, FirstOffset, IDLoc, STI);
4538 TOut.emitRRI(Mips::SRL, ATReg, DstReg, 8, IDLoc, STI);
4539 TOut.emitRRI(Mips::SB, ATReg, SrcReg, SecondOffset, IDLoc, STI);
4570 bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw);
4589 unsigned XWL = IsLoadInst ? Mips::LWL : Mips::SWL;
4590 unsigned XWR = IsLoadInst ? Mips::LWR : Mips::SWR;
4595 TOut.emitRRR(Mips::OR, TmpReg, DstReg, Mips::ZERO, IDLoc, STI);
4617 case Mips::SGE:
4618 OpCode = Mips::SLT;
4620 case Mips::SGEU:
4621 OpCode = Mips::SLTu;
4629 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4651 case Mips::SGEImm:
4652 case Mips::SGEImm64:
4653 OpRegCode = Mips::SLT;
4654 OpImmCode = Mips::SLTi;
4656 case Mips::SGEUImm:
4657 case Mips::SGEUImm64:
4658 OpRegCode = Mips::SLTu;
4659 OpImmCode = Mips::SLTiu;
4669 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4679 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4684 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4708 case Mips::SGTImm:
4709 case Mips::SGTImm64:
4710 OpCode = Mips::SLT;
4712 case Mips::SGTUImm:
4713 case Mips::SGTUImm64:
4714 OpCode = Mips::SLTu;
4727 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4754 case Mips::SLE:
4755 OpCode = Mips::SLT;
4757 case Mips::SLEU:
4758 OpCode = Mips::SLTu;
4766 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4788 case Mips::SLEImm:
4789 case Mips::SLEImm64:
4790 OpRegCode = Mips::SLT;
4792 case Mips::SLEUImm:
4793 case Mips::SLEUImm64:
4794 OpRegCode = Mips::SLTu;
4809 if (loadImmediate(ImmValue, ImmReg, Mips::NoRegister, isInt<32>(ImmValue),
4814 TOut.emitRRI(Mips::XORi, DstReg, DstReg, 1, IDLoc, STI);
4829 unsigned ATReg = Mips::NoRegister;
4830 unsigned FinalDstReg = Mips::NoRegister;
4847 if (!loadImmediate(ImmValue, DstReg, Mips::NoRegister, Is32Bit, false,
4852 case Mips::ADDi:
4853 FinalOpcode = Mips::ADD;
4855 case Mips::ADDiu:
4856 FinalOpcode = Mips::ADDu;
4858 case Mips::ANDi:
4859 FinalOpcode = Mips::AND;
4861 case Mips::NORImm:
4862 FinalOpcode = Mips::NOR;
4864 case Mips::ORi:
4865 FinalOpcode = Mips::OR;
4867 case Mips::SLTi:
4868 FinalOpcode = Mips::SLT;
4870 case Mips::SLTiu:
4871 FinalOpcode = Mips::SLTu;
4873 case Mips::XORi:
4874 FinalOpcode = Mips::XOR;
4876 case Mips::ADDi_MM:
4877 FinalOpcode = Mips::ADD_MM;
4879 case Mips::ADDiu_MM:
4880 FinalOpcode = Mips::ADDu_MM;
4882 case Mips::ANDi_MM:
4883 FinalOpcode = Mips::AND_MM;
4885 case Mips::ORi_MM:
4886 FinalOpcode = Mips::OR_MM;
4888 case Mips::SLTi_MM:
4889 FinalOpcode = Mips::SLT_MM;
4891 case Mips::SLTiu_MM:
4892 FinalOpcode = Mips::SLTu_MM;
4894 case Mips::XORi_MM:
4895 FinalOpcode = Mips::XOR_MM;
4897 case Mips::ANDi64:
4898 FinalOpcode = Mips::AND64;
4900 case Mips::NORImm64:
4901 FinalOpcode = Mips::NOR64;
4903 case Mips::ORi64:
4904 FinalOpcode = Mips::OR64;
4906 case Mips::SLTImm64:
4907 FinalOpcode = Mips::SLT64;
4909 case Mips::SLTUImm64:
4910 FinalOpcode = Mips::SLTu64;
4912 case Mips::XORi64:
4913 FinalOpcode = Mips::XOR64;
4917 if (FinalDstReg == Mips::NoRegister)
4929 unsigned ATReg = Mips::NoRegister;
4935 unsigned FirstShift = Mips::NOP;
4936 unsigned SecondShift = Mips::NOP;
4945 if (Inst.getOpcode() == Mips::ROL) {
4946 TOut.emitRRR(Mips::SUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4947 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
4951 if (Inst.getOpcode() == Mips::ROR) {
4952 TOut.emitRRR(Mips::ROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
4963 case Mips::ROL:
4964 FirstShift = Mips::SRLV;
4965 SecondShift = Mips::SLLV;
4967 case Mips::ROR:
4968 FirstShift = Mips::SLLV;
4969 SecondShift = Mips::SRLV;
4977 TOut.emitRRR(Mips::SUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
4980 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
4992 unsigned ATReg = Mips::NoRegister;
4997 unsigned FirstShift = Mips::NOP;
4998 unsigned SecondShift = Mips::NOP;
5001 if (Inst.getOpcode() == Mips::ROLImm) {
5006 TOut.emitRRI(Mips::ROTR, DReg, SReg, ShiftValue, Inst.getLoc(), STI);
5010 if (Inst.getOpcode() == Mips::RORImm) {
5011 TOut.emitRRI(Mips::ROTR, DReg, SReg, ImmValue, Inst.getLoc(), STI);
5020 TOut.emitRRI(Mips::SRL, DReg, SReg, 0, Inst.getLoc(), STI);
5027 case Mips::ROLImm:
5028 FirstShift = Mips::SLL;
5029 SecondShift = Mips::SRL;
5031 case Mips::RORImm:
5032 FirstShift = Mips::SRL;
5033 SecondShift = Mips::SLL;
5043 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
5054 unsigned ATReg = Mips::NoRegister;
5060 unsigned FirstShift = Mips::NOP;
5061 unsigned SecondShift = Mips::NOP;
5070 if (Inst.getOpcode() == Mips::DROL) {
5071 TOut.emitRRR(Mips::DSUBu, TmpReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
5072 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TmpReg, Inst.getLoc(), STI);
5076 if (Inst.getOpcode() == Mips::DROR) {
5077 TOut.emitRRR(Mips::DROTRV, DReg, SReg, TReg, Inst.getLoc(), STI);
5088 case Mips::DROL:
5089 FirstShift = Mips::DSRLV;
5090 SecondShift = Mips::DSLLV;
5092 case Mips::DROR:
5093 FirstShift = Mips::DSLLV;
5094 SecondShift = Mips::DSRLV;
5102 TOut.emitRRR(Mips::DSUBu, ATReg, Mips::ZERO, TReg, Inst.getLoc(), STI);
5105 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
5117 unsigned ATReg = Mips::NoRegister;
5122 unsigned FirstShift = Mips::NOP;
5123 unsigned SecondShift = Mips::NOP;
5128 unsigned FinalOpcode = Mips::NOP;
5130 FinalOpcode = Mips::DROTR;
5132 FinalOpcode = Mips::DROTR32;
5134 if (Inst.getOpcode() == Mips::DROLImm)
5135 FinalOpcode = Mips::DROTR32;
5137 FinalOpcode = Mips::DROTR;
5139 if (Inst.getOpcode() == Mips::DROLImm)
5140 FinalOpcode = Mips::DROTR;
5142 FinalOpcode = Mips::DROTR32;
5146 if (Inst.getOpcode() == Mips::DROLImm)
5156 TOut.emitRRI(Mips::DSRL, DReg, SReg, 0, Inst.getLoc(), STI);
5163 case Mips::DROLImm:
5165 FirstShift = Mips::DSLL;
5166 SecondShift = Mips::DSRL32;
5169 FirstShift = Mips::DSLL32;
5170 SecondShift = Mips::DSRL32;
5173 FirstShift = Mips::DSLL32;
5174 SecondShift = Mips::DSRL;
5177 case Mips::DRORImm:
5179 FirstShift = Mips::DSRL;
5180 SecondShift = Mips::DSLL32;
5183 FirstShift = Mips::DSRL32;
5184 SecondShift = Mips::DSLL32;
5187 FirstShift = Mips::DSRL32;
5188 SecondShift = Mips::DSLL;
5200 TOut.emitRRR(Mips::OR, DReg, DReg, ATReg, Inst.getLoc(), STI);
5214 TOut.emitRI(Mips::BGEZ, SecondRegOp, 8, IDLoc, STI);
5216 TOut.emitRRR(Mips::ADDu, FirstRegOp, SecondRegOp, Mips::ZERO, IDLoc, STI);
5219 TOut.emitRRR(Mips::SUB, FirstRegOp, Mips::ZERO, SecondRegOp, IDLoc, STI);
5227 unsigned ATReg = Mips::NoRegister;
5236 loadImmediate(ImmValue, ATReg, Mips::NoRegister, true, false, IDLoc, Out,
5239 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
5242 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5250 unsigned ATReg = Mips::NoRegister;
5259 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,
5262 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5264 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32,
5267 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
5270 TOut.emitRRI(Mips::TNE, DstReg, ATReg, 6, IDLoc, STI);
5277 TOut.emitRRX(Mips::BEQ, DstReg, ATReg, LabelOp, IDLoc, STI);
5280 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
5284 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5292 unsigned ATReg = Mips::NoRegister;
5301 TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,
5304 TOut.emitR(Mips::MFHI, ATReg, IDLoc, STI);
5305 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5307 TOut.emitRRI(Mips::TNE, ATReg, Mips::ZERO, 6, IDLoc, STI);
5314 TOut.emitRRX(Mips::BEQ, ATReg, Mips::ZERO, LabelOp, IDLoc, STI);
5317 TOut.emitII(Mips::BREAK, 6, 0, IDLoc, STI);
5332 TOut.emitRR(Mips::DMULTu, SrcReg, TmpReg, IDLoc, STI);
5333 TOut.emitR(Mips::MFLO, DstReg, IDLoc, STI);
5353 unsigned Opcode = IsLoad ? Mips::LW : Mips::SW;
5400 unsigned Opcode = Mips::SWC1;
5443 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
5444 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
5445 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5449 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
5450 TOut.emitRRI(Mips::SLTiu, DstReg, Reg, 1, IDLoc, STI);
5470 TOut.emitRRI(Mips::SLTiu, DstReg, SrcReg, 1, IDLoc, STI);
5474 if (SrcReg == Mips::ZERO) {
5476 TOut.emitRRR(isGP64bit() ? Mips::DADDu : Mips::ADDu,
5484 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
5486 Opc = Mips::XORi;
5494 if (loadImmediate(Imm, ATReg, Mips::NoRegister, true, isGP64bit(), IDLoc,
5498 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
5499 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5504 TOut.emitRRI(Mips::SLTiu, DstReg, DstReg, 1, IDLoc, STI);
5524 if (SrcReg != Mips::ZERO && OpReg != Mips::ZERO) {
5525 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, OpReg, IDLoc, STI);
5526 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
5530 unsigned Reg = SrcReg == Mips::ZERO ? OpReg : SrcReg;
5531 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, Reg, IDLoc, STI);
5551 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, SrcReg, IDLoc, STI);
5555 if (SrcReg == Mips::ZERO) {
5557 if (loadImmediate(1, DstReg, Mips::NoRegister, true, false, IDLoc, Out,
5566 Opc = isGP64bit() ? Mips::DADDiu : Mips::ADDiu;
5568 Opc = Mips::XORi;
5573 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
5581 if (loadImmediate(ImmValue, ATReg, Mips::NoRegister, isInt<32>(ImmValue),
5585 TOut.emitRRR(Mips::XOR, DstReg, SrcReg, ATReg, IDLoc, STI);
5586 TOut.emitRRR(Mips::SLTu, DstReg, Mips::ZERO, DstReg, IDLoc, STI);
5595 case Mips::MFTLO:
5596 case Mips::MTTLO:
5598 case Mips::AC0:
5599 return Mips::ZERO;
5600 case Mips::AC1:
5601 return Mips::A0;
5602 case Mips::AC2:
5603 return Mips::T0;
5604 case Mips::AC3:
5605 return Mips::T4;
5609 case Mips::MFTHI:
5610 case Mips::MTTHI:
5612 case Mips::AC0:
5613 return Mips::AT;
5614 case Mips::AC1:
5615 return Mips::A1;
5616 case Mips::AC2:
5617 return Mips::T1;
5618 case Mips::AC3:
5619 return Mips::T5;
5623 case Mips::MFTACX:
5624 case Mips::MTTACX:
5626 case Mips::AC0:
5627 return Mips::V0;
5628 case Mips::AC1:
5629 return Mips::A2;
5630 case Mips::AC2:
5631 return Mips::T2;
5632 case Mips::AC3:
5633 return Mips::T6;
5637 case Mips::MFTDSP:
5638 case Mips::MTTDSP:
5639 return Mips::S0;
5649 case Mips::F0: return Mips::ZERO;
5650 case Mips::F1: return Mips::AT;
5651 case Mips::F2: return Mips::V0;
5652 case Mips::F3: return Mips::V1;
5653 case Mips::F4: return Mips::A0;
5654 case Mips::F5: return Mips::A1;
5655 case Mips::F6: return Mips::A2;
5656 case Mips::F7: return Mips::A3;
5657 case Mips::F8: return Mips::T0;
5658 case Mips::F9: return Mips::T1;
5659 case Mips::F10: return Mips::T2;
5660 case Mips::F11: return Mips::T3;
5661 case Mips::F12: return Mips::T4;
5662 case Mips::F13: return Mips::T5;
5663 case Mips::F14: return Mips::T6;
5664 case Mips::F15: return Mips::T7;
5665 case Mips::F16: return Mips::S0;
5666 case Mips::F17: return Mips::S1;
5667 case Mips::F18: return Mips::S2;
5668 case Mips::F19: return Mips::S3;
5669 case Mips::F20: return Mips::S4;
5670 case Mips::F21: return Mips::S5;
5671 case Mips::F22: return Mips::S6;
5672 case Mips::F23: return Mips::S7;
5673 case Mips::F24: return Mips::T8;
5674 case Mips::F25: return Mips::T9;
5675 case Mips::F26: return Mips::K0;
5676 case Mips::F27: return Mips::K1;
5677 case Mips::F28: return Mips::GP;
5678 case Mips::F29: return Mips::SP;
5679 case Mips::F30: return Mips::FP;
5680 case Mips::F31: return Mips::RA;
5688 case Mips::COP00: return Mips::ZERO;
5689 case Mips::COP01: return Mips::AT;
5690 case Mips::COP02: return Mips::V0;
5691 case Mips::COP03: return Mips::V1;
5692 case Mips::COP04: return Mips::A0;
5693 case Mips::COP05: return Mips::A1;
5694 case Mips::COP06: return Mips::A2;
5695 case Mips::COP07: return Mips::A3;
5696 case Mips::COP08: return Mips::T0;
5697 case Mips::COP09: return Mips::T1;
5698 case Mips::COP010: return Mips::T2;
5699 case Mips::COP011: return Mips::T3;
5700 case Mips::COP012: return Mips::T4;
5701 case Mips::COP013: return Mips::T5;
5702 case Mips::COP014: return Mips::T6;
5703 case Mips::COP015: return Mips::T7;
5704 case Mips::COP016: return Mips::S0;
5705 case Mips::COP017: return Mips::S1;
5706 case Mips::COP018: return Mips::S2;
5707 case Mips::COP019: return Mips::S3;
5708 case Mips::COP020: return Mips::S4;
5709 case Mips::COP021: return Mips::S5;
5710 case Mips::COP022: return Mips::S6;
5711 case Mips::COP023: return Mips::S7;
5712 case Mips::COP024: return Mips::T8;
5713 case Mips::COP025: return Mips::T9;
5714 case Mips::COP026: return Mips::K0;
5715 case Mips::COP027: return Mips::K1;
5716 case Mips::COP028: return Mips::GP;
5717 case Mips::COP029: return Mips::SP;
5718 case Mips::COP030: return Mips::FP;
5719 case Mips::COP031: return Mips::RA;
5735 case Mips::MFTC0:
5738 case Mips::MTTC0:
5743 case Mips::MFTGPR:
5746 case Mips::MTTGPR:
5749 case Mips::MFTLO:
5750 case Mips::MFTHI:
5751 case Mips::MFTACX:
5752 case Mips::MFTDSP:
5755 case Mips::MTTLO:
5756 case Mips::MTTHI:
5757 case Mips::MTTACX:
5758 case Mips::MTTDSP:
5762 case Mips::MFTHC1:
5765 case Mips::MFTC1:
5770 case Mips::MTTHC1:
5773 case Mips::MTTC1:
5777 case Mips::CFTC1:
5780 case Mips::CTTC1:
5788 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
5791 TOut.emitRRIII(IsMFTR ? Mips::MFTR : Mips::MTTR, Op0, Op1, u, sel, h, IDLoc,
5805 unsigned Opcode = Inst.getOpcode() == Mips::SaaAddr ? Mips::SAA : Mips::SAAD;
5835 case Mips::DATI:
5836 case Mips::DAHI:
5848 case Mips::DAUI:
5849 if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5850 Inst.getOperand(1).getReg() == Mips::ZERO_64)
5857 case Mips::JALR_HB:
5858 case Mips::JALR_HB64:
5859 case Mips::JALRC_HB_MMR6:
5860 case Mips::JALRC_MMR6:
5864 case Mips::LWP_MM:
5868 case Mips::SYNC:
5872 case Mips::MFC0:
5873 case Mips::MTC0:
5874 case Mips::MTC2:
5875 case Mips::MFC2:
5891 case Mips::BLEZC: case Mips::BLEZC_MMR6:
5892 case Mips::BGEZC: case Mips::BGEZC_MMR6:
5893 case Mips::BGTZC: case Mips::BGTZC_MMR6:
5894 case Mips::BLTZC: case Mips::BLTZC_MMR6:
5895 case Mips::BEQZC: case Mips::BEQZC_MMR6:
5896 case Mips::BNEZC: case Mips::BNEZC_MMR6:
5897 case Mips::BLEZC64:
5898 case Mips::BGEZC64:
5899 case Mips::BGTZC64:
5900 case Mips::BLTZC64:
5901 case Mips::BEQZC64:
5902 case Mips::BNEZC64:
5903 if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5904 Inst.getOperand(0).getReg() == Mips::ZERO_64)
5907 case Mips::BGEC: case Mips::BGEC_MMR6:
5908 case Mips::BLTC: case Mips::BLTC_MMR6:
5909 case Mips::BGEUC: case Mips::BGEUC_MMR6:
5910 case Mips::BLTUC: case Mips::BLTUC_MMR6:
5911 case Mips::BEQC: case Mips::BEQC_MMR6:
5912 case Mips::BNEC: case Mips::BNEC_MMR6:
5913 case Mips::BGEC64:
5914 case Mips::BLTC64:
5915 case Mips::BGEUC64:
5916 case Mips::BLTUC64:
5917 case Mips::BEQC64:
5918 case Mips::BNEC64:
5919 if (Inst.getOperand(0).getReg() == Mips::ZERO ||
5920 Inst.getOperand(0).getReg() == Mips::ZERO_64)
5922 if (Inst.getOperand(1).getReg() == Mips::ZERO ||
5923 Inst.getOperand(1).getReg() == Mips::ZERO_64)
5928 case Mips::DINS: {
5937 case Mips::DINSM:
5938 case Mips::DINSU: {
5947 case Mips::DEXT: {
5956 case Mips::DEXTM:
5957 case Mips::DEXTU: {
5966 case Mips::CRC32B: case Mips::CRC32CB:
5967 case Mips::CRC32H: case Mips::CRC32CH:
5968 case Mips::CRC32W: case Mips::CRC32CW:
5969 case Mips::CRC32D: case Mips::CRC32CD:
5977 (Inst.getOperand(0).getReg() != Mips::FCC0) && !hasEightFccRegisters())
6211 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) &&
6399 (isGP64bit()) ? Mips::GPR64RegClassID : Mips::GPR32RegClassID, ATIndex);
6853 unsigned PrevReg = Mips::NoRegister;
6868 if ((isGP64bit() && RegNo == Mips::RA_64) ||
6869 (!isGP64bit() && RegNo == Mips::RA)) {
6874 if ((((TmpReg < Mips::S0) || (TmpReg > Mips::S7)) && !isGP64bit()) ||
6875 (((TmpReg < Mips::S0_64) || (TmpReg > Mips::S7_64)) &&
6886 if ((PrevReg == Mips::NoRegister) &&
6887 ((isGP64bit() && (RegNo != Mips::S0_64) && (RegNo != Mips::RA_64)) ||
6888 (!isGP64bit() && (RegNo != Mips::S0) && (RegNo != Mips::RA))))
6890 if (!(((RegNo == Mips::FP || RegNo == Mips::RA ||
6891 (RegNo >= Mips::S0 && RegNo <= Mips::S7)) &&
6893 ((RegNo == Mips::FP_64 || RegNo == Mips::RA_64 ||
6894 (RegNo >= Mips::S0_64 && RegNo <= Mips::S7_64)) &&
6897 if ((PrevReg != Mips::NoRegister) && (RegNo != PrevReg + 1) &&
6898 ((RegNo != Mips::FP && RegNo != Mips::RA && !isGP64bit()) ||
6899 (RegNo != Mips::FP_64 && RegNo != Mips::RA_64 && isGP64bit())))
6987 // as tested in test/MC/Mips/mips64r6/valid.s.
7209 setFeatureBits(Mips::FeatureMSA, "msa");
7222 clearFeatureBits(Mips::FeatureMSA, "msa");
7237 clearFeatureBits(Mips::FeatureDSP, "dsp");
7252 clearFeatureBits(Mips::FeatureMips3D, "mips3d");
7267 setFeatureBits(Mips::FeatureMips16, "mips16");
7283 clearFeatureBits(Mips::FeatureMips16, "mips16");
7325 clearFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
7339 setFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
7354 setFeatureBits(Mips::FeatureMT, "mt");
7370 clearFeatureBits(Mips::FeatureMT, "mt");
7387 clearFeatureBits(Mips::FeatureCRC, "crc");
7404 clearFeatureBits(Mips::FeatureVirt, "virt");
7421 clearFeatureBits(Mips::FeatureGINV, "ginv");
7471 setFeatureBits(Mips::FeatureSoftFloat, "soft-float");
7482 clearFeatureBits(Mips::FeatureSoftFloat, "soft-float");
7589 case Mips::FeatureMips3D:
7590 setFeatureBits(Mips::FeatureMips3D, "mips3d");
7593 case Mips::FeatureDSP:
7594 setFeatureBits(Mips::FeatureDSP, "dsp");
7597 case Mips::FeatureDSPR2:
7598 setFeatureBits(Mips::FeatureDSPR2, "dspr2");
7601 case Mips::FeatureMicroMips:
7602 setFeatureBits(Mips::FeatureMicroMips, "micromips");
7605 case Mips::FeatureMips1:
7609 case Mips::FeatureMips2:
7613 case Mips::FeatureMips3:
7617 case Mips::FeatureMips4:
7621 case Mips::FeatureMips5:
7625 case Mips::FeatureMips32:
7629 case Mips::FeatureMips32r2:
7633 case Mips::FeatureMips32r3:
7637 case Mips::FeatureMips32r5:
7641 case Mips::FeatureMips32r6:
7645 case Mips::FeatureMips64:
7649 case Mips::FeatureMips64r2:
7653 case Mips::FeatureMips64r3:
7657 case Mips::FeatureMips64r5:
7661 case Mips::FeatureMips64r6:
7665 case Mips::FeatureCRC:
7666 setFeatureBits(Mips::FeatureCRC, "crc");
7669 case Mips::FeatureVirt:
7670 setFeatureBits(Mips::FeatureVirt, "virt");
7673 case Mips::FeatureGINV:
7674 setFeatureBits(Mips::FeatureGINV, "ginv");
7978 clearFeatureBits(Mips::FeatureMicroMips, "micromips");
7988 return parseSetFeature(Mips::FeatureMicroMips);
7993 return parseSetFeature(Mips::FeatureMips1);
7995 return parseSetFeature(Mips::FeatureMips2);
7997 return parseSetFeature(Mips::FeatureMips3);
7999 return parseSetFeature(Mips::FeatureMips4);
8001 return parseSetFeature(Mips::FeatureMips5);
8003 return parseSetFeature(Mips::FeatureMips32);
8005 return parseSetFeature(Mips::FeatureMips32r2);
8007 return parseSetFeature(Mips::FeatureMips32r3);
8009 return parseSetFeature(Mips::FeatureMips32r5);
8011 return parseSetFeature(Mips::FeatureMips32r6);
8013 return parseSetFeature(Mips::FeatureMips64);
8015 return parseSetFeature(Mips::FeatureMips64r2);
8017 return parseSetFeature(Mips::FeatureMips64r3);
8019 return parseSetFeature(Mips::FeatureMips64r5);
8025 return parseSetFeature(Mips::FeatureMips64r6);
8028 return parseSetFeature(Mips::FeatureDSP);
8030 return parseSetFeature(Mips::FeatureDSPR2);
8034 return parseSetFeature(Mips::FeatureMips3D);
8050 return parseSetFeature(Mips::FeatureCRC);
8054 return parseSetFeature(Mips::FeatureVirt);
8058 return parseSetFeature(Mips::FeatureGINV);
8302 clearModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
8309 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8325 setModuleFeatureBits(Mips::FeatureNoOddSPReg, "nooddspreg");
8332 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8346 setModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float");
8353 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8365 clearModuleFeatureBits(Mips::FeatureSoftFloat, "soft-float");
8372 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8384 setModuleFeatureBits(Mips::FeatureMT, "mt");
8391 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8403 setModuleFeatureBits(Mips::FeatureCRC, "crc");
8410 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8422 clearModuleFeatureBits(Mips::FeatureCRC, "crc");
8429 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8441 setModuleFeatureBits(Mips::FeatureVirt, "virt");
8448 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8460 clearModuleFeatureBits(Mips::FeatureVirt, "virt");
8467 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8479 setModuleFeatureBits(Mips::FeatureGINV, "ginv");
8486 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8498 clearModuleFeatureBits(Mips::FeatureGINV, "ginv");
8505 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8549 // If generating ELF, don't do anything (the .MIPS.abiflags section gets
8579 setModuleFeatureBits(Mips::FeatureFPXX, "fpxx");
8580 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64");
8582 setFeatureBits(Mips::FeatureFPXX, "fpxx");
8583 clearFeatureBits(Mips::FeatureFP64Bit, "fp64");
8605 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx");
8606 clearModuleFeatureBits(Mips::FeatureFP64Bit, "fp64");
8608 clearFeatureBits(Mips::FeatureFPXX, "fpxx");
8609 clearFeatureBits(Mips::FeatureFP64Bit, "fp64");
8614 clearModuleFeatureBits(Mips::FeatureFPXX, "fpxx");
8615 setModuleFeatureBits(Mips::FeatureFP64Bit, "fp64");
8617 clearFeatureBits(Mips::FeatureFPXX, "fpxx");
8618 setFeatureBits(Mips::FeatureFP64Bit, "fp64");