Lines Matching full:mips
10 /// Mips.
23 #define DEBUG_TYPE "mips-isel"
97 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::GPRBRegBankID;
102 return RBI.getRegBank(Reg, MRI, TRI)->getID() == Mips::FPRBRegBankID;
128 return &Mips::GPR32RegClass;
136 return &Mips::FGR32RegClass;
137 return STI.isFP64bit() ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
150 B.buildInstr(Mips::ORi, {DestReg}, {Register(Mips::ZERO)})
156 MachineInstr *Inst = B.buildInstr(Mips::LUi, {DestReg}, {})
163 B.buildInstr(Mips::ADDiu, {DestReg}, {Register(Mips::ZERO)})
168 Register LUiReg = B.getMRI()->createVirtualRegister(&Mips::GPR32RegClass);
169 MachineInstr *LUi = B.buildInstr(Mips::LUi, {LUiReg}, {})
171 MachineInstr *ORi = B.buildInstr(Mips::ORi, {DestReg}, {LUiReg})
180 /// When I.getOpcode() is returned, we failed to select MIPS instruction opcode.
200 return Mips::SW;
202 return Mips::SH;
204 return Mips::SB;
212 return Mips::LW;
214 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LH : Mips::LHu;
216 return Opc == TargetOpcode::G_SEXTLOAD ? Mips::LB : Mips::LBu;
229 return isStore ? Mips::SWC1 : Mips::LWC1;
232 return isStore ? Mips::SDC164 : Mips::LDC164;
233 return isStore ? Mips::SDC1 : Mips::LDC1;
242 return isStore ? Mips::ST_B : Mips::LD_B;
244 return isStore ? Mips::ST_H : Mips::LD_H;
246 return isStore ? Mips::ST_W : Mips::LD_W;
248 return isStore ? Mips::ST_D : Mips::LD_D;
300 if (I.getOpcode() == Mips::G_MUL &&
302 MachineInstr *Mul = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MUL))
323 Register PseudoMULTuReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
326 PseudoMULTu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMULTu))
333 PseudoMove = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoMFHI))
343 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
355 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
367 Register JTIndex = MRI.createVirtualRegister(&Mips::GPR32RegClass);
368 MachineInstr *SLL = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SLL))
375 Register DestAddress = MRI.createVirtualRegister(&Mips::GPR32RegClass);
376 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
383 Register Dest = MRI.createVirtualRegister(&Mips::GPR32RegClass);
385 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
395 Register DestTmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
397 MachineInstr *ADDu = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDu))
407 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
416 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::PseudoIndirectBranch))
466 if (!buildUnalignedStore(I, Mips::SWL, BaseAddr, SignedOffset + 3, MMO))
468 if (!buildUnalignedStore(I, Mips::SWR, BaseAddr, SignedOffset, MMO))
475 Register ImplDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
476 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
478 Register Tmp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
479 if (!buildUnalignedLoad(I, Mips::LWL, Tmp, BaseAddr, SignedOffset + 3,
482 if (!buildUnalignedLoad(I, Mips::LWR, I.getOperand(0).getReg(),
507 Register HILOReg = MRI.createVirtualRegister(&Mips::ACC64RegClass);
513 TII.get(IsSigned ? Mips::PseudoSDIV : Mips::PseudoUDIV))
521 TII.get(IsDiv ? Mips::PseudoMFLO : Mips::PseudoMFHI))
532 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MOVN_I_I))
550 STI.isFP64bit() ? Mips::ExtractElementF64_64 : Mips::ExtractElementF64;
571 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::IMPLICIT_DEF))
593 Register GPRReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
599 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
604 Register GPRRegHigh = MRI.createVirtualRegister(&Mips::GPR32RegClass);
605 Register GPRRegLow = MRI.createVirtualRegister(&Mips::GPR32RegClass);
613 STI.isFP64bit() ? Mips::BuildPairF64_64 : Mips::BuildPairF64,
625 Size == 32 ? Mips::FABS_S
626 : STI.isFP64bit() ? Mips::FABS_D64 : Mips::FABS_D32;
642 Opcode = Mips::TRUNC_W_S;
644 Opcode = STI.isFP64bit() ? Mips::TRUNC_W_D64 : Mips::TRUNC_W_D32;
645 Register ResultInFPR = MRI.createVirtualRegister(&Mips::FGR32RegClass);
652 MachineInstr *Move = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::MFC1))
664 MachineInstr *LWGOT = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
684 Register LWGOTDef = MRI.createVirtualRegister(&Mips::GPR32RegClass);
688 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
697 Register LUiReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
699 MachineInstr *LUi = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
707 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
720 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LW))
730 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LUi))
744 if (Opcode == Mips::SLTiu || Opcode == Mips::XORi)
752 Register Temp = MRI.createVirtualRegister(&Mips::GPR32RegClass);
760 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
761 Instructions.emplace_back(Mips::SLTiu, ICMPReg, Temp, 1);
764 Instructions.emplace_back(Mips::XOR, Temp, LHS, RHS);
765 Instructions.emplace_back(Mips::SLTu, ICMPReg, Mips::ZERO, Temp);
768 Instructions.emplace_back(Mips::SLTu, ICMPReg, RHS, LHS);
771 Instructions.emplace_back(Mips::SLTu, Temp, LHS, RHS);
772 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
775 Instructions.emplace_back(Mips::SLTu, ICMPReg, LHS, RHS);
778 Instructions.emplace_back(Mips::SLTu, Temp, RHS, LHS);
779 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
782 Instructions.emplace_back(Mips::SLT, ICMPReg, RHS, LHS);
785 Instructions.emplace_back(Mips::SLT, Temp, LHS, RHS);
786 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
789 Instructions.emplace_back(Mips::SLT, ICMPReg, LHS, RHS);
792 Instructions.emplace_back(Mips::SLT, Temp, RHS, LHS);
793 Instructions.emplace_back(Mips::XORi, ICMPReg, Temp, 1);
823 MipsFCMPCondCode = Mips::FCOND_UN;
828 MipsFCMPCondCode = Mips::FCOND_OEQ;
833 MipsFCMPCondCode = Mips::FCOND_UEQ;
838 MipsFCMPCondCode = Mips::FCOND_OLT;
843 MipsFCMPCondCode = Mips::FCOND_ULT;
848 MipsFCMPCondCode = Mips::FCOND_OLE;
853 MipsFCMPCondCode = Mips::FCOND_ULE;
861 // We will move `false` (MIPS::Zero) to gpr result when fcmp gives false
864 unsigned MoveOpcode = isLogicallyNegated ? Mips::MOVT_I : Mips::MOVF_I;
866 Register TrueInReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
867 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::ADDiu))
869 .addUse(Mips::ZERO)
874 Size == 32 ? Mips::FCMP_S32
875 : STI.isFP64bit() ? Mips::FCMP_D64 : Mips::FCMP_D32;
885 .addUse(Mips::ZERO)
886 .addUse(Mips::FCC0)
895 MI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SYNC)).addImm(0);
902 Register LeaReg = MRI.createVirtualRegister(&Mips::GPR32RegClass);
904 BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::LEA_ADDiu))
911 MachineInstr *Store = BuildMI(MBB, I, I.getDebugLoc(), TII.get(Mips::SW))