Lines Matching full:mips
16 // spills between ll and sc. These stores cause some MIPS implementations to
21 #include "Mips.h"
30 #define DEBUG_TYPE "mips-pseudo"
49 return "Mips pseudo instruction expansion pass";
84 unsigned ZERO = Mips::ZERO;
85 unsigned BNE = Mips::BNE;
86 unsigned BEQ = Mips::BEQ;
88 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I8_POSTRA ? Mips::SEB : Mips::SEH;
91 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
92 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
93 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM;
94 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
96 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
97 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
98 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
99 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
146 BuildMI(loop1MBB, DL, TII->get(Mips::AND), Scratch2)
157 BuildMI(loop2MBB, DL, TII->get(Mips::AND), Scratch)
160 BuildMI(loop2MBB, DL, TII->get(Mips::OR), Scratch)
175 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
182 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I16_POSTRA ? 16 : 24;
183 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
186 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
207 I->getOpcode() == Mips::ATOMIC_CMP_SWAP_I32_POSTRA ? 4 : 8;
217 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
218 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
219 BNE = STI->hasMips32r6() ? Mips::BNEC_MMR6 : Mips::BNE_MM;
220 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
223 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
224 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
226 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
227 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
228 BNE = Mips::BNE;
229 BEQ = Mips::BEQ;
232 ZERO = Mips::ZERO;
233 MOVE = Mips::OR;
235 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
236 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
237 ZERO = Mips::ZERO_64;
238 BNE = Mips::BNE64;
239 BEQ = Mips::BEQ64;
240 MOVE = Mips::OR64;
312 unsigned BEQ = Mips::BEQ;
313 unsigned SEOp = Mips::SEH;
316 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
317 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
318 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
319 SLT = Mips::SLT_MM;
320 SLTu = Mips::SLTu_MM;
321 OR = STI->hasMips32r6() ? Mips::OR_MMR6 : Mips::OR_MM;
322 MOVN = Mips::MOVN_I_MM;
323 MOVZ = Mips::MOVZ_I_MM;
324 SELNEZ = STI->hasMips32r6() ? Mips::SELNEZ_MMR6 : Mips::SELNEZ;
325 SELEQZ = STI->hasMips32r6() ? Mips::SELEQZ_MMR6 : Mips::SELEQZ;
327 LL = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
328 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
329 SC = STI->hasMips32r6() ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
330 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
331 SLT = Mips::SLT;
332 SLTu = Mips::SLTu;
333 OR = Mips::OR;
334 MOVN = Mips::MOVN_I_I;
335 MOVZ = Mips::MOVZ_I_I;
336 SELNEZ = Mips::SELNEZ;
337 SELEQZ = Mips::SELEQZ;
349 case Mips::ATOMIC_LOAD_NAND_I8_POSTRA:
350 SEOp = Mips::SEB;
352 case Mips::ATOMIC_LOAD_NAND_I16_POSTRA:
355 case Mips::ATOMIC_SWAP_I8_POSTRA:
356 SEOp = Mips::SEB;
358 case Mips::ATOMIC_SWAP_I16_POSTRA:
361 case Mips::ATOMIC_LOAD_ADD_I8_POSTRA:
362 SEOp = Mips::SEB;
364 case Mips::ATOMIC_LOAD_ADD_I16_POSTRA:
365 Opcode = Mips::ADDu;
367 case Mips::ATOMIC_LOAD_SUB_I8_POSTRA:
368 SEOp = Mips::SEB;
370 case Mips::ATOMIC_LOAD_SUB_I16_POSTRA:
371 Opcode = Mips::SUBu;
373 case Mips::ATOMIC_LOAD_AND_I8_POSTRA:
374 SEOp = Mips::SEB;
376 case Mips::ATOMIC_LOAD_AND_I16_POSTRA:
377 Opcode = Mips::AND;
379 case Mips::ATOMIC_LOAD_OR_I8_POSTRA:
380 SEOp = Mips::SEB;
382 case Mips::ATOMIC_LOAD_OR_I16_POSTRA:
383 Opcode = Mips::OR;
385 case Mips::ATOMIC_LOAD_XOR_I8_POSTRA:
386 SEOp = Mips::SEB;
388 case Mips::ATOMIC_LOAD_XOR_I16_POSTRA:
389 Opcode = Mips::XOR;
391 case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA:
392 SEOp = Mips::SEB;
396 case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA:
400 case Mips::ATOMIC_LOAD_MIN_I8_POSTRA:
401 SEOp = Mips::SEB;
404 case Mips::ATOMIC_LOAD_MIN_I16_POSTRA:
407 case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA:
408 SEOp = Mips::SEB;
412 case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA:
416 case Mips::ATOMIC_LOAD_MAX_I8_POSTRA:
417 SEOp = Mips::SEB;
420 case Mips::ATOMIC_LOAD_MAX_I16_POSTRA:
459 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
462 BuildMI(loopMBB, DL, TII->get(Mips::NOR), BinOpRes)
463 .addReg(Mips::ZERO)
465 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
479 BuildMI(loopMBB, DL, TII->get(Mips::SRAV), StoreVal)
483 const unsigned OpMask = SEOp == Mips::SEH ? 0xffff : 0xff;
484 BuildMI(loopMBB, DL, TII->get(Mips::ANDi), StoreVal)
490 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
491 const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA;
492 BuildMI(loopMBB, DL, TII->get(Mips::SLL), StoreVal)
499 BuildMI(loopMBB, DL, TII->get(Mips::OR), Dest)
500 .addReg(Mips::ZERO)
503 BuildMI(loopMBB, DL, TII->get(Mips::SLLV), StoreVal)
536 .addReg(Mips::ZERO);
544 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
554 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
559 BuildMI(loopMBB, DL, TII->get(Mips::AND), BinOpRes)
568 BuildMI(loopMBB, DL, TII->get(Mips::AND), StoreVal)
570 BuildMI(loopMBB, DL, TII->get(Mips::OR), StoreVal)
575 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
584 BuildMI(sinkMBB, DL, TII->get(Mips::AND), Dest).addReg(OldVal).addReg(Mask);
585 BuildMI(sinkMBB, DL, TII->get(Mips::SRLV), Dest)
592 const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24;
593 BuildMI(sinkMBB, DL, TII->get(Mips::SLL), Dest)
596 BuildMI(sinkMBB, DL, TII->get(Mips::SRA), Dest)
626 LL = STI->hasMips32r6() ? Mips::LL_MMR6 : Mips::LL_MM;
627 SC = STI->hasMips32r6() ? Mips::SC_MMR6 : Mips::SC_MM;
628 BEQ = STI->hasMips32r6() ? Mips::BEQC_MMR6 : Mips::BEQ_MM;
629 SLT = Mips::SLT_MM;
630 SLTu = Mips::SLTu_MM;
631 OR = STI->hasMips32r6() ? Mips::OR_MMR6 : Mips::OR_MM;
632 MOVN = Mips::MOVN_I_MM;
633 MOVZ = Mips::MOVZ_I_MM;
634 SELNEZ = STI->hasMips32r6() ? Mips::SELNEZ_MMR6 : Mips::SELNEZ;
635 SELEQZ = STI->hasMips32r6() ? Mips::SELEQZ_MMR6 : Mips::SELEQZ;
638 ? (ArePtrs64bit ? Mips::LL64_R6 : Mips::LL_R6)
639 : (ArePtrs64bit ? Mips::LL64 : Mips::LL);
641 ? (ArePtrs64bit ? Mips::SC64_R6 : Mips::SC_R6)
642 : (ArePtrs64bit ? Mips::SC64 : Mips::SC);
643 BEQ = Mips::BEQ;
644 SLT = Mips::SLT;
645 SLTu = Mips::SLTu;
646 OR = Mips::OR;
647 MOVN = Mips::MOVN_I_I;
648 MOVZ = Mips::MOVZ_I_I;
649 SELNEZ = Mips::SELNEZ;
650 SELEQZ = Mips::SELEQZ;
653 ZERO = Mips::ZERO;
655 LL = STI->hasMips64r6() ? Mips::LLD_R6 : Mips::LLD;
656 SC = STI->hasMips64r6() ? Mips::SCD_R6 : Mips::SCD;
657 ZERO = Mips::ZERO_64;
658 BEQ = Mips::BEQ64;
659 SLT = Mips::SLT64;
660 SLTu = Mips::SLTu64;
661 OR = Mips::OR64;
662 MOVN = Mips::MOVN_I64_I64;
663 MOVZ = Mips::MOVZ_I64_I64;
664 SELNEZ = Mips::SELNEZ64;
665 SELEQZ = Mips::SELEQZ64;
684 case Mips::ATOMIC_LOAD_ADD_I32_POSTRA:
685 Opcode = Mips::ADDu;
687 case Mips::ATOMIC_LOAD_SUB_I32_POSTRA:
688 Opcode = Mips::SUBu;
690 case Mips::ATOMIC_LOAD_AND_I32_POSTRA:
691 Opcode = Mips::AND;
693 case Mips::ATOMIC_LOAD_OR_I32_POSTRA:
694 Opcode = Mips::OR;
696 case Mips::ATOMIC_LOAD_XOR_I32_POSTRA:
697 Opcode = Mips::XOR;
699 case Mips::ATOMIC_LOAD_NAND_I32_POSTRA:
701 AND = Mips::AND;
702 NOR = Mips::NOR;
704 case Mips::ATOMIC_SWAP_I32_POSTRA:
707 case Mips::ATOMIC_LOAD_ADD_I64_POSTRA:
708 Opcode = Mips::DADDu;
710 case Mips::ATOMIC_LOAD_SUB_I64_POSTRA:
711 Opcode = Mips::DSUBu;
713 case Mips::ATOMIC_LOAD_AND_I64_POSTRA:
714 Opcode = Mips::AND64;
716 case Mips::ATOMIC_LOAD_OR_I64_POSTRA:
717 Opcode = Mips::OR64;
719 case Mips::ATOMIC_LOAD_XOR_I64_POSTRA:
720 Opcode = Mips::XOR64;
722 case Mips::ATOMIC_LOAD_NAND_I64_POSTRA:
724 AND = Mips::AND64;
725 NOR = Mips::NOR64;
727 case Mips::ATOMIC_SWAP_I64_POSTRA:
730 case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA:
731 case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA:
734 case Mips::ATOMIC_LOAD_MIN_I32_POSTRA:
735 case Mips::ATOMIC_LOAD_MIN_I64_POSTRA:
738 case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA:
739 case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA:
742 case Mips::ATOMIC_LOAD_MAX_I32_POSTRA:
743 case Mips::ATOMIC_LOAD_MAX_I64_POSTRA:
776 (Size == 8) ? STI->getRegisterInfo()->getSubReg(Scratch2, Mips::sub_32)
859 case Mips::ATOMIC_CMP_SWAP_I32_POSTRA:
860 case Mips::ATOMIC_CMP_SWAP_I64_POSTRA:
862 case Mips::ATOMIC_CMP_SWAP_I8_POSTRA:
863 case Mips::ATOMIC_CMP_SWAP_I16_POSTRA:
865 case Mips::ATOMIC_SWAP_I8_POSTRA:
866 case Mips::ATOMIC_SWAP_I16_POSTRA:
867 case Mips::ATOMIC_LOAD_NAND_I8_POSTRA:
868 case Mips::ATOMIC_LOAD_NAND_I16_POSTRA:
869 case Mips::ATOMIC_LOAD_ADD_I8_POSTRA:
870 case Mips::ATOMIC_LOAD_ADD_I16_POSTRA:
871 case Mips::ATOMIC_LOAD_SUB_I8_POSTRA:
872 case Mips::ATOMIC_LOAD_SUB_I16_POSTRA:
873 case Mips::ATOMIC_LOAD_AND_I8_POSTRA:
874 case Mips::ATOMIC_LOAD_AND_I16_POSTRA:
875 case Mips::ATOMIC_LOAD_OR_I8_POSTRA:
876 case Mips::ATOMIC_LOAD_OR_I16_POSTRA:
877 case Mips::ATOMIC_LOAD_XOR_I8_POSTRA:
878 case Mips::ATOMIC_LOAD_XOR_I16_POSTRA:
879 case Mips::ATOMIC_LOAD_MIN_I8_POSTRA:
880 case Mips::ATOMIC_LOAD_MIN_I16_POSTRA:
881 case Mips::ATOMIC_LOAD_MAX_I8_POSTRA:
882 case Mips::ATOMIC_LOAD_MAX_I16_POSTRA:
883 case Mips::ATOMIC_LOAD_UMIN_I8_POSTRA:
884 case Mips::ATOMIC_LOAD_UMIN_I16_POSTRA:
885 case Mips::ATOMIC_LOAD_UMAX_I8_POSTRA:
886 case Mips::ATOMIC_LOAD_UMAX_I16_POSTRA:
888 case Mips::ATOMIC_LOAD_ADD_I32_POSTRA:
889 case Mips::ATOMIC_LOAD_SUB_I32_POSTRA:
890 case Mips::ATOMIC_LOAD_AND_I32_POSTRA:
891 case Mips::ATOMIC_LOAD_OR_I32_POSTRA:
892 case Mips::ATOMIC_LOAD_XOR_I32_POSTRA:
893 case Mips::ATOMIC_LOAD_NAND_I32_POSTRA:
894 case Mips::ATOMIC_SWAP_I32_POSTRA:
895 case Mips::ATOMIC_LOAD_MIN_I32_POSTRA:
896 case Mips::ATOMIC_LOAD_MAX_I32_POSTRA:
897 case Mips::ATOMIC_LOAD_UMIN_I32_POSTRA:
898 case Mips::ATOMIC_LOAD_UMAX_I32_POSTRA:
900 case Mips::ATOMIC_LOAD_ADD_I64_POSTRA:
901 case Mips::ATOMIC_LOAD_SUB_I64_POSTRA:
902 case Mips::ATOMIC_LOAD_AND_I64_POSTRA:
903 case Mips::ATOMIC_LOAD_OR_I64_POSTRA:
904 case Mips::ATOMIC_LOAD_XOR_I64_POSTRA:
905 case Mips::ATOMIC_LOAD_NAND_I64_POSTRA:
906 case Mips::ATOMIC_SWAP_I64_POSTRA:
907 case Mips::ATOMIC_LOAD_MIN_I64_POSTRA:
908 case Mips::ATOMIC_LOAD_MAX_I64_POSTRA:
909 case Mips::ATOMIC_LOAD_UMIN_I64_POSTRA:
910 case Mips::ATOMIC_LOAD_UMAX_I64_POSTRA: