Lines Matching full:mips
1 //===- MipsInstrInfo.cpp - Mips Instruction Information -------------------===//
9 // This file contains the Mips implementation of the TargetInstrInfo class.
41 : MipsGenInstrInfo(Mips::ADJCALLSTACKDOWN, Mips::ADJCALLSTACKUP),
61 BuildMI(MBB, MI, DL, get(Mips::NOP));
70 Subtarget.hasMips32r6() ? Mips::SLL_MMR6 : Mips::SLL_MM;
72 Subtarget.inMicroMipsMode() ? MMOpc : (unsigned)Mips::SLL;
73 return BuildMI(MBB, MI, DL, get(Opc), Mips::ZERO)
74 .addReg(Mips::ZERO)
150 "# of Mips branch conditions must be <= 3!");
199 "Invalid Mips branch condition!");
295 case Mips::B:
296 case Mips::BAL:
297 case Mips::BAL_BR:
298 case Mips::BAL_BR_MM:
299 case Mips::BC1F:
300 case Mips::BC1FL:
301 case Mips::BC1T:
302 case Mips::BC1TL:
303 case Mips::BEQ: case Mips::BEQ64:
304 case Mips::BEQL:
305 case Mips::BGEZ: case Mips::BGEZ64:
306 case Mips::BGEZL:
307 case Mips::BGEZAL:
308 case Mips::BGEZALL:
309 case Mips::BGTZ: case Mips::BGTZ64:
310 case Mips::BGTZL:
311 case Mips::BLEZ: case Mips::BLEZ64:
312 case Mips::BLEZL:
313 case Mips::BLTZ: case Mips::BLTZ64:
314 case Mips::BLTZL:
315 case Mips::BLTZAL:
316 case Mips::BLTZALL:
317 case Mips::BNE: case Mips::BNE64:
318 case Mips::BNEL:
322 case Mips::B_MM:
323 case Mips::BC1F_MM:
324 case Mips::BC1T_MM:
325 case Mips::BEQ_MM:
326 case Mips::BGEZ_MM:
327 case Mips::BGEZAL_MM:
328 case Mips::BGTZ_MM:
329 case Mips::BLEZ_MM:
330 case Mips::BLTZ_MM:
331 case Mips::BLTZAL_MM:
332 case Mips::BNE_MM:
333 case Mips::BEQZC_MM:
334 case Mips::BNEZC_MM:
338 case Mips::B16_MM:
341 case Mips::BEQZ16_MM:
342 case Mips::BNEZ16_MM:
346 case Mips::BALC:
347 case Mips::BC:
350 case Mips::BC1EQZ:
351 case Mips::BC1NEZ:
352 case Mips::BC2EQZ:
353 case Mips::BC2NEZ:
354 case Mips::BEQC: case Mips::BEQC64:
355 case Mips::BNEC: case Mips::BNEC64:
356 case Mips::BGEC: case Mips::BGEC64:
357 case Mips::BGEUC: case Mips::BGEUC64:
358 case Mips::BGEZC: case Mips::BGEZC64:
359 case Mips::BGTZC: case Mips::BGTZC64:
360 case Mips::BLEZC: case Mips::BLEZC64:
361 case Mips::BLTC: case Mips::BLTC64:
362 case Mips::BLTUC: case Mips::BLTUC64:
363 case Mips::BLTZC: case Mips::BLTZC64:
364 case Mips::BNVC:
365 case Mips::BOVC:
366 case Mips::BGEZALC:
367 case Mips::BEQZALC:
368 case Mips::BGTZALC:
369 case Mips::BLEZALC:
370 case Mips::BLTZALC:
371 case Mips::BNEZALC:
374 case Mips::BEQZC: case Mips::BEQZC64:
375 case Mips::BNEZC: case Mips::BNEZC64:
379 case Mips::BC16_MMR6:
382 case Mips::BEQZC16_MMR6:
383 case Mips::BNEZC16_MMR6:
386 case Mips::BALC_MMR6:
387 case Mips::BC_MMR6:
390 case Mips::BC1EQZC_MMR6:
391 case Mips::BC1NEZC_MMR6:
392 case Mips::BC2EQZC_MMR6:
393 case Mips::BC2NEZC_MMR6:
394 case Mips::BGEZALC_MMR6:
395 case Mips::BEQZALC_MMR6:
396 case Mips::BGTZALC_MMR6:
397 case Mips::BLEZALC_MMR6:
398 case Mips::BLTZALC_MMR6:
399 case Mips::BNEZALC_MMR6:
400 case Mips::BNVC_MMR6:
401 case Mips::BOVC_MMR6:
404 case Mips::BEQC_MMR6:
405 case Mips::BNEC_MMR6:
406 case Mips::BGEC_MMR6:
407 case Mips::BGEUC_MMR6:
408 case Mips::BGEZC_MMR6:
409 case Mips::BGTZC_MMR6:
410 case Mips::BLEZC_MMR6:
411 case Mips::BLTC_MMR6:
412 case Mips::BLTUC_MMR6:
413 case Mips::BLTZC_MMR6:
416 case Mips::BEQZC_MMR6:
417 case Mips::BNEZC_MMR6:
421 case Mips::BPOSGE32:
423 case Mips::BPOSGE32_MM:
424 case Mips::BPOSGE32C_MMR3:
428 case Mips::BBIT0:
429 case Mips::BBIT032:
430 case Mips::BBIT1:
431 case Mips::BBIT132:
435 case Mips::BZ_B:
436 case Mips::BZ_H:
437 case Mips::BZ_W:
438 case Mips::BZ_D:
439 case Mips::BZ_V:
440 case Mips::BNZ_B:
441 case Mips::BNZ_H:
442 case Mips::BNZ_W:
443 case Mips::BNZ_D:
444 case Mips::BNZ_V:
459 case Mips::BNE:
460 case Mips::BNE_MM:
461 case Mips::BEQ:
462 case Mips::BEQ_MM:
470 case Mips::JR:
471 case Mips::PseudoReturn:
472 case Mips::PseudoIndirectBranch:
481 (I->getOperand(0).getReg() == Mips::ZERO ||
482 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
484 (I->getOperand(1).getReg() == Mips::ZERO ||
485 I->getOperand(1).getReg() == Mips::ZERO_64)))
490 case Mips::B:
491 return Mips::BC;
492 case Mips::BAL:
493 return Mips::BALC;
494 case Mips::BEQ:
495 case Mips::BEQ_MM:
497 return Mips::BEQZC_MM;
500 return Mips::BEQC;
501 case Mips::BNE:
502 case Mips::BNE_MM:
504 return Mips::BNEZC_MM;
507 return Mips::BNEC;
508 case Mips::BGE:
511 return Mips::BGEC;
512 case Mips::BGEU:
515 return Mips::BGEUC;
516 case Mips::BGEZ:
517 return Mips::BGEZC;
518 case Mips::BGTZ:
519 return Mips::BGTZC;
520 case Mips::BLEZ:
521 return Mips::BLEZC;
522 case Mips::BLT:
525 return Mips::BLTC;
526 case Mips::BLTU:
529 return Mips::BLTUC;
530 case Mips::BLTZ:
531 return Mips::BLTZC;
532 case Mips::BEQ64:
535 return Mips::BEQC64;
536 case Mips::BNE64:
539 return Mips::BNEC64;
540 case Mips::BGTZ64:
541 return Mips::BGTZC64;
542 case Mips::BGEZ64:
543 return Mips::BGEZC64;
544 case Mips::BLTZ64:
545 return Mips::BLTZC64;
546 case Mips::BLEZ64:
547 return Mips::BLEZC64;
550 case Mips::JR:
551 case Mips::PseudoIndirectBranchR6:
552 case Mips::PseudoReturn:
553 case Mips::TAILCALLR6REG:
555 return Mips::JRC16_MM;
556 return Mips::JIC;
557 case Mips::JALRPseudo:
558 return Mips::JIALC;
559 case Mips::JR64:
560 case Mips::PseudoIndirectBranch64R6:
561 case Mips::PseudoReturn64:
562 case Mips::TAILCALL64R6REG:
563 return Mips::JIC64;
564 case Mips::JALR64Pseudo:
565 return Mips::JIALC64;
593 case Mips::BC1F:
594 case Mips::BC1FL:
595 case Mips::BC1T:
596 case Mips::BC1TL:
634 case Mips::MTC1:
635 case Mips::MFC1:
636 case Mips::MTC1_D64:
637 case Mips::MFC1_D64:
638 case Mips::DMTC1:
639 case Mips::DMFC1:
640 case Mips::FCMP_S32:
641 case Mips::FCMP_D32:
642 case Mips::FCMP_D64:
653 case Mips::LB:
654 case Mips::LBu:
655 case Mips::LH:
656 case Mips::LHu:
657 case Mips::LW:
658 case Mips::LWR:
659 case Mips::LWL:
677 case Mips::CONSTPOOL_ENTRY:
695 // Mips::ZERO, which is incorrect. This test should be updated to use
702 ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, TRI, false);
708 case Mips::BEQC:
709 NewOpc = Mips::BEQZC;
711 case Mips::BNEC:
712 NewOpc = Mips::BNEZC;
714 case Mips::BGEC:
715 NewOpc = Mips::BGEZC;
717 case Mips::BLTC:
718 NewOpc = Mips::BLTZC;
720 case Mips::BEQC64:
721 NewOpc = Mips::BEQZC64;
723 case Mips::BNEC64:
724 NewOpc = Mips::BNEZC64;
735 if (NewOpc == Mips::JIC || NewOpc == Mips::JIALC || NewOpc == Mips::JIC64 ||
736 NewOpc == Mips::JIALC64) {
738 if (NewOpc == Mips::JIALC || NewOpc == Mips::JIALC64)
782 case Mips::DPADD_U_H:
783 case Mips::DPADD_U_W:
784 case Mips::DPADD_U_D:
785 case Mips::DPADD_S_H:
786 case Mips::DPADD_S_W:
787 case Mips::DPADD_S_D:
854 case Mips::EXT:
855 case Mips::EXT_MM:
856 case Mips::INS:
857 case Mips::INS_MM:
858 case Mips::DINS:
860 case Mips::DINSM:
867 case Mips::DINSU:
873 case Mips::DEXT:
875 case Mips::DEXTM:
877 case Mips::DEXTU:
879 case Mips::TAILCALLREG:
880 case Mips::PseudoIndirectBranch:
881 case Mips::JR:
882 case Mips::JR64:
883 case Mips::JALR:
884 case Mips::JALR64:
885 case Mips::JALRPseudo:
908 {MO_GOT, "mips-got"},
909 {MO_GOT_CALL, "mips-got-call"},
910 {MO_GPREL, "mips-gprel"},
911 {MO_ABS_HI, "mips-abs-hi"},
912 {MO_ABS_LO, "mips-abs-lo"},
913 {MO_TLSGD, "mips-tlsgd"},
914 {MO_TLSLDM, "mips-tlsldm"},
915 {MO_DTPREL_HI, "mips-dtprel-hi"},
916 {MO_DTPREL_LO, "mips-dtprel-lo"},
917 {MO_GOTTPREL, "mips-gottprel"},
918 {MO_TPREL_HI, "mips-tprel-hi"},
919 {MO_TPREL_LO, "mips-tprel-lo"},
920 {MO_GPOFF_HI, "mips-gpoff-hi"},
921 {MO_GPOFF_LO, "mips-gpoff-lo"},
922 {MO_GOT_DISP, "mips-got-disp"},
923 {MO_GOT_PAGE, "mips-got-page"},
924 {MO_GOT_OFST, "mips-got-ofst"},
925 {MO_HIGHER, "mips-higher"},
926 {MO_HIGHEST, "mips-highest"},
927 {MO_GOT_HI16, "mips-got-hi16"},
928 {MO_GOT_LO16, "mips-got-lo16"},
929 {MO_CALL_HI16, "mips-call-hi16"},
930 {MO_CALL_LO16, "mips-call-lo16"},
931 {MO_JALR, "mips-jalr"}
941 // TODO: Special MIPS instructions that need to be described separately.
947 if (SrcReg == Mips::ZERO || SrcReg == Mips::ZERO_64) {
974 case Mips::ADDiu:
975 case Mips::DADDiu: {