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/llvm-project/llvm/test/CodeGen/AArch64/
H A Dcomplex-deinterleaving-add-mull-fixed-contract.ll10 ; CHECK-NEXT: zip2 v4.2d, v2.2d, v3.2d
11 ; CHECK-NEXT: zip2 v5.2d, v0.2d, v1.2d
12 ; CHECK-NEXT: zip1 v0.2d, v0.2d, v1.2d
13 ; CHECK-NEXT: zip1 v2.2d, v2.2d, v3.2d
14 ; CHECK-NEXT: fmul v1.2d, v5.2d, v4.2d
15 ; CHECK-NEXT: fmul v3.2d, v0.2d, v4.2d
16 ; CHECK-NEXT: fneg v1.2d, v1.2d
17 ; CHECK-NEXT: fmla v3.2d, v2.2d, v5.2d
18 ; CHECK-NEXT: fmla v1.2d, v2.2d, v0.2d
19 ; CHECK-NEXT: fadd v1.2d, v2.2d, v1.2d
[all …]
H A Dcomplex-deinterleaving-add-mull-scalable-contract.ll10 ; CHECK-NEXT: uzp2 z6.d, z0.d, z1.d
11 ; CHECK-NEXT: uzp1 z0.d, z0.d, z1.d
12 ; CHECK-NEXT: uzp2 z1.d, z2.d, z3.d
13 ; CHECK-NEXT: uzp1 z2.d, z2.d, z3.d
14 ; CHECK-NEXT: ptrue p0.d
15 ; CHECK-NEXT: fmul z7.d, z0.d, z1.d
16 ; CHECK-NEXT: fmul z1.d, z6.d, z1.d
18 ; CHECK-NEXT: fmla z3.d, p0/m, z6.d, z2.d
19 ; CHECK-NEXT: fnmsb z0.d, p0/m, z2.d, z1.d
20 ; CHECK-NEXT: uzp2 z1.d, z4.d, z5.d
[all …]
H A Dcomplex-deinterleaving-add-mull-fixed-fast.ll10 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #0
11 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #0
12 ; CHECK-NEXT: fcmla v4.2d, v0.2d, v2.2d, #90
13 ; CHECK-NEXT: fcmla v5.2d, v1.2d, v3.2d, #90
18 %strided.vec = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 0, i32 2>
19 %strided.vec28 = shufflevector <4 x double> %a, <4 x double> poison, <2 x i32> <i32 1, i32 3>
20 %strided.vec30 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 0, i32 2>
21 %strided.vec31 = shufflevector <4 x double> %b, <4 x double> poison, <2 x i32> <i32 1, i32 3>
22 %0 = fmul fast <2 x double> %strided.vec31, %strided.vec
23 %1 = fmul fast <2 x double> %strided.vec30, %strided.vec28
[all …]
H A Dcomplex-deinterleaving-add-mull-scalable-fast.ll10 ; CHECK-NEXT: ptrue p0.d
11 ; CHECK-NEXT: fcmla z4.d, p0/m, z0.d, z2.d, #0
12 ; CHECK-NEXT: fcmla z5.d, p0/m, z1.d, z3.d, #0
13 ; CHECK-NEXT: fcmla z4.d, p0/m, z0.d, z2.d, #90
14 ; CHECK-NEXT: fcmla z5.d, p0/m, z1.d, z3.d, #90
15 ; CHECK-NEXT: mov z0.d, z4.d
16 ; CHECK-NEXT: mov z1.d, z5.d
19 …%strided.vec = tail call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.vector.deinterleav…
20 %0 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %strided.vec, 0
21 %1 = extractvalue { <vscale x 2 x double>, <vscale x 2 x double> } %strided.vec, 1
[all …]
H A Dsve-gep.ll10 %d = getelementptr <vscale x 2 x i64>, ptr %base, i64 4
11 ret ptr %d
20 %d = getelementptr <vscale x 2 x i64>, ptr %base, i64 %offset
21 ret ptr %d
30 %d = getelementptr <vscale x 2 x i32>, ptr %base, i64 %offset
31 ret ptr %d
34 define <2 x ptr> @fixed_of_scalable_1(ptr %base) {
38 ; CHECK-NEXT: dup v1.2d, x0
39 ; CHECK-NEXT: dup v0.2d, x8
40 ; CHECK-NEXT: add v0.2d, v1.2d, v0.2d
[all …]
H A Dsqrt-fastmath.ll6 declare <2 x float> @llvm.sqrt.v2f32(<2 x float>) #0
10 declare <2 x double> @llvm.sqrt.v2f64(<2 x double>) #0
59 define <2 x float> @f2sqrt(<2 x float> %a) #0 {
62 ; FAULT-NEXT: fsqrt v0.2s, v0.2s
67 ; CHECK-NEXT: frsqrte v1.2s, v0.2s
68 ; CHECK-NEXT: fmul v2.2s, v1.2s, v1.2s
69 ; CHECK-NEXT: frsqrts v2.2s, v0.2s, v2.2s
70 ; CHECK-NEXT: fmul v1.2s, v1.2s, v2.2s
71 ; CHECK-NEXT: fmul v2.2s, v1.2s, v1.2s
72 ; CHECK-NEXT: fmul v1.2s, v0.2s, v1.2s
[all …]
H A Dvector-llrint.ll17 define <2 x i64> @llrint_v1i64_v2f16(<2 x half> %x) {
29 ; CHECK-NEXT: mov v0.d[1], x9
31 %a = call <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half> %x)
32 ret <2 x i64> %a
34 declare <2 x i64> @llvm.llrint.v2i64.v2f16(<2 x half>)
40 ; CHECK-NEXT: mov h1, v0.h[2]
57 ; CHECK-NEXT: mov v0.d[1], x10
58 ; CHECK-NEXT: mov v1.d[1], x11
69 ; CHECK-NEXT: mov h4, v0.h[2]
73 ; CHECK-NEXT: mov h2, v1.h[2]
[all …]
H A Dcomplex-deinterleaving-splat-scalable.ll11 ; CHECK-NEXT: mov z4.d, #0 // =0x0
12 ; CHECK-NEXT: ptrue p0.d
13 ; CHECK-NEXT: fmov z7.d, #3.00000000
14 ; CHECK-NEXT: fmov z24.d, #11.00000000
15 ; CHECK-NEXT: mov z6.d, z4.d
16 ; CHECK-NEXT: mov z5.d, z4.d
17 ; CHECK-NEXT: fcmla z6.d, p0/m, z1.d, z3.d, #0
18 ; CHECK-NEXT: fcmla z5.d, p0/m, z0.d, z2.d, #0
19 ; CHECK-NEXT: fcmla z6.d, p0/m, z1.d, z3.d, #90
20 ; CHECK-NEXT: zip2 z1.d, z24.d, z7.d
[all …]
H A Dsme2-intrinsics-max.ll9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
[all...]
H A Dsme2-intrinsics-min.ll9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
[all...]
H A Dsme2-intrinsics-rshl.ll9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
35 ; CHECK-NEXT: mov z5.d, z2.d
36 ; CHECK-NEXT: mov z4.d, z1.d
[all …]
H A Dvector-fcvt.ll90 ; CHECK-NEXT: scvtf v0.2d, v0.2d
91 ; CHECK-NEXT: scvtf v2.2d, v2.2d
92 ; CHECK-NEXT: scvtf v4.2d, v1.2d
93 ; CHECK-NEXT: fcvtn v0.2s, v0.2d
94 ; CHECK-NEXT: fcvtn v1.2s, v2.2d
95 ; CHECK-NEXT: scvtf v2.2d, v3.2d
96 ; CHECK-NEXT: fcvtn2 v0.4s, v4.2d
97 ; CHECK-NEXT: fcvtn2 v1.4s, v2.2d
180 ; CHECK-NEXT: ucvtf v0.2d, v0.2d
181 ; CHECK-NEXT: ucvtf v2.2d, v2.2d
[all …]
H A Dsve2-eor3.ll5 … 16 x i8> @eor3_nxv16i8_left(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
8 ; SVE-NEXT: eor z0.d, z0.d, z1.d
9 ; SVE-NEXT: eor z0.d, z0.d, z2.d
14 ; SVE2-NEXT: eor3 z0.d, z0.d, z1.d, z2.d
17 %5 = xor <vscale x 16 x i8> %4, %2
21 …16 x i8> @eor3_nxv16i8_right(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
24 ; SVE-NEXT: eor z0.d, z0.d, z1.d
25 ; SVE-NEXT: eor z0.d, z2.d, z0.d
30 ; SVE2-NEXT: eor3 z2.d, z2.d, z0.d, z1.d
31 ; SVE2-NEXT: mov z0.d, z2.d
[all …]
H A Dcomplex-deinterleaving-splat.ll12 ; CHECK-NEXT: movi v6.2d, #0000000000000000
13 ; CHECK-NEXT: movi v5.2d, #0000000000000000
15 ; CHECK-NEXT: movi v4.2d, #0000000000000000
16 ; CHECK-NEXT: fcmla v6.2d, v1.2d, v3.2d, #0
17 ; CHECK-NEXT: fcmla v5.2d, v0.2d, v2.2d, #0
18 ; CHECK-NEXT: fcmla v6.2d, v1.2d, v3.2d, #90
20 ; CHECK-NEXT: fcmla v5.2d, v0.2d, v2.2d, #90
21 ; CHECK-NEXT: movi v0.2d, #0000000000000000
22 ; CHECK-NEXT: fcmla v4.2d, v6.2d, v1.2d, #0
23 ; CHECK-NEXT: fcmla v0.2d, v5.2d, v1.2d, #0
[all …]
H A Dsme2-intrinsics-sqdmulh.ll9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
35 ; CHECK-NEXT: mov z5.d, z2.d
36 ; CHECK-NEXT: mov z4.d, z1.d
[all …]
H A Dfp16-v16-instructions.ll26 ; CHECK-NEXT: scvtf v0.2d, v0.2d
27 ; CHECK-NEXT: scvtf v4.2d, v4.2d
28 ; CHECK-NEXT: scvtf v2.2d, v2.2d
29 ; CHECK-NEXT: scvtf v1.2d, v1.2d
30 ; CHECK-NEXT: scvtf v6.2d, v6.2d
31 ; CHECK-NEXT: scvtf v5.2d, v5.2d
32 ; CHECK-NEXT: scvtf v3.2d, v3.2d
33 ; CHECK-NEXT: fcvtn v0.2s, v0.2d
34 ; CHECK-NEXT: fcvtn v4.2s, v4.2d
35 ; CHECK-NEXT: fcvtn v2.2s, v2.2d
[all …]
H A Dsve2-xar.ll5 define <vscale x 2 x i64> @xar_nxv2i64_l(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
8 ; SVE-NEXT: eor z0.d, z0.d, z1.d
9 ; SVE-NEXT: lsr z1.d, z0.d, #4
10 ; SVE-NEXT: lsl z0.d, z0.d, #60
11 ; SVE-NEXT: orr z0.d, z0.d, z1.d
16 ; SVE2-NEXT: xar z0.d, z0.d, z1.d, #4
18 %a = xor <vscale x 2 x i64> %x, %y
19 …%b = call <vscale x 2 x i64> @llvm.fshl.nxv2i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %a, <vsc…
20 ret <vscale x 2 x i64> %b
23 define <vscale x 2 x i64> @xar_nxv2i64_r(<vscale x 2 x i64> %x, <vscale x 2 x i64> %y) {
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-ld4.s7 ld4r {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
8 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
10 ld4 {v0.d, v1.d, v2.d, v3.d}[0], [sp]
11 ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
12 ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
15 ld4r {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #16
16 ld4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #32
18 ld4 {v0.d, v1.d, v2.d, v3.d}[0], [sp], #32
19 ld4r {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #32
20 ld4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64
[all …]
H A Dasimd-st1.s7 st1 {v0.2s}, [sp]
8 st1 {v0.2s, v1.2s}, [sp]
9 st1 {v0.2s, v1.2s, v2.2s}, [sp]
10 st1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
12 st1 {v0.d}[0], [sp]
13 st1 {v0.2d}, [sp]
14 st1 {v0.2d, v1.2d}, [sp]
15 st1 {v0.2d, v1.2d, v2.2d}, [sp]
16 st1 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
19 st1 {v0.2s}, [sp], #8
[all …]
H A Dasimd-ld3.s7 ld3r {v0.2s, v1.2s, v2.2s}, [sp]
8 ld3 {v0.2s, v1.2s, v2.2s}, [sp]
10 ld3 {v0.d, v1.d, v2.d}[0], [sp]
11 ld3r {v0.2d, v1.2d, v2.2d}, [sp]
12 ld3 {v0.2d, v1.2d, v2.2d}, [sp]
15 ld3r {v0.2s, v1.2s, v2.2s}, [sp], #12
16 ld3 {v0.2s, v1.2s, v2.2s}, [sp], #24
18 ld3 {v0.d, v1.d, v2.d}[0], [sp], #24
19 ld3r {v0.2d, v1.2d, v2.2d}, [sp], #24
20 ld3 {v0.2d, v1.2d, v2.2d}, [sp], #48
[all …]
H A Dasimd-ld1.s7 ld1r {v0.2s}, [sp]
8 ld1 {v0.2s}, [sp]
9 ld1 {v0.2s, v1.2s}, [sp]
10 ld1 {v0.2s, v1.2s, v2.2s}, [sp]
11 ld1 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
13 ld1 {v0.d}[0], [sp]
14 ld1r {v0.2d}, [sp]
15 ld1 {v0.2d}, [sp]
16 ld1 {v0.2d, v1.2d}, [sp]
17 ld1 {v0.2d, v1.2d, v2.2d}, [sp]
[all …]
H A Dasimd-st4.s7 st4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp]
9 st4 {v0.d, v1.d, v2.d, v3.d}[0], [sp]
10 st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp]
13 st4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], #32
15 st4 {v0.d, v1.d, v2.d, v3.d}[0], [sp], #32
16 st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], #64
19 st4 {v0.2s, v1.2s, v2.2s, v3.2s}, [sp], x0
21 st4 {v0.d, v1.d, v2.d, v3.d}[0], [sp], x0
22 st4 {v0.2d, v1.2d, v2.2d, v3.2d}, [sp], x0
52 # ALL-NEXT: [2]: Latency
[all …]
H A Dasimd-st3.s7 st3 {v0.2s, v1.2s, v2.2s}, [sp]
9 st3 {v0.d, v1.d, v2.d}[0], [sp]
10 st3 {v0.2d, v1.2d, v2.2d}, [sp]
13 st3 {v0.2s, v1.2s, v2.2s}, [sp], #24
15 st3 {v0.d, v1.d, v2.d}[0], [sp], #24
16 st3 {v0.2d, v1.2d, v2.2d}, [sp], #48
19 st3 {v0.2s, v1.2s, v2.2s}, [sp], x0
21 st3 {v0.d, v1.d, v2.d}[0], [sp], x0
22 st3 {v0.2d, v1.2d, v2.2d}, [sp], x0
52 # ALL-NEXT: [2]: Latency
[all …]
H A Dasimd-ld2.s7 ld2r {v0.2s, v1.2s}, [sp]
8 ld2 {v0.2s, v1.2s}, [sp]
10 ld2 {v0.d, v1.d}[0], [sp]
11 ld2r {v0.2d, v1.2d}, [sp]
12 ld2 {v0.2d, v1.2d}, [sp]
15 ld2r {v0.2s, v1.2s}, [sp], #8
16 ld2 {v0.2s, v1.2s}, [sp], #16
18 ld2 {v0.d, v1.d}[0], [sp], #16
19 ld2r {v0.2d, v1.2d}, [sp], #16
20 ld2 {v0.2d, v1.2d}, [sp], #32
[all …]
/llvm-project/llvm/test/tools/llvm-mca/AArch64/Neoverse/
H A DV2-forwarding.s2 …instruction-info=0 --resource-pressure=0 --timeline --timeline-max-iterations=2 < %s | FileCheck %s
71 sadalp v0.2d, v1.4s
72 sadalp v0.2d, v1.4s
73 sadalp v0.2d, v0.4s
78 ssra v0.2d, v1.2d, #1
79 ssra v0.2d, v1.2d, #1
80 ssra v0.2d, v0.2d, #1
85 fcmla v0.2d, v1.2d, v2.2d, #90
86 fcmla v0.2d, v1.2d, v2.2d, #90
87 fcmla v0.2d, v0.2d, v1.2d, #90
[all …]

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