Lines Matching +full:2 +full:d
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
35 ; CHECK-NEXT: mov z5.d, z2.d
36 ; CHECK-NEXT: mov z4.d, z1.d
38 ; CHECK-NEXT: mov z0.d, z4.d
39 ; CHECK-NEXT: mov z1.d, z5.d
45 …2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_single_x2_s64(<vscale x 2 x i64> %dummy, <v…
48 ; CHECK-NEXT: mov z5.d, z2.d
49 ; CHECK-NEXT: mov z4.d, z1.d
50 ; CHECK-NEXT: srshl { z4.d, z5.d }, { z4.d, z5.d }, z3.d
51 ; CHECK-NEXT: mov z0.d, z4.d
52 ; CHECK-NEXT: mov z1.d, z5.d
54 …scale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64…
55 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
63 ; CHECK-NEXT: mov z27.d, z4.d
64 ; CHECK-NEXT: mov z26.d, z3.d
65 ; CHECK-NEXT: mov z25.d, z2.d
66 ; CHECK-NEXT: mov z24.d, z1.d
68 ; CHECK-NEXT: mov z0.d, z24.d
69 ; CHECK-NEXT: mov z1.d, z25.d
70 ; CHECK-NEXT: mov z2.d, z26.d
71 ; CHECK-NEXT: mov z3.d, z27.d
81 ; CHECK-NEXT: mov z27.d, z4.d
82 ; CHECK-NEXT: mov z26.d, z3.d
83 ; CHECK-NEXT: mov z25.d, z2.d
84 ; CHECK-NEXT: mov z24.d, z1.d
86 ; CHECK-NEXT: mov z0.d, z24.d
87 ; CHECK-NEXT: mov z1.d, z25.d
88 ; CHECK-NEXT: mov z2.d, z26.d
89 ; CHECK-NEXT: mov z3.d, z27.d
99 ; CHECK-NEXT: mov z27.d, z4.d
100 ; CHECK-NEXT: mov z26.d, z3.d
101 ; CHECK-NEXT: mov z25.d, z2.d
102 ; CHECK-NEXT: mov z24.d, z1.d
104 ; CHECK-NEXT: mov z0.d, z24.d
105 ; CHECK-NEXT: mov z1.d, z25.d
106 ; CHECK-NEXT: mov z2.d, z26.d
107 ; CHECK-NEXT: mov z3.d, z27.d
114 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_sin…
117 ; CHECK-NEXT: mov z27.d, z4.d
118 ; CHECK-NEXT: mov z26.d, z3.d
119 ; CHECK-NEXT: mov z25.d, z2.d
120 ; CHECK-NEXT: mov z24.d, z1.d
121 ; CHECK-NEXT: srshl { z24.d - z27.d }, { z24.d - z27.d }, z5.d
122 ; CHECK-NEXT: mov z0.d, z24.d
123 ; CHECK-NEXT: mov z1.d, z25.d
124 ; CHECK-NEXT: mov z2.d, z26.d
125 ; CHECK-NEXT: mov z3.d, z27.d
127 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
128 …le.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscal…
129 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
137 ; CHECK-NEXT: mov z5.d, z2.d
138 ; CHECK-NEXT: mov z4.d, z1.d
140 ; CHECK-NEXT: mov z0.d, z4.d
141 ; CHECK-NEXT: mov z1.d, z5.d
150 ; CHECK-NEXT: mov z5.d, z2.d
151 ; CHECK-NEXT: mov z4.d, z1.d
153 ; CHECK-NEXT: mov z0.d, z4.d
154 ; CHECK-NEXT: mov z1.d, z5.d
163 ; CHECK-NEXT: mov z5.d, z2.d
164 ; CHECK-NEXT: mov z4.d, z1.d
166 ; CHECK-NEXT: mov z0.d, z4.d
167 ; CHECK-NEXT: mov z1.d, z5.d
173 …2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_single_x2_u64(<vscale x 2 x i64> %dummy, <v…
176 ; CHECK-NEXT: mov z5.d, z2.d
177 ; CHECK-NEXT: mov z4.d, z1.d
178 ; CHECK-NEXT: urshl { z4.d, z5.d }, { z4.d, z5.d }, z3.d
179 ; CHECK-NEXT: mov z0.d, z4.d
180 ; CHECK-NEXT: mov z1.d, z5.d
182 …scale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.single.x2.nxv2i64(<vscale x 2 x i64…
183 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
191 ; CHECK-NEXT: mov z27.d, z4.d
192 ; CHECK-NEXT: mov z26.d, z3.d
193 ; CHECK-NEXT: mov z25.d, z2.d
194 ; CHECK-NEXT: mov z24.d, z1.d
196 ; CHECK-NEXT: mov z0.d, z24.d
197 ; CHECK-NEXT: mov z1.d, z25.d
198 ; CHECK-NEXT: mov z2.d, z26.d
199 ; CHECK-NEXT: mov z3.d, z27.d
209 ; CHECK-NEXT: mov z27.d, z4.d
210 ; CHECK-NEXT: mov z26.d, z3.d
211 ; CHECK-NEXT: mov z25.d, z2.d
212 ; CHECK-NEXT: mov z24.d, z1.d
214 ; CHECK-NEXT: mov z0.d, z24.d
215 ; CHECK-NEXT: mov z1.d, z25.d
216 ; CHECK-NEXT: mov z2.d, z26.d
217 ; CHECK-NEXT: mov z3.d, z27.d
227 ; CHECK-NEXT: mov z27.d, z4.d
228 ; CHECK-NEXT: mov z26.d, z3.d
229 ; CHECK-NEXT: mov z25.d, z2.d
230 ; CHECK-NEXT: mov z24.d, z1.d
232 ; CHECK-NEXT: mov z0.d, z24.d
233 ; CHECK-NEXT: mov z1.d, z25.d
234 ; CHECK-NEXT: mov z2.d, z26.d
235 ; CHECK-NEXT: mov z3.d, z27.d
242 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_sin…
245 ; CHECK-NEXT: mov z27.d, z4.d
246 ; CHECK-NEXT: mov z26.d, z3.d
247 ; CHECK-NEXT: mov z25.d, z2.d
248 ; CHECK-NEXT: mov z24.d, z1.d
249 ; CHECK-NEXT: urshl { z24.d - z27.d }, { z24.d - z27.d }, z5.d
250 ; CHECK-NEXT: mov z0.d, z24.d
251 ; CHECK-NEXT: mov z1.d, z25.d
252 ; CHECK-NEXT: mov z2.d, z26.d
253 ; CHECK-NEXT: mov z3.d, z27.d
255 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
256 …le.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscal…
257 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
265 ; CHECK-NEXT: mov z7.d, z4.d
266 ; CHECK-NEXT: mov z5.d, z2.d
267 ; CHECK-NEXT: mov z6.d, z3.d
268 ; CHECK-NEXT: mov z4.d, z1.d
270 ; CHECK-NEXT: mov z0.d, z4.d
271 ; CHECK-NEXT: mov z1.d, z5.d
280 ; CHECK-NEXT: mov z7.d, z4.d
281 ; CHECK-NEXT: mov z5.d, z2.d
282 ; CHECK-NEXT: mov z6.d, z3.d
283 ; CHECK-NEXT: mov z4.d, z1.d
285 ; CHECK-NEXT: mov z0.d, z4.d
286 ; CHECK-NEXT: mov z1.d, z5.d
295 ; CHECK-NEXT: mov z7.d, z4.d
296 ; CHECK-NEXT: mov z5.d, z2.d
297 ; CHECK-NEXT: mov z6.d, z3.d
298 ; CHECK-NEXT: mov z4.d, z1.d
300 ; CHECK-NEXT: mov z0.d, z4.d
301 ; CHECK-NEXT: mov z1.d, z5.d
307 …2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_x2_s64(<vscale x 2 x i64> %dummy, <vscale x…
310 ; CHECK-NEXT: mov z7.d, z4.d
311 ; CHECK-NEXT: mov z5.d, z2.d
312 ; CHECK-NEXT: mov z6.d, z3.d
313 ; CHECK-NEXT: mov z4.d, z1.d
314 ; CHECK-NEXT: srshl { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
315 ; CHECK-NEXT: mov z0.d, z4.d
316 ; CHECK-NEXT: mov z1.d, z5.d
318 …2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscal…
319 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
327 ; CHECK-NEXT: mov z30.d, z7.d
328 ; CHECK-NEXT: mov z27.d, z4.d
330 ; CHECK-NEXT: mov z29.d, z6.d
331 ; CHECK-NEXT: mov z26.d, z3.d
332 ; CHECK-NEXT: mov z28.d, z5.d
333 ; CHECK-NEXT: mov z25.d, z2.d
335 ; CHECK-NEXT: mov z24.d, z1.d
337 ; CHECK-NEXT: mov z0.d, z24.d
338 ; CHECK-NEXT: mov z1.d, z25.d
339 ; CHECK-NEXT: mov z2.d, z26.d
340 ; CHECK-NEXT: mov z3.d, z27.d
351 ; CHECK-NEXT: mov z30.d, z7.d
352 ; CHECK-NEXT: mov z27.d, z4.d
354 ; CHECK-NEXT: mov z29.d, z6.d
355 ; CHECK-NEXT: mov z26.d, z3.d
356 ; CHECK-NEXT: mov z28.d, z5.d
357 ; CHECK-NEXT: mov z25.d, z2.d
359 ; CHECK-NEXT: mov z24.d, z1.d
361 ; CHECK-NEXT: mov z0.d, z24.d
362 ; CHECK-NEXT: mov z1.d, z25.d
363 ; CHECK-NEXT: mov z2.d, z26.d
364 ; CHECK-NEXT: mov z3.d, z27.d
375 ; CHECK-NEXT: mov z30.d, z7.d
376 ; CHECK-NEXT: mov z27.d, z4.d
378 ; CHECK-NEXT: mov z29.d, z6.d
379 ; CHECK-NEXT: mov z26.d, z3.d
380 ; CHECK-NEXT: mov z28.d, z5.d
381 ; CHECK-NEXT: mov z25.d, z2.d
383 ; CHECK-NEXT: mov z24.d, z1.d
385 ; CHECK-NEXT: mov z0.d, z24.d
386 ; CHECK-NEXT: mov z1.d, z25.d
387 ; CHECK-NEXT: mov z2.d, z26.d
388 ; CHECK-NEXT: mov z3.d, z27.d
396 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_x4_…
399 ; CHECK-NEXT: mov z30.d, z7.d
400 ; CHECK-NEXT: mov z27.d, z4.d
401 ; CHECK-NEXT: ptrue p0.d
402 ; CHECK-NEXT: mov z29.d, z6.d
403 ; CHECK-NEXT: mov z26.d, z3.d
404 ; CHECK-NEXT: mov z28.d, z5.d
405 ; CHECK-NEXT: mov z25.d, z2.d
406 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
407 ; CHECK-NEXT: mov z24.d, z1.d
408 ; CHECK-NEXT: srshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
409 ; CHECK-NEXT: mov z0.d, z24.d
410 ; CHECK-NEXT: mov z1.d, z25.d
411 ; CHECK-NEXT: mov z2.d, z26.d
412 ; CHECK-NEXT: mov z3.d, z27.d
414 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
415 …rch64.sve.srshl.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> …
416 …<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)
417 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
425 ; CHECK-NEXT: mov z7.d, z4.d
426 ; CHECK-NEXT: mov z5.d, z2.d
427 ; CHECK-NEXT: mov z6.d, z3.d
428 ; CHECK-NEXT: mov z4.d, z1.d
430 ; CHECK-NEXT: mov z0.d, z4.d
431 ; CHECK-NEXT: mov z1.d, z5.d
440 ; CHECK-NEXT: mov z7.d, z4.d
441 ; CHECK-NEXT: mov z5.d, z2.d
442 ; CHECK-NEXT: mov z6.d, z3.d
443 ; CHECK-NEXT: mov z4.d, z1.d
445 ; CHECK-NEXT: mov z0.d, z4.d
446 ; CHECK-NEXT: mov z1.d, z5.d
455 ; CHECK-NEXT: mov z7.d, z4.d
456 ; CHECK-NEXT: mov z5.d, z2.d
457 ; CHECK-NEXT: mov z6.d, z3.d
458 ; CHECK-NEXT: mov z4.d, z1.d
460 ; CHECK-NEXT: mov z0.d, z4.d
461 ; CHECK-NEXT: mov z1.d, z5.d
467 …2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_uhl_x2_u64(<vscale x 2 x i64> %dummy, <vscale x…
470 ; CHECK-NEXT: mov z7.d, z4.d
471 ; CHECK-NEXT: mov z5.d, z2.d
472 ; CHECK-NEXT: mov z6.d, z3.d
473 ; CHECK-NEXT: mov z4.d, z1.d
474 ; CHECK-NEXT: urshl { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
475 ; CHECK-NEXT: mov z0.d, z4.d
476 ; CHECK-NEXT: mov z1.d, z5.d
478 …2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscal…
479 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
487 ; CHECK-NEXT: mov z30.d, z7.d
488 ; CHECK-NEXT: mov z27.d, z4.d
490 ; CHECK-NEXT: mov z29.d, z6.d
491 ; CHECK-NEXT: mov z26.d, z3.d
492 ; CHECK-NEXT: mov z28.d, z5.d
493 ; CHECK-NEXT: mov z25.d, z2.d
495 ; CHECK-NEXT: mov z24.d, z1.d
497 ; CHECK-NEXT: mov z0.d, z24.d
498 ; CHECK-NEXT: mov z1.d, z25.d
499 ; CHECK-NEXT: mov z2.d, z26.d
500 ; CHECK-NEXT: mov z3.d, z27.d
511 ; CHECK-NEXT: mov z30.d, z7.d
512 ; CHECK-NEXT: mov z27.d, z4.d
514 ; CHECK-NEXT: mov z29.d, z6.d
515 ; CHECK-NEXT: mov z26.d, z3.d
516 ; CHECK-NEXT: mov z28.d, z5.d
517 ; CHECK-NEXT: mov z25.d, z2.d
519 ; CHECK-NEXT: mov z24.d, z1.d
521 ; CHECK-NEXT: mov z0.d, z24.d
522 ; CHECK-NEXT: mov z1.d, z25.d
523 ; CHECK-NEXT: mov z2.d, z26.d
524 ; CHECK-NEXT: mov z3.d, z27.d
535 ; CHECK-NEXT: mov z30.d, z7.d
536 ; CHECK-NEXT: mov z27.d, z4.d
538 ; CHECK-NEXT: mov z29.d, z6.d
539 ; CHECK-NEXT: mov z26.d, z3.d
540 ; CHECK-NEXT: mov z28.d, z5.d
541 ; CHECK-NEXT: mov z25.d, z2.d
543 ; CHECK-NEXT: mov z24.d, z1.d
545 ; CHECK-NEXT: mov z0.d, z24.d
546 ; CHECK-NEXT: mov z1.d, z25.d
547 ; CHECK-NEXT: mov z2.d, z26.d
548 ; CHECK-NEXT: mov z3.d, z27.d
556 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_x4_…
559 ; CHECK-NEXT: mov z30.d, z7.d
560 ; CHECK-NEXT: mov z27.d, z4.d
561 ; CHECK-NEXT: ptrue p0.d
562 ; CHECK-NEXT: mov z29.d, z6.d
563 ; CHECK-NEXT: mov z26.d, z3.d
564 ; CHECK-NEXT: mov z28.d, z5.d
565 ; CHECK-NEXT: mov z25.d, z2.d
566 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
567 ; CHECK-NEXT: mov z24.d, z1.d
568 ; CHECK-NEXT: urshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
569 ; CHECK-NEXT: mov z0.d, z24.d
570 ; CHECK-NEXT: mov z1.d, z25.d
571 ; CHECK-NEXT: mov z2.d, z26.d
572 ; CHECK-NEXT: mov z3.d, z27.d
574 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
575 …rch64.sve.urshl.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> …
576 …<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)
577 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
583 …e { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2…
588 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.sin…
593 …e { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.single.x2.nxv2i64(<vscale x 2…
598 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.sin…
603 …scale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.x2.nxv2i64(<vscale x 2 x i64>, <vsc…
611 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
612 …ale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <v…
617 …scale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.x2.nxv2i64(<vscale x 2 x i64>, <vsc…
625 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
626 …ale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <v…