Lines Matching +full:2 +full:d
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
35 ; CHECK-NEXT: mov z5.d, z2.d
36 ; CHECK-NEXT: mov z4.d, z1.d
38 ; CHECK-NEXT: mov z0.d, z4.d
39 ; CHECK-NEXT: mov z1.d, z5.d
45 define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_single_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {
48 ; CHECK-NEXT: mov z5.d, z2.d
49 ; CHECK-NEXT: mov z4.d, z1.d
50 ; CHECK-NEXT: smax { z4.d, z5.d }, { z4.d, z5.d }, z3.d
51 ; CHECK-NEXT: mov z0.d, z4.d
52 ; CHECK-NEXT: mov z1.d, z5.d
54 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)
55 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
63 ; CHECK-NEXT: mov z5.d, z2.d
64 ; CHECK-NEXT: mov z4.d, z1.d
66 ; CHECK-NEXT: mov z0.d, z4.d
67 ; CHECK-NEXT: mov z1.d, z5.d
76 ; CHECK-NEXT: mov z5.d, z2.d
77 ; CHECK-NEXT: mov z4.d, z1.d
79 ; CHECK-NEXT: mov z0.d, z4.d
80 ; CHECK-NEXT: mov z1.d, z5.d
89 ; CHECK-NEXT: mov z5.d, z2.d
90 ; CHECK-NEXT: mov z4.d, z1.d
92 ; CHECK-NEXT: mov z0.d, z4.d
93 ; CHECK-NEXT: mov z1.d, z5.d
99 define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_single_x2_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {
102 ; CHECK-NEXT: mov z5.d, z2.d
103 ; CHECK-NEXT: mov z4.d, z1.d
104 ; CHECK-NEXT: umax { z4.d, z5.d }, { z4.d, z5.d }, z3.d
105 ; CHECK-NEXT: mov z0.d, z4.d
106 ; CHECK-NEXT: mov z1.d, z5.d
108 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umax.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)
109 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
130 ; CHECK-NEXT: mov z5.d, z2.d
131 ; CHECK-NEXT: mov z4.d, z1.d
133 ; CHECK-NEXT: mov z0.d, z4.d
134 ; CHECK-NEXT: mov z1.d, z5.d
143 ; CHECK-NEXT: mov z5.d, z2.d
144 ; CHECK-NEXT: mov z4.d, z1.d
146 ; CHECK-NEXT: mov z0.d, z4.d
147 ; CHECK-NEXT: mov z1.d, z5.d
153 define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_single_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm) {
156 ; CHECK-NEXT: mov z5.d, z2.d
157 ; CHECK-NEXT: mov z4.d, z1.d
158 ; CHECK-NEXT: fmax { z4.d, z5.d }, { z4.d, z5.d }, z3.d
159 ; CHECK-NEXT: mov z0.d, z4.d
160 ; CHECK-NEXT: mov z1.d, z5.d
162 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmax.single.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm)
163 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
171 ; CHECK-NEXT: mov z27.d, z4.d
172 ; CHECK-NEXT: mov z26.d, z3.d
173 ; CHECK-NEXT: mov z25.d, z2.d
174 ; CHECK-NEXT: mov z24.d, z1.d
176 ; CHECK-NEXT: mov z0.d, z24.d
177 ; CHECK-NEXT: mov z1.d, z25.d
178 ; CHECK-NEXT: mov z2.d, z26.d
179 ; CHECK-NEXT: mov z3.d, z27.d
189 ; CHECK-NEXT: mov z27.d, z4.d
190 ; CHECK-NEXT: mov z26.d, z3.d
191 ; CHECK-NEXT: mov z25.d, z2.d
192 ; CHECK-NEXT: mov z24.d, z1.d
194 ; CHECK-NEXT: mov z0.d, z24.d
195 ; CHECK-NEXT: mov z1.d, z25.d
196 ; CHECK-NEXT: mov z2.d, z26.d
197 ; CHECK-NEXT: mov z3.d, z27.d
207 ; CHECK-NEXT: mov z27.d, z4.d
208 ; CHECK-NEXT: mov z26.d, z3.d
209 ; CHECK-NEXT: mov z25.d, z2.d
210 ; CHECK-NEXT: mov z24.d, z1.d
212 ; CHECK-NEXT: mov z0.d, z24.d
213 ; CHECK-NEXT: mov z1.d, z25.d
214 ; CHECK-NEXT: mov z2.d, z26.d
215 ; CHECK-NEXT: mov z3.d, z27.d
222 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_single_x4_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {
225 ; CHECK-NEXT: mov z27.d, z4.d
226 ; CHECK-NEXT: mov z26.d, z3.d
227 ; CHECK-NEXT: mov z25.d, z2.d
228 ; CHECK-NEXT: mov z24.d, z1.d
229 ; CHECK-NEXT: smax { z24.d - z27.d }, { z24.d - z27.d }, z5.d
230 ; CHECK-NEXT: mov z0.d, z24.d
231 ; CHECK-NEXT: mov z1.d, z25.d
232 ; CHECK-NEXT: mov z2.d, z26.d
233 ; CHECK-NEXT: mov z3.d, z27.d
235 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
236 @llvm.aarch64.sve.smax.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)
237 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
245 ; CHECK-NEXT: mov z27.d, z4.d
246 ; CHECK-NEXT: mov z26.d, z3.d
247 ; CHECK-NEXT: mov z25.d, z2.d
248 ; CHECK-NEXT: mov z24.d, z1.d
250 ; CHECK-NEXT: mov z0.d, z24.d
251 ; CHECK-NEXT: mov z1.d, z25.d
252 ; CHECK-NEXT: mov z2.d, z26.d
253 ; CHECK-NEXT: mov z3.d, z27.d
263 ; CHECK-NEXT: mov z27.d, z4.d
264 ; CHECK-NEXT: mov z26.d, z3.d
265 ; CHECK-NEXT: mov z25.d, z2.d
266 ; CHECK-NEXT: mov z24.d, z1.d
268 ; CHECK-NEXT: mov z0.d, z24.d
269 ; CHECK-NEXT: mov z1.d, z25.d
270 ; CHECK-NEXT: mov z2.d, z26.d
271 ; CHECK-NEXT: mov z3.d, z27.d
281 ; CHECK-NEXT: mov z27.d, z4.d
282 ; CHECK-NEXT: mov z26.d, z3.d
283 ; CHECK-NEXT: mov z25.d, z2.d
284 ; CHECK-NEXT: mov z24.d, z1.d
286 ; CHECK-NEXT: mov z0.d, z24.d
287 ; CHECK-NEXT: mov z1.d, z25.d
288 ; CHECK-NEXT: mov z2.d, z26.d
289 ; CHECK-NEXT: mov z3.d, z27.d
296 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_single_x4_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {
299 ; CHECK-NEXT: mov z27.d, z4.d
300 ; CHECK-NEXT: mov z26.d, z3.d
301 ; CHECK-NEXT: mov z25.d, z2.d
302 ; CHECK-NEXT: mov z24.d, z1.d
303 ; CHECK-NEXT: umax { z24.d - z27.d }, { z24.d - z27.d }, z5.d
304 ; CHECK-NEXT: mov z0.d, z24.d
305 ; CHECK-NEXT: mov z1.d, z25.d
306 ; CHECK-NEXT: mov z2.d, z26.d
307 ; CHECK-NEXT: mov z3.d, z27.d
309 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
310 @llvm.aarch64.sve.umax.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)
311 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
334 ; CHECK-NEXT: mov z27.d, z4.d
335 ; CHECK-NEXT: mov z26.d, z3.d
336 ; CHECK-NEXT: mov z25.d, z2.d
337 ; CHECK-NEXT: mov z24.d, z1.d
339 ; CHECK-NEXT: mov z0.d, z24.d
340 ; CHECK-NEXT: mov z1.d, z25.d
341 ; CHECK-NEXT: mov z2.d, z26.d
342 ; CHECK-NEXT: mov z3.d, z27.d
352 ; CHECK-NEXT: mov z27.d, z4.d
353 ; CHECK-NEXT: mov z26.d, z3.d
354 ; CHECK-NEXT: mov z25.d, z2.d
355 ; CHECK-NEXT: mov z24.d, z1.d
357 ; CHECK-NEXT: mov z0.d, z24.d
358 ; CHECK-NEXT: mov z1.d, z25.d
359 ; CHECK-NEXT: mov z2.d, z26.d
360 ; CHECK-NEXT: mov z3.d, z27.d
367 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_single_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm) {
370 ; CHECK-NEXT: mov z27.d, z4.d
371 ; CHECK-NEXT: mov z26.d, z3.d
372 ; CHECK-NEXT: mov z25.d, z2.d
373 ; CHECK-NEXT: mov z24.d, z1.d
374 ; CHECK-NEXT: fmax { z24.d - z27.d }, { z24.d - z27.d }, z5.d
375 ; CHECK-NEXT: mov z0.d, z24.d
376 ; CHECK-NEXT: mov z1.d, z25.d
377 ; CHECK-NEXT: mov z2.d, z26.d
378 ; CHECK-NEXT: mov z3.d, z27.d
380 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
381 @llvm.aarch64.sve.fmax.single.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm)
382 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
390 ; CHECK-NEXT: mov z7.d, z4.d
391 ; CHECK-NEXT: mov z5.d, z2.d
392 ; CHECK-NEXT: mov z6.d, z3.d
393 ; CHECK-NEXT: mov z4.d, z1.d
395 ; CHECK-NEXT: mov z0.d, z4.d
396 ; CHECK-NEXT: mov z1.d, z5.d
405 ; CHECK-NEXT: mov z7.d, z4.d
406 ; CHECK-NEXT: mov z5.d, z2.d
407 ; CHECK-NEXT: mov z6.d, z3.d
408 ; CHECK-NEXT: mov z4.d, z1.d
410 ; CHECK-NEXT: mov z0.d, z4.d
411 ; CHECK-NEXT: mov z1.d, z5.d
420 ; CHECK-NEXT: mov z7.d, z4.d
421 ; CHECK-NEXT: mov z5.d, z2.d
422 ; CHECK-NEXT: mov z6.d, z3.d
423 ; CHECK-NEXT: mov z4.d, z1.d
425 ; CHECK-NEXT: mov z0.d, z4.d
426 ; CHECK-NEXT: mov z1.d, z5.d
432 define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_multi_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {
435 ; CHECK-NEXT: mov z7.d, z4.d
436 ; CHECK-NEXT: mov z5.d, z2.d
437 ; CHECK-NEXT: mov z6.d, z3.d
438 ; CHECK-NEXT: mov z4.d, z1.d
439 ; CHECK-NEXT: smax { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
440 ; CHECK-NEXT: mov z0.d, z4.d
441 ; CHECK-NEXT: mov z1.d, z5.d
443 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)
444 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
452 ; CHECK-NEXT: mov z7.d, z4.d
453 ; CHECK-NEXT: mov z5.d, z2.d
454 ; CHECK-NEXT: mov z6.d, z3.d
455 ; CHECK-NEXT: mov z4.d, z1.d
457 ; CHECK-NEXT: mov z0.d, z4.d
458 ; CHECK-NEXT: mov z1.d, z5.d
467 ; CHECK-NEXT: mov z7.d, z4.d
468 ; CHECK-NEXT: mov z5.d, z2.d
469 ; CHECK-NEXT: mov z6.d, z3.d
470 ; CHECK-NEXT: mov z4.d, z1.d
472 ; CHECK-NEXT: mov z0.d, z4.d
473 ; CHECK-NEXT: mov z1.d, z5.d
482 ; CHECK-NEXT: mov z7.d, z4.d
483 ; CHECK-NEXT: mov z5.d, z2.d
484 ; CHECK-NEXT: mov z6.d, z3.d
485 ; CHECK-NEXT: mov z4.d, z1.d
487 ; CHECK-NEXT: mov z0.d, z4.d
488 ; CHECK-NEXT: mov z1.d, z5.d
494 define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_multi_x2_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {
497 ; CHECK-NEXT: mov z7.d, z4.d
498 ; CHECK-NEXT: mov z5.d, z2.d
499 ; CHECK-NEXT: mov z6.d, z3.d
500 ; CHECK-NEXT: mov z4.d, z1.d
501 ; CHECK-NEXT: umax { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
502 ; CHECK-NEXT: mov z0.d, z4.d
503 ; CHECK-NEXT: mov z1.d, z5.d
505 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umax.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)
506 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
529 ; CHECK-NEXT: mov z7.d, z4.d
530 ; CHECK-NEXT: mov z5.d, z2.d
531 ; CHECK-NEXT: mov z6.d, z3.d
532 ; CHECK-NEXT: mov z4.d, z1.d
534 ; CHECK-NEXT: mov z0.d, z4.d
535 ; CHECK-NEXT: mov z1.d, z5.d
544 ; CHECK-NEXT: mov z7.d, z4.d
545 ; CHECK-NEXT: mov z5.d, z2.d
546 ; CHECK-NEXT: mov z6.d, z3.d
547 ; CHECK-NEXT: mov z4.d, z1.d
549 ; CHECK-NEXT: mov z0.d, z4.d
550 ; CHECK-NEXT: mov z1.d, z5.d
556 define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_multi_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {
559 ; CHECK-NEXT: mov z7.d, z4.d
560 ; CHECK-NEXT: mov z5.d, z2.d
561 ; CHECK-NEXT: mov z6.d, z3.d
562 ; CHECK-NEXT: mov z4.d, z1.d
563 ; CHECK-NEXT: fmax { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
564 ; CHECK-NEXT: mov z0.d, z4.d
565 ; CHECK-NEXT: mov z1.d, z5.d
567 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmax.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)
568 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
576 ; CHECK-NEXT: mov z30.d, z7.d
577 ; CHECK-NEXT: mov z27.d, z4.d
579 ; CHECK-NEXT: mov z29.d, z6.d
580 ; CHECK-NEXT: mov z26.d, z3.d
581 ; CHECK-NEXT: mov z28.d, z5.d
582 ; CHECK-NEXT: mov z25.d, z2.d
584 ; CHECK-NEXT: mov z24.d, z1.d
586 ; CHECK-NEXT: mov z0.d, z24.d
587 ; CHECK-NEXT: mov z1.d, z25.d
588 ; CHECK-NEXT: mov z2.d, z26.d
589 ; CHECK-NEXT: mov z3.d, z27.d
601 ; CHECK-NEXT: mov z30.d, z7.d
602 ; CHECK-NEXT: mov z27.d, z4.d
604 ; CHECK-NEXT: mov z29.d, z6.d
605 ; CHECK-NEXT: mov z26.d, z3.d
606 ; CHECK-NEXT: mov z28.d, z5.d
607 ; CHECK-NEXT: mov z25.d, z2.d
609 ; CHECK-NEXT: mov z24.d, z1.d
611 ; CHECK-NEXT: mov z0.d, z24.d
612 ; CHECK-NEXT: mov z1.d, z25.d
613 ; CHECK-NEXT: mov z2.d, z26.d
614 ; CHECK-NEXT: mov z3.d, z27.d
626 ; CHECK-NEXT: mov z30.d, z7.d
627 ; CHECK-NEXT: mov z27.d, z4.d
629 ; CHECK-NEXT: mov z29.d, z6.d
630 ; CHECK-NEXT: mov z26.d, z3.d
631 ; CHECK-NEXT: mov z28.d, z5.d
632 ; CHECK-NEXT: mov z25.d, z2.d
634 ; CHECK-NEXT: mov z24.d, z1.d
636 ; CHECK-NEXT: mov z0.d, z24.d
637 ; CHECK-NEXT: mov z1.d, z25.d
638 ; CHECK-NEXT: mov z2.d, z26.d
639 ; CHECK-NEXT: mov z3.d, z27.d
648 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_multi_x4_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,
651 ; CHECK-NEXT: mov z30.d, z7.d
652 ; CHECK-NEXT: mov z27.d, z4.d
653 ; CHECK-NEXT: ptrue p0.d
654 ; CHECK-NEXT: mov z29.d, z6.d
655 ; CHECK-NEXT: mov z26.d, z3.d
656 ; CHECK-NEXT: mov z28.d, z5.d
657 ; CHECK-NEXT: mov z25.d, z2.d
658 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
659 ; CHECK-NEXT: mov z24.d, z1.d
660 ; CHECK-NEXT: smax { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
661 ; CHECK-NEXT: mov z0.d, z24.d
662 ; CHECK-NEXT: mov z1.d, z25.d
663 ; CHECK-NEXT: mov z2.d, z26.d
664 ; CHECK-NEXT: mov z3.d, z27.d
666 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
667 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
668 @llvm.aarch64.sve.smax.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,
669 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)
670 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
678 ; CHECK-NEXT: mov z30.d, z7.d
679 ; CHECK-NEXT: mov z27.d, z4.d
681 ; CHECK-NEXT: mov z29.d, z6.d
682 ; CHECK-NEXT: mov z26.d, z3.d
683 ; CHECK-NEXT: mov z28.d, z5.d
684 ; CHECK-NEXT: mov z25.d, z2.d
686 ; CHECK-NEXT: mov z24.d, z1.d
688 ; CHECK-NEXT: mov z0.d, z24.d
689 ; CHECK-NEXT: mov z1.d, z25.d
690 ; CHECK-NEXT: mov z2.d, z26.d
691 ; CHECK-NEXT: mov z3.d, z27.d
703 ; CHECK-NEXT: mov z30.d, z7.d
704 ; CHECK-NEXT: mov z27.d, z4.d
706 ; CHECK-NEXT: mov z29.d, z6.d
707 ; CHECK-NEXT: mov z26.d, z3.d
708 ; CHECK-NEXT: mov z28.d, z5.d
709 ; CHECK-NEXT: mov z25.d, z2.d
711 ; CHECK-NEXT: mov z24.d, z1.d
713 ; CHECK-NEXT: mov z0.d, z24.d
714 ; CHECK-NEXT: mov z1.d, z25.d
715 ; CHECK-NEXT: mov z2.d, z26.d
716 ; CHECK-NEXT: mov z3.d, z27.d
728 ; CHECK-NEXT: mov z30.d, z7.d
729 ; CHECK-NEXT: mov z27.d, z4.d
731 ; CHECK-NEXT: mov z29.d, z6.d
732 ; CHECK-NEXT: mov z26.d, z3.d
733 ; CHECK-NEXT: mov z28.d, z5.d
734 ; CHECK-NEXT: mov z25.d, z2.d
736 ; CHECK-NEXT: mov z24.d, z1.d
738 ; CHECK-NEXT: mov z0.d, z24.d
739 ; CHECK-NEXT: mov z1.d, z25.d
740 ; CHECK-NEXT: mov z2.d, z26.d
741 ; CHECK-NEXT: mov z3.d, z27.d
750 define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_max_multi_x4_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,
753 ; CHECK-NEXT: mov z30.d, z7.d
754 ; CHECK-NEXT: mov z27.d, z4.d
755 ; CHECK-NEXT: ptrue p0.d
756 ; CHECK-NEXT: mov z29.d, z6.d
757 ; CHECK-NEXT: mov z26.d, z3.d
758 ; CHECK-NEXT: mov z28.d, z5.d
759 ; CHECK-NEXT: mov z25.d, z2.d
760 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
761 ; CHECK-NEXT: mov z24.d, z1.d
762 ; CHECK-NEXT: umax { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
763 ; CHECK-NEXT: mov z0.d, z24.d
764 ; CHECK-NEXT: mov z1.d, z25.d
765 ; CHECK-NEXT: mov z2.d, z26.d
766 ; CHECK-NEXT: mov z3.d, z27.d
768 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {
769 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
770 @llvm.aarch64.sve.umax.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,
771 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)
772 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
799 ; CHECK-NEXT: mov z30.d, z7.d
800 ; CHECK-NEXT: mov z27.d, z4.d
802 ; CHECK-NEXT: mov z29.d, z6.d
803 ; CHECK-NEXT: mov z26.d, z3.d
804 ; CHECK-NEXT: mov z28.d, z5.d
805 ; CHECK-NEXT: mov z25.d, z2.d
807 ; CHECK-NEXT: mov z24.d, z1.d
809 ; CHECK-NEXT: mov z0.d, z24.d
810 ; CHECK-NEXT: mov z1.d, z25.d
811 ; CHECK-NEXT: mov z2.d, z26.d
812 ; CHECK-NEXT: mov z3.d, z27.d
824 ; CHECK-NEXT: mov z30.d, z7.d
825 ; CHECK-NEXT: mov z27.d, z4.d
827 ; CHECK-NEXT: mov z29.d, z6.d
828 ; CHECK-NEXT: mov z26.d, z3.d
829 ; CHECK-NEXT: mov z28.d, z5.d
830 ; CHECK-NEXT: mov z25.d, z2.d
832 ; CHECK-NEXT: mov z24.d, z1.d
834 ; CHECK-NEXT: mov z0.d, z24.d
835 ; CHECK-NEXT: mov z1.d, z25.d
836 ; CHECK-NEXT: mov z2.d, z26.d
837 ; CHECK-NEXT: mov z3.d, z27.d
846 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_multi_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,
849 ; CHECK-NEXT: mov z30.d, z7.d
850 ; CHECK-NEXT: mov z27.d, z4.d
851 ; CHECK-NEXT: ptrue p0.d
852 ; CHECK-NEXT: mov z29.d, z6.d
853 ; CHECK-NEXT: mov z26.d, z3.d
854 ; CHECK-NEXT: mov z28.d, z5.d
855 ; CHECK-NEXT: mov z25.d, z2.d
856 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
857 ; CHECK-NEXT: mov z24.d, z1.d
858 ; CHECK-NEXT: fmax { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
859 ; CHECK-NEXT: mov z0.d, z24.d
860 ; CHECK-NEXT: mov z1.d, z25.d
861 ; CHECK-NEXT: mov z2.d, z26.d
862 ; CHECK-NEXT: mov z3.d, z27.d
864 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {
865 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
866 @llvm.aarch64.sve.fmax.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,
867 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)
868 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
889 ; CHECK-NEXT: mov z5.d, z2.d
890 ; CHECK-NEXT: mov z4.d, z1.d
892 ; CHECK-NEXT: mov z0.d, z4.d
893 ; CHECK-NEXT: mov z1.d, z5.d
902 ; CHECK-NEXT: mov z5.d, z2.d
903 ; CHECK-NEXT: mov z4.d, z1.d
905 ; CHECK-NEXT: mov z0.d, z4.d
906 ; CHECK-NEXT: mov z1.d, z5.d
912 define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_maxnm_single_x2_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm) {
915 ; CHECK-NEXT: mov z5.d, z2.d
916 ; CHECK-NEXT: mov z4.d, z1.d
917 ; CHECK-NEXT: fmaxnm { z4.d, z5.d }, { z4.d, z5.d }, z3.d
918 ; CHECK-NEXT: mov z0.d, z4.d
919 ; CHECK-NEXT: mov z1.d, z5.d
921 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm)
922 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
945 ; CHECK-NEXT: mov z27.d, z4.d
946 ; CHECK-NEXT: mov z26.d, z3.d
947 ; CHECK-NEXT: mov z25.d, z2.d
948 ; CHECK-NEXT: mov z24.d, z1.d
950 ; CHECK-NEXT: mov z0.d, z24.d
951 ; CHECK-NEXT: mov z1.d, z25.d
952 ; CHECK-NEXT: mov z2.d, z26.d
953 ; CHECK-NEXT: mov z3.d, z27.d
963 ; CHECK-NEXT: mov z27.d, z4.d
964 ; CHECK-NEXT: mov z26.d, z3.d
965 ; CHECK-NEXT: mov z25.d, z2.d
966 ; CHECK-NEXT: mov z24.d, z1.d
968 ; CHECK-NEXT: mov z0.d, z24.d
969 ; CHECK-NEXT: mov z1.d, z25.d
970 ; CHECK-NEXT: mov z2.d, z26.d
971 ; CHECK-NEXT: mov z3.d, z27.d
978 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_maxnm_single_x4_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm) {
981 ; CHECK-NEXT: mov z27.d, z4.d
982 ; CHECK-NEXT: mov z26.d, z3.d
983 ; CHECK-NEXT: mov z25.d, z2.d
984 ; CHECK-NEXT: mov z24.d, z1.d
985 ; CHECK-NEXT: fmaxnm { z24.d - z27.d }, { z24.d - z27.d }, z5.d
986 ; CHECK-NEXT: mov z0.d, z24.d
987 ; CHECK-NEXT: mov z1.d, z25.d
988 ; CHECK-NEXT: mov z2.d, z26.d
989 ; CHECK-NEXT: mov z3.d, z27.d
991 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
992 @llvm.aarch64.sve.fmaxnm.single.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm)
993 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
1016 ; CHECK-NEXT: mov z7.d, z4.d
1017 ; CHECK-NEXT: mov z5.d, z2.d
1018 ; CHECK-NEXT: mov z6.d, z3.d
1019 ; CHECK-NEXT: mov z4.d, z1.d
1021 ; CHECK-NEXT: mov z0.d, z4.d
1022 ; CHECK-NEXT: mov z1.d, z5.d
1031 ; CHECK-NEXT: mov z7.d, z4.d
1032 ; CHECK-NEXT: mov z5.d, z2.d
1033 ; CHECK-NEXT: mov z6.d, z3.d
1034 ; CHECK-NEXT: mov z4.d, z1.d
1036 ; CHECK-NEXT: mov z0.d, z4.d
1037 ; CHECK-NEXT: mov z1.d, z5.d
1043 define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_maxnm_x2_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {
1046 ; CHECK-NEXT: mov z7.d, z4.d
1047 ; CHECK-NEXT: mov z5.d, z2.d
1048 ; CHECK-NEXT: mov z6.d, z3.d
1049 ; CHECK-NEXT: mov z4.d, z1.d
1050 ; CHECK-NEXT: fmaxnm { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
1051 ; CHECK-NEXT: mov z0.d, z4.d
1052 ; CHECK-NEXT: mov z1.d, z5.d
1054 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)
1055 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res
1082 ; CHECK-NEXT: mov z30.d, z7.d
1083 ; CHECK-NEXT: mov z27.d, z4.d
1085 ; CHECK-NEXT: mov z29.d, z6.d
1086 ; CHECK-NEXT: mov z26.d, z3.d
1087 ; CHECK-NEXT: mov z28.d, z5.d
1088 ; CHECK-NEXT: mov z25.d, z2.d
1090 ; CHECK-NEXT: mov z24.d, z1.d
1092 ; CHECK-NEXT: mov z0.d, z24.d
1093 ; CHECK-NEXT: mov z1.d, z25.d
1094 ; CHECK-NEXT: mov z2.d, z26.d
1095 ; CHECK-NEXT: mov z3.d, z27.d
1106 ; CHECK-NEXT: mov z30.d, z7.d
1107 ; CHECK-NEXT: mov z27.d, z4.d
1109 ; CHECK-NEXT: mov z29.d, z6.d
1110 ; CHECK-NEXT: mov z26.d, z3.d
1111 ; CHECK-NEXT: mov z28.d, z5.d
1112 ; CHECK-NEXT: mov z25.d, z2.d
1114 ; CHECK-NEXT: mov z24.d, z1.d
1116 ; CHECK-NEXT: mov z0.d, z24.d
1117 ; CHECK-NEXT: mov z1.d, z25.d
1118 ; CHECK-NEXT: mov z2.d, z26.d
1119 ; CHECK-NEXT: mov z3.d, z27.d
1127 define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_maxnm_x4_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {
1130 ; CHECK-NEXT: mov z30.d, z7.d
1131 ; CHECK-NEXT: mov z27.d, z4.d
1132 ; CHECK-NEXT: ptrue p0.d
1133 ; CHECK-NEXT: mov z29.d, z6.d
1134 ; CHECK-NEXT: mov z26.d, z3.d
1135 ; CHECK-NEXT: mov z28.d, z5.d
1136 ; CHECK-NEXT: mov z25.d, z2.d
1137 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
1138 ; CHECK-NEXT: mov z24.d, z1.d
1139 ; CHECK-NEXT: fmaxnm { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
1140 ; CHECK-NEXT: mov z0.d, z24.d
1141 ; CHECK-NEXT: mov z1.d, z25.d
1142 ; CHECK-NEXT: mov z2.d, z26.d
1143 ; CHECK-NEXT: mov z3.d, z27.d
1145 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
1146 @llvm.aarch64.sve.fmaxnm.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,
1147 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)
1148 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res
1154 declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1159 declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umax.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1163 declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmax.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1168 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1173 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umax.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1179 declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
1180 @llvm.aarch64.sve.fmax.single.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1185 declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smax.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1190 declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umax.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1194 declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmax.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1202 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
1203 @llvm.aarch64.sve.smax.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1211 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
1212 @llvm.aarch64.sve.umax.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)
1218 declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
1219 @llvm.aarch64.sve.fmax.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1223 declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1229 declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
1230 @llvm.aarch64.sve.fmaxnm.single.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1234 declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmaxnm.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)
1240 declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }
1241 @llvm.aarch64.sve.fmaxnm.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)