Lines Matching +full:2 +full:d
9 ; CHECK-NEXT: mov z5.d, z2.d
10 ; CHECK-NEXT: mov z4.d, z1.d
12 ; CHECK-NEXT: mov z0.d, z4.d
13 ; CHECK-NEXT: mov z1.d, z5.d
22 ; CHECK-NEXT: mov z5.d, z2.d
23 ; CHECK-NEXT: mov z4.d, z1.d
25 ; CHECK-NEXT: mov z0.d, z4.d
26 ; CHECK-NEXT: mov z1.d, z5.d
35 ; CHECK-NEXT: mov z5.d, z2.d
36 ; CHECK-NEXT: mov z4.d, z1.d
38 ; CHECK-NEXT: mov z0.d, z4.d
39 ; CHECK-NEXT: mov z1.d, z5.d
45 …2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_single_x2_s64(<vscale x 2 x i64> %unused…
48 ; CHECK-NEXT: mov z5.d, z2.d
49 ; CHECK-NEXT: mov z4.d, z1.d
50 ; CHECK-NEXT: sqdmulh { z4.d, z5.d }, { z4.d, z5.d }, z3.d
51 ; CHECK-NEXT: mov z0.d, z4.d
52 ; CHECK-NEXT: mov z1.d, z5.d
54 …ale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i…
55 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
63 ; CHECK-NEXT: mov z27.d, z4.d
64 ; CHECK-NEXT: mov z26.d, z3.d
65 ; CHECK-NEXT: mov z25.d, z2.d
66 ; CHECK-NEXT: mov z24.d, z1.d
68 ; CHECK-NEXT: mov z0.d, z24.d
69 ; CHECK-NEXT: mov z1.d, z25.d
70 ; CHECK-NEXT: mov z2.d, z26.d
71 ; CHECK-NEXT: mov z3.d, z27.d
81 ; CHECK-NEXT: mov z27.d, z4.d
82 ; CHECK-NEXT: mov z26.d, z3.d
83 ; CHECK-NEXT: mov z25.d, z2.d
84 ; CHECK-NEXT: mov z24.d, z1.d
86 ; CHECK-NEXT: mov z0.d, z24.d
87 ; CHECK-NEXT: mov z1.d, z25.d
88 ; CHECK-NEXT: mov z2.d, z26.d
89 ; CHECK-NEXT: mov z3.d, z27.d
99 ; CHECK-NEXT: mov z27.d, z4.d
100 ; CHECK-NEXT: mov z26.d, z3.d
101 ; CHECK-NEXT: mov z25.d, z2.d
102 ; CHECK-NEXT: mov z24.d, z1.d
104 ; CHECK-NEXT: mov z0.d, z24.d
105 ; CHECK-NEXT: mov z1.d, z25.d
106 ; CHECK-NEXT: mov z2.d, z26.d
107 ; CHECK-NEXT: mov z3.d, z27.d
114 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_…
117 ; CHECK-NEXT: mov z27.d, z4.d
118 ; CHECK-NEXT: mov z26.d, z3.d
119 ; CHECK-NEXT: mov z25.d, z2.d
120 ; CHECK-NEXT: mov z24.d, z1.d
121 ; CHECK-NEXT: sqdmulh { z24.d - z27.d }, { z24.d - z27.d }, z5.d
122 ; CHECK-NEXT: mov z0.d, z24.d
123 ; CHECK-NEXT: mov z1.d, z25.d
124 ; CHECK-NEXT: mov z2.d, z26.d
125 ; CHECK-NEXT: mov z3.d, z27.d
127 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
128 ….vgx4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscal…
129 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
137 ; CHECK-NEXT: mov z7.d, z4.d
138 ; CHECK-NEXT: mov z5.d, z2.d
139 ; CHECK-NEXT: mov z6.d, z3.d
140 ; CHECK-NEXT: mov z4.d, z1.d
142 ; CHECK-NEXT: mov z0.d, z4.d
143 ; CHECK-NEXT: mov z1.d, z5.d
152 ; CHECK-NEXT: mov z7.d, z4.d
153 ; CHECK-NEXT: mov z5.d, z2.d
154 ; CHECK-NEXT: mov z6.d, z3.d
155 ; CHECK-NEXT: mov z4.d, z1.d
157 ; CHECK-NEXT: mov z0.d, z4.d
158 ; CHECK-NEXT: mov z1.d, z5.d
167 ; CHECK-NEXT: mov z7.d, z4.d
168 ; CHECK-NEXT: mov z5.d, z2.d
169 ; CHECK-NEXT: mov z6.d, z3.d
170 ; CHECK-NEXT: mov z4.d, z1.d
172 ; CHECK-NEXT: mov z0.d, z4.d
173 ; CHECK-NEXT: mov z1.d, z5.d
179 …2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_multi_x2_s64(<vscale x 2 x i64> %unused,…
182 ; CHECK-NEXT: mov z7.d, z4.d
183 ; CHECK-NEXT: mov z5.d, z2.d
184 ; CHECK-NEXT: mov z6.d, z3.d
185 ; CHECK-NEXT: mov z4.d, z1.d
186 ; CHECK-NEXT: sqdmulh { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }
187 ; CHECK-NEXT: mov z0.d, z4.d
188 ; CHECK-NEXT: mov z1.d, z5.d
190 …2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv2i64(<vscale x 2 x i64> %zdn1, <v…
191 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res
199 ; CHECK-NEXT: mov z30.d, z7.d
200 ; CHECK-NEXT: mov z27.d, z4.d
202 ; CHECK-NEXT: mov z29.d, z6.d
203 ; CHECK-NEXT: mov z26.d, z3.d
204 ; CHECK-NEXT: mov z28.d, z5.d
205 ; CHECK-NEXT: mov z25.d, z2.d
207 ; CHECK-NEXT: mov z24.d, z1.d
209 ; CHECK-NEXT: mov z0.d, z24.d
210 ; CHECK-NEXT: mov z1.d, z25.d
211 ; CHECK-NEXT: mov z2.d, z26.d
212 ; CHECK-NEXT: mov z3.d, z27.d
224 ; CHECK-NEXT: mov z30.d, z7.d
225 ; CHECK-NEXT: mov z27.d, z4.d
227 ; CHECK-NEXT: mov z29.d, z6.d
228 ; CHECK-NEXT: mov z26.d, z3.d
229 ; CHECK-NEXT: mov z28.d, z5.d
230 ; CHECK-NEXT: mov z25.d, z2.d
232 ; CHECK-NEXT: mov z24.d, z1.d
234 ; CHECK-NEXT: mov z0.d, z24.d
235 ; CHECK-NEXT: mov z1.d, z25.d
236 ; CHECK-NEXT: mov z2.d, z26.d
237 ; CHECK-NEXT: mov z3.d, z27.d
249 ; CHECK-NEXT: mov z30.d, z7.d
250 ; CHECK-NEXT: mov z27.d, z4.d
252 ; CHECK-NEXT: mov z29.d, z6.d
253 ; CHECK-NEXT: mov z26.d, z3.d
254 ; CHECK-NEXT: mov z28.d, z5.d
255 ; CHECK-NEXT: mov z25.d, z2.d
257 ; CHECK-NEXT: mov z24.d, z1.d
259 ; CHECK-NEXT: mov z0.d, z24.d
260 ; CHECK-NEXT: mov z1.d, z25.d
261 ; CHECK-NEXT: mov z2.d, z26.d
262 ; CHECK-NEXT: mov z3.d, z27.d
271 …2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_…
274 ; CHECK-NEXT: mov z30.d, z7.d
275 ; CHECK-NEXT: mov z27.d, z4.d
276 ; CHECK-NEXT: ptrue p0.d
277 ; CHECK-NEXT: mov z29.d, z6.d
278 ; CHECK-NEXT: mov z26.d, z3.d
279 ; CHECK-NEXT: mov z28.d, z5.d
280 ; CHECK-NEXT: mov z25.d, z2.d
281 ; CHECK-NEXT: ld1d { z31.d }, p0/z, [x0]
282 ; CHECK-NEXT: mov z24.d, z1.d
283 ; CHECK-NEXT: sqdmulh { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }
284 ; CHECK-NEXT: mov z0.d, z24.d
285 ; CHECK-NEXT: mov z1.d, z25.d
286 ; CHECK-NEXT: mov z2.d, z26.d
287 ; CHECK-NEXT: mov z3.d, z27.d
289 …<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4…
290 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
291 …4.sve.sqdmulh.vgx4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> …
292 …<vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)
293 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res
299 …{ <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x…
307 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
308 …dmulh.single.vgx4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 …
313 …ale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv2i64(<vscale x 2 x i64>, <v…
324 declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }
325 …vm.aarch64.sve.sqdmulh.vgx4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <v…
326 … <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)