xref: /llvm-project/llvm/test/CodeGen/AArch64/sve2-eor3.ll (revision d39b4ce3ce8a3c256e01bdec2b140777a332a633) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=aarch64 -mattr=+sve < %s -o - | FileCheck --check-prefix=SVE %s
3; RUN: llc -mtriple=aarch64 -mattr=+sve2 < %s -o - | FileCheck --check-prefix=SVE2 %s
4
5define <vscale x 16 x i8> @eor3_nxv16i8_left(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
6; SVE-LABEL: eor3_nxv16i8_left:
7; SVE:       // %bb.0:
8; SVE-NEXT:    eor z0.d, z0.d, z1.d
9; SVE-NEXT:    eor z0.d, z0.d, z2.d
10; SVE-NEXT:    ret
11;
12; SVE2-LABEL: eor3_nxv16i8_left:
13; SVE2:       // %bb.0:
14; SVE2-NEXT:    eor3 z0.d, z0.d, z1.d, z2.d
15; SVE2-NEXT:    ret
16  %4 = xor <vscale x 16 x i8> %0, %1
17  %5 = xor <vscale x 16 x i8> %4, %2
18  ret <vscale x 16 x i8> %5
19}
20
21define <vscale x 16 x i8> @eor3_nxv16i8_right(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, <vscale x 16 x i8> %2) {
22; SVE-LABEL: eor3_nxv16i8_right:
23; SVE:       // %bb.0:
24; SVE-NEXT:    eor z0.d, z0.d, z1.d
25; SVE-NEXT:    eor z0.d, z2.d, z0.d
26; SVE-NEXT:    ret
27;
28; SVE2-LABEL: eor3_nxv16i8_right:
29; SVE2:       // %bb.0:
30; SVE2-NEXT:    eor3 z2.d, z2.d, z0.d, z1.d
31; SVE2-NEXT:    mov z0.d, z2.d
32; SVE2-NEXT:    ret
33  %4 = xor <vscale x 16 x i8> %0, %1
34  %5 = xor <vscale x 16 x i8> %2, %4
35  ret <vscale x 16 x i8> %5
36}
37
38define <vscale x 8 x i16> @eor3_nxv8i16_left(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {
39; SVE-LABEL: eor3_nxv8i16_left:
40; SVE:       // %bb.0:
41; SVE-NEXT:    eor z0.d, z0.d, z1.d
42; SVE-NEXT:    eor z0.d, z0.d, z2.d
43; SVE-NEXT:    ret
44;
45; SVE2-LABEL: eor3_nxv8i16_left:
46; SVE2:       // %bb.0:
47; SVE2-NEXT:    eor3 z0.d, z0.d, z1.d, z2.d
48; SVE2-NEXT:    ret
49  %4 = xor <vscale x 8 x i16> %0, %1
50  %5 = xor <vscale x 8 x i16> %4, %2
51  ret <vscale x 8 x i16> %5
52}
53
54define <vscale x 8 x i16> @eor3_nxv8i16_right(<vscale x 8 x i16> %0, <vscale x 8 x i16> %1, <vscale x 8 x i16> %2) {
55; SVE-LABEL: eor3_nxv8i16_right:
56; SVE:       // %bb.0:
57; SVE-NEXT:    eor z0.d, z0.d, z1.d
58; SVE-NEXT:    eor z0.d, z2.d, z0.d
59; SVE-NEXT:    ret
60;
61; SVE2-LABEL: eor3_nxv8i16_right:
62; SVE2:       // %bb.0:
63; SVE2-NEXT:    eor3 z2.d, z2.d, z0.d, z1.d
64; SVE2-NEXT:    mov z0.d, z2.d
65; SVE2-NEXT:    ret
66  %4 = xor <vscale x 8 x i16> %0, %1
67  %5 = xor <vscale x 8 x i16> %2, %4
68  ret <vscale x 8 x i16> %5
69}
70
71define <vscale x 4 x i32> @eor3_nxv4i32_left(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {
72; SVE-LABEL: eor3_nxv4i32_left:
73; SVE:       // %bb.0:
74; SVE-NEXT:    eor z0.d, z0.d, z1.d
75; SVE-NEXT:    eor z0.d, z0.d, z2.d
76; SVE-NEXT:    ret
77;
78; SVE2-LABEL: eor3_nxv4i32_left:
79; SVE2:       // %bb.0:
80; SVE2-NEXT:    eor3 z0.d, z0.d, z1.d, z2.d
81; SVE2-NEXT:    ret
82  %4 = xor <vscale x 4 x i32> %0, %1
83  %5 = xor <vscale x 4 x i32> %4, %2
84  ret <vscale x 4 x i32> %5
85}
86
87define <vscale x 4 x i32> @eor3_nxv4i32_right(<vscale x 4 x i32> %0, <vscale x 4 x i32> %1, <vscale x 4 x i32> %2) {
88; SVE-LABEL: eor3_nxv4i32_right:
89; SVE:       // %bb.0:
90; SVE-NEXT:    eor z0.d, z0.d, z1.d
91; SVE-NEXT:    eor z0.d, z2.d, z0.d
92; SVE-NEXT:    ret
93;
94; SVE2-LABEL: eor3_nxv4i32_right:
95; SVE2:       // %bb.0:
96; SVE2-NEXT:    eor3 z2.d, z2.d, z0.d, z1.d
97; SVE2-NEXT:    mov z0.d, z2.d
98; SVE2-NEXT:    ret
99  %4 = xor <vscale x 4 x i32> %0, %1
100  %5 = xor <vscale x 4 x i32> %2, %4
101  ret <vscale x 4 x i32> %5
102}
103
104define <vscale x 2 x i64> @eor3_nxv2i64_left(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2) {
105; SVE-LABEL: eor3_nxv2i64_left:
106; SVE:       // %bb.0:
107; SVE-NEXT:    eor z0.d, z0.d, z1.d
108; SVE-NEXT:    eor z0.d, z0.d, z2.d
109; SVE-NEXT:    ret
110;
111; SVE2-LABEL: eor3_nxv2i64_left:
112; SVE2:       // %bb.0:
113; SVE2-NEXT:    eor3 z0.d, z0.d, z1.d, z2.d
114; SVE2-NEXT:    ret
115  %4 = xor <vscale x 2 x i64> %0, %1
116  %5 = xor <vscale x 2 x i64> %4, %2
117  ret <vscale x 2 x i64> %5
118}
119
120define <vscale x 2 x i64> @eor3_nxv2i64_right(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1, <vscale x 2 x i64> %2) {
121; SVE-LABEL: eor3_nxv2i64_right:
122; SVE:       // %bb.0:
123; SVE-NEXT:    eor z0.d, z0.d, z1.d
124; SVE-NEXT:    eor z0.d, z2.d, z0.d
125; SVE-NEXT:    ret
126;
127; SVE2-LABEL: eor3_nxv2i64_right:
128; SVE2:       // %bb.0:
129; SVE2-NEXT:    eor3 z2.d, z2.d, z0.d, z1.d
130; SVE2-NEXT:    mov z0.d, z2.d
131; SVE2-NEXT:    ret
132  %4 = xor <vscale x 2 x i64> %0, %1
133  %5 = xor <vscale x 2 x i64> %2, %4
134  ret <vscale x 2 x i64> %5
135}
136
137define <vscale x 2 x i64> @eor3_vnot(<vscale x 2 x i64> %0, <vscale x 2 x i64> %1) {
138; SVE-LABEL: eor3_vnot:
139; SVE:       // %bb.0:
140; SVE-NEXT:    eor z0.d, z0.d, z1.d
141; SVE-NEXT:    ret
142;
143; SVE2-LABEL: eor3_vnot:
144; SVE2:       // %bb.0:
145; SVE2-NEXT:    eor z0.d, z0.d, z1.d
146; SVE2-NEXT:    ret
147  %3 = xor <vscale x 2 x i64> %0, zeroinitializer
148  %4 = xor <vscale x 2 x i64> %3, %1
149  ret <vscale x 2 x i64> %4
150}
151
152