| /llvm-project/llvm/lib/Target/X86/MCTargetDesc/ |
| H A D | X86InstComments.cpp | 25 CASE_SSE_INS_COMMON(Inst,src) global() argument
28 CASE_AVX_INS_COMMON(Inst,Suffix,src) global() argument
31 CASE_MASK_INS_COMMON(Inst,Suffix,src) global() argument
34 CASE_MASKZ_INS_COMMON(Inst,Suffix,src) global() argument
37 CASE_AVX512_INS_COMMON(Inst,Suffix,src) global() argument
42 CASE_MOVDUP(Inst,src) global() argument
50 CASE_MASK_MOVDUP(Inst,src) global() argument
55 CASE_MASKZ_MOVDUP(Inst,src) global() argument
60 CASE_PMOVZX(Inst,src) global() argument
68 CASE_UNPCK(Inst,src) global() argument
76 CASE_MASK_UNPCK(Inst,src) global() argument
81 CASE_MASKZ_UNPCK(Inst,src) global() argument
86 CASE_SHUF(Inst,suf) global() argument
94 CASE_MASK_SHUF(Inst,src) global() argument
99 CASE_MASKZ_SHUF(Inst,src) global() argument
104 CASE_VPERMILPI(Inst,src) global() argument
111 CASE_MASK_VPERMILPI(Inst,src) global() argument
116 CASE_MASKZ_VPERMILPI(Inst,src) global() argument
121 CASE_VPERM(Inst,src) global() argument
126 CASE_MASK_VPERM(Inst,src) global() argument
130 CASE_MASKZ_VPERM(Inst,src) global() argument
134 CASE_VSHUF(Inst,src) global() argument
140 CASE_MASK_VSHUF(Inst,src) global() argument
146 CASE_MASKZ_VSHUF(Inst,src) global() argument
152 CASE_AVX512_FMA(Inst,suf) global() argument
157 CASE_FMA(Inst,suf) global() argument
162 CASE_FMA_PACKED_REG(Inst) global() argument
166 CASE_FMA_PACKED_MEM(Inst) global() argument
172 CASE_FMA_SCALAR_REG(Inst) global() argument
182 CASE_FMA_SCALAR_MEM(Inst) global() argument
192 CASE_FMA4(Inst,suf) global() argument
196 CASE_FMA4_PACKED_RR(Inst) global() argument
200 CASE_FMA4_PACKED_RM(Inst) global() argument
204 CASE_FMA4_PACKED_MR(Inst) global() argument
208 CASE_FMA4_SCALAR_RR(Inst) global() argument
214 CASE_FMA4_SCALAR_RM(Inst) global() argument
220 CASE_FMA4_SCALAR_MR(Inst) global() argument
[all...] |
| /llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchMatInt.h | 17 struct Inst { struct
20 InstInst Inst() argument
|
| /llvm-project/llvm/lib/Target/PowerPC/Disassembler/ |
| H A D | PPCDisassembler.cpp | 65 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm, in decodeCondBrTarget()
72 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm, in decodeDirectBrTarget()
84 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, in decodeRegisterClass()
92 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRRCRegisterClass()
98 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeCRBITRCRegisterClass()
104 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeF4RCRegisterClass()
110 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeF8RCRegisterClass()
116 static DecodeStatus DecodeFpRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFpRCRegisterClass()
124 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeVFRCRegisterClass()
130 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeVRRCRegisterClass()
[all …]
|
| /llvm-project/llvm/lib/Target/SystemZ/Disassembler/ |
| H A D | SystemZDisassembler.cpp | 82 decodeRegisterClass(MCInst & Inst,uint64_t RegNo,const unsigned * Regs,unsigned Size,bool IsAddr=false) decodeRegisterClass() argument
97 DecodeGR32BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGR32BitRegisterClass() argument
103 DecodeGRH32BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGRH32BitRegisterClass() argument
109 DecodeGR64BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGR64BitRegisterClass() argument
115 DecodeGR128BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGR128BitRegisterClass() argument
122 DecodeADDR32BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeADDR32BitRegisterClass() argument
128 DecodeADDR64BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeADDR64BitRegisterClass() argument
133 DecodeFP32BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFP32BitRegisterClass() argument
139 DecodeFP64BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFP64BitRegisterClass() argument
145 DecodeFP128BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFP128BitRegisterClass() argument
151 DecodeVR32BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVR32BitRegisterClass() argument
157 DecodeVR64BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVR64BitRegisterClass() argument
163 DecodeVR128BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVR128BitRegisterClass() argument
169 DecodeAR32BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeAR32BitRegisterClass() argument
175 DecodeCR64BitRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCR64BitRegisterClass() argument
182 decodeUImmOperand(MCInst & Inst,uint64_t Imm) decodeUImmOperand() argument
190 decodeSImmOperand(MCInst & Inst,uint64_t Imm) decodeSImmOperand() argument
197 decodeU1ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU1ImmOperand() argument
203 decodeU2ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU2ImmOperand() argument
209 decodeU3ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU3ImmOperand() argument
215 decodeU4ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU4ImmOperand() argument
221 decodeU8ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU8ImmOperand() argument
227 decodeU12ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU12ImmOperand() argument
233 decodeU16ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU16ImmOperand() argument
239 decodeU32ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeU32ImmOperand() argument
245 decodeS8ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS8ImmOperand() argument
251 decodeS16ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS16ImmOperand() argument
257 decodeS20ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS20ImmOperand() argument
263 decodeS32ImmOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeS32ImmOperand() argument
270 decodeLenOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodeLenOperand() argument
280 decodePCDBLOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,bool isBranch,const MCDisassembler * Decoder) decodePCDBLOperand() argument
293 decodePC12DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC12DBLBranchOperand() argument
299 decodePC16DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC16DBLBranchOperand() argument
305 decodePC24DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC24DBLBranchOperand() argument
311 decodePC32DBLBranchOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC32DBLBranchOperand() argument
317 decodePC32DBLOperand(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) decodePC32DBLOperand() argument
354 uint64_t Inst = 0; getInstruction() local
[all...] |
| /llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
| H A D | AArch64Disassembler.cpp | 429 DecodeFPR128RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR128RegisterClass() argument
442 DecodeFPR128_loRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR128_loRegisterClass() argument
450 DecodeFPR128_0to7RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR128_0to7RegisterClass() argument
457 DecodeFPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR64RegisterClass() argument
469 DecodeFPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR32RegisterClass() argument
481 DecodeFPR16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR16RegisterClass() argument
493 DecodeFPR8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeFPR8RegisterClass() argument
506 DecodeGPR64commonRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeGPR64commonRegisterClass() argument
518 DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeGPR64RegisterClass() argument
531 DecodeGPR64x8ClassRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPR64x8ClassRegisterClass() argument
545 DecodeGPR64spRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeGPR64spRegisterClass() argument
557 DecodeMatrixIndexGPR32_8_11RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const void * Decoder) DecodeMatrixIndexGPR32_8_11RegisterClass() argument
570 DecodeMatrixIndexGPR32_12_15RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeMatrixIndexGPR32_12_15RegisterClass() argument
583 DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeGPR32RegisterClass() argument
595 DecodeGPR32spRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeGPR32spRegisterClass() argument
607 DecodeZPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeZPRRegisterClass() argument
619 DecodeZPR_4bRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeZPR_4bRegisterClass() argument
627 DecodeZPR_3bRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeZPR_3bRegisterClass() argument
635 DecodeZPR2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeZPR2RegisterClass() argument
646 DecodeZPR3RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeZPR3RegisterClass() argument
657 DecodeZPR4RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeZPR4RegisterClass() argument
668 DecodeZPR2Mul2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder) DecodeZPR2Mul2RegisterClass() argument
679 DecodeZPR4Mul4RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder) DecodeZPR4Mul4RegisterClass() argument
690 DecodeZPR2StridedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder) DecodeZPR2StridedRegisterClass() argument
702 DecodeZPR4StridedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder) DecodeZPR4StridedRegisterClass() argument
715 DecodeMatrixTileListRegisterClass(MCInst & Inst,unsigned RegMask,uint64_t Address,const MCDisassembler * Decoder) DecodeMatrixTileListRegisterClass() argument
736 DecodeMatrixTile(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMatrixTile() argument
747 DecodePPRorPNRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodePPRorPNRRegisterClass() argument
759 DecodePPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodePPRRegisterClass() argument
771 DecodePNRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodePNRRegisterClass() argument
783 DecodePPR_3bRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodePPR_3bRegisterClass() argument
794 DecodePNR_p8to15RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodePNR_p8to15RegisterClass() argument
803 DecodePPR2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder) DecodePPR2RegisterClass() argument
815 DecodePPR2Mul2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const void * Decoder) DecodePPR2Mul2RegisterClass() argument
826 DecodeQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeQQRegisterClass() argument
837 DecodeQQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeQQQRegisterClass() argument
848 DecodeQQQQRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeQQQQRegisterClass() argument
859 DecodeDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeDDRegisterClass() argument
870 DecodeDDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeDDDRegisterClass() argument
881 DecodeDDDDRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeDDDDRegisterClass() argument
892 DecodeFixedPointScaleImm32(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeFixedPointScaleImm32() argument
901 DecodeFixedPointScaleImm64(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeFixedPointScaleImm64() argument
908 DecodePCRelLabel16(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodePCRelLabel16() argument
923 DecodePCRelLabel19(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodePCRelLabel19() argument
938 DecodeMemExtend(MCInst & Inst,unsigned Imm,uint64_t Address,const MCDisassembler * Decoder) DecodeMemExtend() argument
946 DecodeMRSSystemRegister(MCInst & Inst,unsigned Imm,uint64_t Address,const MCDisassembler * Decoder) DecodeMRSSystemRegister() argument
956 DecodeMSRSystemRegister(MCInst & Inst,unsigned Imm,uint64_t Address,const MCDisassembler * Decoder) DecodeMSRSystemRegister() argument
964 DecodeFMOVLaneInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMOVLaneInstruction() argument
987 DecodeVecShiftRImm(MCInst & Inst,unsigned Imm,unsigned Add) DecodeVecShiftRImm() argument
993 DecodeVecShiftLImm(MCInst & Inst,unsigned Imm,unsigned Add) DecodeVecShiftLImm() argument
999 DecodeVecShiftR64Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR64Imm() argument
1005 DecodeVecShiftR64ImmNarrow(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR64ImmNarrow() argument
1011 DecodeVecShiftR32Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR32Imm() argument
1017 DecodeVecShiftR32ImmNarrow(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR32ImmNarrow() argument
1023 DecodeVecShiftR16Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR16Imm() argument
1029 DecodeVecShiftR16ImmNarrow(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR16ImmNarrow() argument
1035 DecodeVecShiftR8Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftR8Imm() argument
1041 DecodeVecShiftL64Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftL64Imm() argument
1047 DecodeVecShiftL32Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftL32Imm() argument
1053 DecodeVecShiftL16Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftL16Imm() argument
1059 DecodeVecShiftL8Imm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeVecShiftL8Imm() argument
1066 DecodeThreeAddrSRegInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeThreeAddrSRegInstruction() argument
1127 DecodeMoveImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeMoveImmInstruction() argument
1161 DecodeUnsignedLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeUnsignedLdStInstruction() argument
1219 DecodeSignedLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeSignedLdStInstruction() argument
1418 DecodeExclusiveLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeExclusiveLdStInstruction() argument
1500 DecodePairLdStInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodePairLdStInstruction() argument
1634 DecodeAuthLoadInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeAuthLoadInstruction() argument
1667 DecodeAddSubERegInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeAddSubERegInstruction() argument
1724 DecodeLogicalImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeLogicalImmInstruction() argument
1755 DecodeModImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeModImmInstruction() argument
1794 DecodeModImmTiedInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeModImmTiedInstruction() argument
1812 DecodeAdrInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeAdrInstruction() argument
1830 DecodeAddSubImmShift(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeAddSubImmShift() argument
1865 DecodeUnconditionalBranch(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeUnconditionalBranch() argument
1887 DecodeSystemPStateImm0_15Instruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeSystemPStateImm0_15Instruction() argument
1908 DecodeSystemPStateImm0_1Instruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeSystemPStateImm0_1Instruction() argument
1929 DecodeTestAndBranch(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeTestAndBranch() argument
1953 DecodeGPRSeqPairsClassRegisterClass(MCInst & Inst,unsigned RegClassID,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeGPRSeqPairsClassRegisterClass() argument
1966 DecodeWSeqPairsClassRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeWSeqPairsClassRegisterClass() argument
1974 DecodeXSeqPairsClassRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Addr,const MCDisassembler * Decoder) DecodeXSeqPairsClassRegisterClass() argument
1981 DecodeSyspXzrInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeSyspXzrInstruction() argument
2002 DecodeSVELogicalImmInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeSVELogicalImmInstruction() argument
2018 DecodeSImm(MCInst & Inst,uint64_t Imm,uint64_t Address,const MCDisassembler * Decoder) DecodeSImm() argument
2033 DecodeImm8OptLsl(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeImm8OptLsl() argument
2045 DecodeSVEIncDecImm(MCInst & Inst,unsigned Imm,uint64_t Addr,const MCDisassembler * Decoder) DecodeSVEIncDecImm() argument
2052 DecodeSVCROp(MCInst & Inst,unsigned Imm,uint64_t Address,const MCDisassembler * Decoder) DecodeSVCROp() argument
2061 DecodeCPYMemOpInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeCPYMemOpInstruction() argument
2086 DecodeSETMemOpInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodeSETMemOpInstruction() argument
2110 DecodePRFMRegInstruction(MCInst & Inst,uint32_t insn,uint64_t Addr,const MCDisassembler * Decoder) DecodePRFMRegInstruction() argument
[all...] |
| /llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrAnalysis.h | 53 virtual void updateState(const MCInst &Inst, uint64_t Addr) {} in updateState() argument
55 virtual bool isBranch(const MCInst &Inst) const { in isBranch() argument
59 virtual bool isConditionalBranch(const MCInst &Inst) const { in isConditionalBranch() argument
63 virtual bool isUnconditionalBranch(const MCInst &Inst) const { in isUnconditionalBranch() argument
67 virtual bool isIndirectBranch(const MCInst &Inst) const { in isIndirectBranch() argument
71 isCall(const MCInst & Inst) isCall() argument
75 isReturn(const MCInst & Inst) isReturn() argument
79 isTerminator(const MCInst & Inst) isTerminator() argument
83 mayAffectControlFlow(const MCInst & Inst,const MCRegisterInfo & MCRI) mayAffectControlFlow() argument
[all...] |
| /llvm-project/llvm/lib/Target/CSKY/Disassembler/ |
| H A D | CSKYDisassembler.cpp | 108 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGPRRegisterClass()
118 static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFPR32RegisterClass()
128 static DecodeStatus DecodesFPR32RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodesFPR32RegisterClass()
138 static DecodeStatus DecodesFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodesFPR64RegisterClass()
148 static DecodeStatus DecodesFPR64_VRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodesFPR64_VRegisterClass()
158 static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeFPR64RegisterClass()
170 static DecodeStatus DecodesFPR128RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodesFPR128RegisterClass()
180 static DecodeStatus DecodesGPRRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodesGPRRegisterClass()
190 static DecodeStatus DecodemGPRRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodemGPRRegisterClass()
202 static DecodeStatus DecodeGPRSPRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeGPRSPRegisterClass()
[all …]
|
| /llvm-project/llvm/lib/Target/Xtensa/Disassembler/ |
| H A D | XtensaDisassembler.cpp | 120 switch (Inst argument
67 DecodeARRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeARRegisterClass() argument
80 DecodeSRRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeSRRegisterClass() argument
106 decodeCallOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeCallOperand() argument
113 decodeJumpOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeJumpOperand() argument
141 decodeL32ROperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeL32ROperand() argument
150 decodeImm8Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm8Operand() argument
157 decodeImm8_sh8Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm8_sh8Operand() argument
165 decodeImm12Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm12Operand() argument
172 decodeUimm4Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeUimm4Operand() argument
179 decodeUimm5Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeUimm5Operand() argument
186 decodeImm1_16Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeImm1_16Operand() argument
193 decodeShimm1_31Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeShimm1_31Operand() argument
203 decodeB4constOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeB4constOperand() argument
213 decodeB4constuOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeB4constuOperand() argument
222 decodeMem8Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeMem8Operand() argument
230 decodeMem16Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeMem16Operand() argument
238 decodeMem32Operand(MCInst & Inst,uint64_t Imm,int64_t Address,const void * Decoder) decodeMem32Operand() argument
[all...] |
| /llvm-project/llvm/lib/Target/RISCV/Disassembler/ |
| H A D | RISCVDisassembler.cpp | 84 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRX1X5RegisterClass() argument
71 DecodeGPRRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRRegisterClass() argument
95 DecodeFPR16RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR16RegisterClass() argument
106 DecodeFPR32RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR32RegisterClass() argument
117 DecodeFPR32CRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR32CRegisterClass() argument
128 DecodeFPR64RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR64RegisterClass() argument
139 DecodeFPR64CRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR64CRegisterClass() argument
150 DecodeGPRNoX0RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRNoX0RegisterClass() argument
161 DecodeGPRNoX0X2RegisterClass(MCInst & Inst,uint64_t RegNo,uint32_t Address,const MCDisassembler * Decoder) DecodeGPRNoX0X2RegisterClass() argument
170 DecodeGPRCRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRCRegisterClass() argument
181 DecodeGPRPairRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRPairRegisterClass() argument
192 DecodeSR07RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const void * Decoder) DecodeSR07RegisterClass() argument
203 DecodeVRRegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVRRegisterClass() argument
214 DecodeVRM2RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVRM2RegisterClass() argument
231 DecodeVRM4RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVRM4RegisterClass() argument
248 DecodeVRM8RegisterClass(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVRM8RegisterClass() argument
265 decodeVMaskReg(MCInst & Inst,uint32_t RegNo,uint64_t Address,const MCDisassembler * Decoder) decodeVMaskReg() argument
278 decodeUImmOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeUImmOperand() argument
287 decodeUImmNonZeroOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeUImmNonZeroOperand() argument
296 decodeSImmOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeSImmOperand() argument
306 decodeSImmNonZeroOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeSImmNonZeroOperand() argument
315 decodeSImmOperandAndLsl1(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeSImmOperandAndLsl1() argument
326 decodeCLUIImmOperand(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeCLUIImmOperand() argument
337 decodeFRMArg(MCInst & Inst,uint32_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeFRMArg() argument
386 decodeRVCInstrRdRs1ImmZero(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeRVCInstrRdRs1ImmZero() argument
398 decodeCSSPushPopchk(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeCSSPushPopchk() argument
408 decodeRVCInstrRdSImm(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeRVCInstrRdSImm() argument
420 decodeRVCInstrRdRs1UImm(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeRVCInstrRdRs1UImm() argument
433 decodeRVCInstrRdRs2(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeRVCInstrRdRs2() argument
443 decodeRVCInstrRdRs1Rs2(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeRVCInstrRdRs1Rs2() argument
454 decodeXTHeadMemPair(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeXTHeadMemPair() argument
480 decodeZcmpRlist(MCInst & Inst,uint32_t Imm,uint64_t Address,const void * Decoder) decodeZcmpRlist() argument
488 decodeRegReg(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) decodeRegReg() argument
497 decodeZcmpSpimm(MCInst & Inst,uint32_t Imm,uint64_t Address,const void * Decoder) decodeZcmpSpimm() argument
[all...] |
| /llvm-project/llvm/lib/Target/Mips/Disassembler/ |
| H A D | MipsDisassembler.cpp | 352 DecodeUImmWithOffset(MCInst & Inst,unsigned Value,uint64_t Address,const MCDisassembler * Decoder) DecodeUImmWithOffset() argument
1338 DecodeCPU16RegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCPU16RegsRegisterClass() argument
1343 DecodeGPR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPR64RegisterClass() argument
1354 DecodeGPRMM16RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRMM16RegisterClass() argument
1365 DecodeGPRMM16ZeroRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRMM16ZeroRegisterClass() argument
1375 DecodeGPRMM16MovePRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRMM16MovePRegisterClass() argument
1384 DecodeGPR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPR32RegisterClass() argument
1394 DecodePtrRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodePtrRegisterClass() argument
1403 DecodeDSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeDSPRRegisterClass() argument
1409 DecodeFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFGR64RegisterClass() argument
1420 DecodeFGR32RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFGR32RegisterClass() argument
1431 DecodeCCRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCCRRegisterClass() argument
1441 DecodeFCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFCCRegisterClass() argument
1451 DecodeFGRCCRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFGRCCRegisterClass() argument
1462 DecodeMem(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMem() argument
1482 DecodeMemEVA(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemEVA() argument
1501 DecodeLoadByte15(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeLoadByte15() argument
1518 DecodeCacheOp(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeCacheOp() argument
1533 DecodeCacheOpMM(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeCacheOpMM() argument
1549 DecodePrefeOpMM(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodePrefeOpMM() argument
1565 DecodeCacheeOp_CacheOpR6(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeCacheeOp_CacheOpR6() argument
1581 DecodeSyncI(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSyncI() argument
1594 DecodeSyncI_MM(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSyncI_MM() argument
1608 DecodeSynciR6(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSynciR6() argument
1621 DecodeMSA128Mem(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMSA128Mem() argument
1668 DecodeMemMMImm4(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMImm4() argument
1725 DecodeMemMMSPImm5Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMSPImm5Lsl2() argument
1740 DecodeMemMMGPImm7Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMGPImm7Lsl2() argument
1755 DecodeMemMMReglistImm4Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMReglistImm4Lsl2() argument
1779 DecodeMemMMImm9(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMImm9() argument
1799 DecodeMemMMImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMImm12() argument
1833 DecodeMemMMImm16(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMMImm16() argument
1850 DecodeFMem(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMem() argument
1866 DecodeFMemMMR2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMemMMR2() argument
1885 DecodeFMem2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMem2() argument
1901 DecodeFMem3(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMem3() argument
1917 DecodeFMemCop2R6(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMemCop2R6() argument
1934 DecodeFMemCop2MMR6(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFMemCop2MMR6() argument
1951 DecodeSpecial3LlSc(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSpecial3LlSc() argument
1972 DecodeHWRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeHWRegsRegisterClass() argument
1982 DecodeAFGR64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeAFGR64RegisterClass() argument
1993 DecodeACC64DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeACC64DSPRegisterClass() argument
2004 DecodeHI32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeHI32DSPRegisterClass() argument
2015 DecodeLO32DSPRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeLO32DSPRegisterClass() argument
2026 DecodeMSA128BRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMSA128BRegisterClass() argument
2037 DecodeMSA128HRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMSA128HRegisterClass() argument
2048 DecodeMSA128WRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMSA128WRegisterClass() argument
2059 DecodeMSA128DRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMSA128DRegisterClass() argument
2070 DecodeMSACtrlRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMSACtrlRegisterClass() argument
2081 DecodeCOP0RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCOP0RegisterClass() argument
2092 DecodeCOP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCOP2RegisterClass() argument
2103 DecodeBranchTarget(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget() argument
2111 DecodeBranchTarget1SImm16(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget1SImm16() argument
2119 DecodeJumpTarget(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeJumpTarget() argument
2127 DecodeBranchTarget21(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget21() argument
2136 DecodeBranchTarget21MM(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget21MM() argument
2145 DecodeBranchTarget26(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget26() argument
2154 DecodeBranchTarget7MM(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget7MM() argument
2162 DecodeBranchTarget10MM(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget10MM() argument
2170 DecodeBranchTargetMM(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTargetMM() argument
2178 DecodeBranchTarget26MM(MCInst & Inst,unsigned Offset,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchTarget26MM() argument
2187 DecodeJumpTargetMM(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeJumpTargetMM() argument
2195 DecodeJumpTargetXMM(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeJumpTargetXMM() argument
2203 DecodeAddiur2Simm7(MCInst & Inst,unsigned Value,uint64_t Address,const MCDisassembler * Decoder) DecodeAddiur2Simm7() argument
2215 DecodeLi16Imm(MCInst & Inst,unsigned Value,uint64_t Address,const MCDisassembler * Decoder) DecodeLi16Imm() argument
2225 DecodePOOL16BEncodedField(MCInst & Inst,unsigned Value,uint64_t Address,const MCDisassembler * Decoder) DecodePOOL16BEncodedField() argument
2234 DecodeUImmWithOffsetAndScale(MCInst & Inst,unsigned Value,uint64_t Address,const MCDisassembler * Decoder) DecodeUImmWithOffsetAndScale() argument
2244 DecodeSImmWithOffsetAndScale(MCInst & Inst,unsigned Value,uint64_t Address,const MCDisassembler * Decoder) DecodeSImmWithOffsetAndScale() argument
2251 DecodeInsSize(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeInsSize() argument
2262 DecodeSimm19Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSimm19Lsl2() argument
2269 DecodeSimm18Lsl3(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSimm18Lsl3() argument
2276 DecodeSimm9SP(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSimm9SP() argument
2290 DecodeANDI16Imm(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeANDI16Imm() argument
2301 DecodeRegListOperand(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeRegListOperand() argument
2329 DecodeRegListOperand16(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeRegListOperand16() argument
2353 DecodeMovePOperands(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMovePOperands() argument
2379 DecodeMovePRegPair(MCInst & Inst,unsigned RegPair,uint64_t Address,const MCDisassembler * Decoder) DecodeMovePRegPair() argument
2422 DecodeSimm23Lsl2(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSimm23Lsl2() argument
2524 DecodeFIXMEInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeFIXMEInstruction() argument
[all...] |
| /llvm-project/llvm/lib/Target/ARM/Disassembler/ |
| H A D | ARMDisassembler.cpp | 1296 DecodeGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRRegisterClass() argument
1307 DecodeCLRMGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCLRMGPRRegisterClass() argument
1321 DecodeGPRnopcRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRnopcRegisterClass() argument
1334 DecodeGPRnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRnospRegisterClass() argument
1348 DecodeGPRwithAPSRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRwithAPSRRegisterClass() argument
1363 DecodeGPRwithZRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRwithZRRegisterClass() argument
1381 DecodeGPRwithZRnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRwithZRnospRegisterClass() argument
1390 DecodetGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodetGPRRegisterClass() argument
1403 DecodeGPRPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRPairRegisterClass() argument
1422 DecodeGPRPairnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRPairnospRegisterClass() argument
1435 DecodeGPRspRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRspRegisterClass() argument
1446 DecodetcGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodetcGPRRegisterClass() argument
1477 DecoderGPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecoderGPRRegisterClass() argument
1503 DecodeSPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeSPRRegisterClass() argument
1514 DecodeHPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeHPRRegisterClass() argument
1531 DecodeDPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeDPRRegisterClass() argument
1547 DecodeDPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeDPR_8RegisterClass() argument
1555 DecodeSPR_8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeSPR_8RegisterClass() argument
1563 DecodeDPR_VFP2RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeDPR_VFP2RegisterClass() argument
1578 DecodeQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeQPRRegisterClass() argument
1599 DecodeDPairRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeDPairRegisterClass() argument
1622 DecodeDPairSpacedRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeDPairSpacedRegisterClass() argument
1632 DecodePredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodePredicateOperand() argument
1652 DecodeCCOutOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeCCOutOperand() argument
1662 DecodeSORegImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeSORegImmOperand() argument
1700 DecodeSORegRegOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeSORegRegOperand() argument
1736 DecodeRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeRegListOperand() argument
1784 DecodeSPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeSPRRegListOperand() argument
1809 DecodeDPRRegListOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeDPRRegListOperand() argument
1835 DecodeBitfieldMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeBitfieldMaskOperand() argument
1863 DecodeCopMemInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeCopMemInstruction() argument
2043 DecodeAddrMode2IdxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrMode2IdxInstruction() argument
2148 DecodeSORegMemOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeSORegMemOperand() argument
2192 DecodeTSBInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeTSBInstruction() argument
2205 DecodeAddrMode3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrMode3Instruction() argument
2397 DecodeRFEInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeRFEInstruction() argument
2427 DecodeQADDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeQADDInstruction() argument
2452 DecodeMemMultipleWritebackInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMemMultipleWritebackInstruction() argument
2544 DecodeHINTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeHINTInstruction() argument
2567 DecodeCPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeCPSInstruction() argument
2615 DecodeT2CPSInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2CPSInstruction() argument
2659 DecodeT2HintSpaceInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2HintSpaceInstruction() argument
2683 DecodeT2MOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2MOVTWInstruction() argument
2708 DecodeArmMOVTWInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeArmMOVTWInstruction() argument
2736 DecodeSMLAInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSMLAInstruction() argument
2765 DecodeTSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeTSTInstruction() argument
2787 DecodeSETPANInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSETPANInstruction() argument
2816 DecodeAddrModeImm12Operand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrModeImm12Operand() argument
2837 DecodeAddrMode5Operand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrMode5Operand() argument
2858 DecodeAddrMode5FP16Operand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrMode5FP16Operand() argument
2879 DecodeAddrMode7Operand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrMode7Operand() argument
2885 DecodeT2BInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2BInstruction() argument
2912 DecodeBranchImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeBranchImmInstruction() argument
2942 DecodeAddrMode6Operand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeAddrMode6Operand() argument
2960 DecodeVLDInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLDInstruction() argument
3237 DecodeVLDST1Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLDST1Instruction() argument
3251 DecodeVLDST2Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLDST2Instruction() argument
3267 DecodeVLDST3Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLDST3Instruction() argument
3281 DecodeVLDST4Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLDST4Instruction() argument
3292 DecodeVSTInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVSTInstruction() argument
3563 DecodeVLD1DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD1DupInstruction() argument
3611 DecodeVLD2DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD2DupInstruction() argument
3660 DecodeVLD3DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD3DupInstruction() argument
3696 DecodeVLD4DupInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD4DupInstruction() argument
3749 DecodeVMOVModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVMOVModImmInstruction() argument
3795 DecodeMVEModImmInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEModImmInstruction() argument
3824 DecodeMVEVADCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEVADCInstruction() argument
3850 DecodeVSHLMaxInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVSHLMaxInstruction() argument
3870 DecodeShiftRight8Imm(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeShiftRight8Imm() argument
3877 DecodeShiftRight16Imm(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeShiftRight16Imm() argument
3884 DecodeShiftRight32Imm(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeShiftRight32Imm() argument
3891 DecodeShiftRight64Imm(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeShiftRight64Imm() argument
3898 DecodeTBLInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeTBLInstruction() argument
3935 DecodeThumbAddSpecialReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddSpecialReg() argument
3960 DecodeThumbBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbBROperand() argument
3969 DecodeT2BROperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2BROperand() argument
3978 DecodeThumbCmpBROperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbCmpBROperand() argument
3987 DecodeThumbAddrModeRR(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddrModeRR() argument
4003 DecodeThumbAddrModeIS(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddrModeIS() argument
4018 DecodeThumbAddrModePC(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddrModePC() argument
4029 DecodeThumbAddrModeSP(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddrModeSP() argument
4038 DecodeT2AddrModeSOReg(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeSOReg() argument
4068 DecodeT2LoadShift(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LoadShift() argument
4152 DecodeT2LoadImm8(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LoadImm8() argument
4237 DecodeT2LoadImm12(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LoadImm12() argument
4318 DecodeT2LoadT(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LoadT() argument
4357 DecodeT2LoadLabel(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LoadLabel() argument
4411 DecodeT2Imm8S4(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2Imm8S4() argument
4425 DecodeT2Imm7S4(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2Imm7S4() argument
4440 DecodeT2AddrModeImm8s4(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeImm8s4() argument
4456 DecodeT2AddrModeImm7s4(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeImm7s4() argument
4472 DecodeT2AddrModeImm0_1020s4(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeImm0_1020s4() argument
4488 DecodeT2Imm8(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2Imm8() argument
4501 DecodeT2Imm7(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2Imm7() argument
4515 DecodeT2AddrModeImm8(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeImm8() argument
4563 DecodeTAddrModeImm7(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeTAddrModeImm7() argument
4580 DecodeT2AddrModeImm7(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeImm7() argument
4598 DecodeT2LdStPre(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LdStPre() argument
4660 DecodeT2AddrModeImm12(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddrModeImm12() argument
4687 DecodeThumbAddSPImm(MCInst & Inst,uint16_t Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddSPImm() argument
4699 DecodeThumbAddSPReg(MCInst & Inst,uint16_t Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbAddSPReg() argument
4725 DecodeThumbCPS(MCInst & Inst,uint16_t Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbCPS() argument
4737 DecodePostIdxReg(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodePostIdxReg() argument
4751 DecodeMveAddrModeRQ(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMveAddrModeRQ() argument
4767 DecodeMveAddrModeQ(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMveAddrModeQ() argument
4790 DecodeThumbBLXOffset(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbBLXOffset() argument
4815 DecodeCoprocessor(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeCoprocessor() argument
4831 DecodeThumbTableBranch(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbTableBranch() argument
4849 DecodeThumb2BCCInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeThumb2BCCInstruction() argument
4892 DecodeT2SOImm(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2SOImm() argument
4923 DecodeThumbBCCTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbBCCTargetOperand() argument
4932 DecodeThumbBLTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeThumbBLTargetOperand() argument
4956 DecodeMemBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeMemBarrierOption() argument
4966 DecodeInstSyncBarrierOption(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeInstSyncBarrierOption() argument
4976 DecodeMSRMask(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeMSRMask() argument
5077 DecodeBankedReg(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeBankedReg() argument
5093 DecodeDoubleRegLoad(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeDoubleRegLoad() argument
5115 DecodeDoubleRegStore(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeDoubleRegStore() argument
5141 DecodeLDRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeLDRPreImm() argument
5167 DecodeLDRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeLDRPreReg() argument
5195 DecodeSTRPreImm(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSTRPreImm() argument
5221 DecodeSTRPreReg(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSTRPreReg() argument
5247 DecodeVLD1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD1LN() argument
5314 DecodeVST1LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVST1LN() argument
5379 DecodeVLD2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD2LN() argument
5446 DecodeVST2LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVST2LN() argument
5509 DecodeVLD3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD3LN() argument
5579 DecodeVST3LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVST3LN() argument
5642 DecodeVLD4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVLD4LN() argument
5723 DecodeVST4LN(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVST4LN() argument
5795 DecodeVMOVSRR(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVMOVSRR() argument
5821 DecodeVMOVRRS(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVMOVRRS() argument
5847 DecodeIT(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeIT() argument
5876 DecodeT2LDRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2LDRDPreInstruction() argument
5913 DecodeT2STRDPreInstruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2STRDPreInstruction() argument
5948 DecodeT2Adr(MCInst & Inst,uint32_t Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2Adr() argument
5974 DecodeT2ShifterImmOperand(MCInst & Inst,uint32_t Val,uint64_t Address,const MCDisassembler * Decoder) DecodeT2ShifterImmOperand() argument
5985 DecodeSwap(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeSwap() argument
6012 DecodeVCVTD(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVCVTD() argument
6071 DecodeVCVTQ(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVCVTQ() argument
6131 DecodeNEONComplexLane64Instruction(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeNEONComplexLane64Instruction() argument
6163 DecodeLDR(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeLDR() argument
6190 DecoderForMRRC2AndMCRR2(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecoderForMRRC2AndMCRR2() argument
6236 DecodeForVMRSandVMSR(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeForVMRSandVMSR() argument
6288 DecodeBFLabelOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeBFLabelOperand() argument
6307 DecodeBFAfterTargetOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeBFAfterTargetOperand() argument
6319 DecodePredNoALOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodePredNoALOperand() argument
6328 DecodeLOLoop(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeLOLoop() argument
6390 DecodeLongShiftOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeLongShiftOperand() argument
6403 DecodetGPROddRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodetGPROddRegisterClass() argument
6414 DecodetGPREvenRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodetGPREvenRegisterClass() argument
6426 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRwithAPSR_NZCVnospRegisterClass() argument
6443 DecodeVSCCLRM(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeVSCCLRM() argument
6469 DecodeMQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMQPRRegisterClass() argument
6485 DecodeMQQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMQQPRRegisterClass() argument
6501 DecodeMQQQQPRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeMQQQQPRRegisterClass() argument
6512 DecodeVPTMaskOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeVPTMaskOperand() argument
6543 DecodeVpredROperand(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVpredROperand() argument
6557 DecodeVpredNOperand(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeVpredNOperand() argument
6568 DecodeRestrictedIPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeRestrictedIPredicateOperand() argument
6575 DecodeRestrictedSPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeRestrictedSPredicateOperand() argument
6597 DecodeRestrictedUPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeRestrictedUPredicateOperand() argument
6604 DecodeRestrictedFPPredicateOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeRestrictedFPPredicateOperand() argument
6634 DecodeVCVTImmOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeVCVTImmOperand() argument
6678 DecodeVSTRVLDR_SYSREG(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeVSTRVLDR_SYSREG() argument
6722 DecodeMVE_MEM_pre(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder,unsigned Rn,OperandDecoder RnDecoder,OperandDecoder AddrDecoder) DecodeMVE_MEM_pre() argument
6742 DecodeMVE_MEM_1_pre(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeMVE_MEM_1_pre() argument
6752 DecodeMVE_MEM_2_pre(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeMVE_MEM_2_pre() argument
6762 DecodeMVE_MEM_3_pre(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeMVE_MEM_3_pre() argument
6772 DecodePowerTwoOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodePowerTwoOperand() argument
6786 DecodeMVEPairVectorIndexOperand(MCInst & Inst,unsigned Val,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEPairVectorIndexOperand() argument
6795 DecodeMVEVMOVQtoDReg(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEVMOVQtoDReg() argument
6819 DecodeMVEVMOVDRegtoQ(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEVMOVDRegtoQ() argument
6846 DecodeMVEOverlappingLongShift(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEOverlappingLongShift() argument
6925 DecodeMVEVCVTt1fp(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEVCVTt1fp() argument
6946 DecodeMVEVCMP(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEVCMP() argument
6983 DecodeMveVCTP(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMveVCTP() argument
6993 DecodeMVEVPNOT(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeMVEVPNOT() argument
7002 DecodeT2AddSubSPImm(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeT2AddSubSPImm() argument
7037 DecodeLazyLoadStoreMul(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) DecodeLazyLoadStoreMul() argument
[all...] |
| /llvm-project/llvm/lib/Target/LoongArch/Disassembler/ |
| H A D | LoongArchDisassembler.cpp | 58 DecodeGPRRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPRRegisterClass() argument
67 DecodeFPR32RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR32RegisterClass() argument
76 DecodeFPR64RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFPR64RegisterClass() argument
85 DecodeCFRRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeCFRRegisterClass() argument
94 DecodeFCSRRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeFCSRRegisterClass() argument
103 DecodeLSX128RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeLSX128RegisterClass() argument
112 DecodeLASX256RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeLASX256RegisterClass() argument
121 DecodeSCRRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeSCRRegisterClass() argument
131 decodeUImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeUImmOperand() argument
140 decodeSImmOperand(MCInst & Inst,uint64_t Imm,int64_t Address,const MCDisassembler * Decoder) decodeSImmOperand() argument
[all...] |
| /llvm-project/llvm/lib/Target/M68k/Disassembler/ |
| H A D | M68kDisassembler.cpp | 42 static DecodeStatus DecodeRegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeRegisterClass() argument
50 static DecodeStatus DecodeDR32RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeDR32RegisterClass() argument
56 static DecodeStatus DecodeDR16RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeDR16RegisterClass() argument
62 static DecodeStatus DecodeDR8RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeDR8RegisterClass() argument
68 static DecodeStatus DecodeAR32RegisterClass(MCInst &Inst, uint64_t RegNo, in DecodeAR32RegisterClass() argument
74 DecodeAR16RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeAR16RegisterClass() argument
80 DecodeXR32RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeXR32RegisterClass() argument
86 DecodeXR16RegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeXR16RegisterClass() argument
92 DecodeFPDRRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeFPDRRegisterClass() argument
101 DecodeFPCSCRegisterClass(MCInst & Inst,uint64_t RegNo,uint64_t Address,const void * Decoder) DecodeFPCSCRegisterClass() argument
108 DecodeCCRCRegisterClass(MCInst & Inst,APInt & Insn,uint64_t Address,const void * Decoder) DecodeCCRCRegisterClass() argument
114 DecodeImm32(MCInst & Inst,uint64_t Imm,uint64_t Address,const void * Decoder) DecodeImm32() argument
[all...] |
| /llvm-project/bolt/lib/Core/ |
| H A D | MCPlusBuilder.cpp | 166 void MCPlusBuilder::addEHInfo(MCInst &Inst, const MCLandingPad &LP) const { in addEHInfo()
176 bool MCPlusBuilder::updateEHInfo(MCInst &Inst, const MCLandingPad &LP) const { in updateEHInfo()
195 void MCPlusBuilder::addGnuArgsSize(MCInst &Inst, int64_t GnuArgsSize) const { in addGnuArgsSize()
215 bool MCPlusBuilder::setJumpTable(MCInst &Inst, uint64_t Value, in setJumpTable()
241 bool MCPlusBuilder::setConditionalTailCall(MCInst &Inst, uint64_t Dest) const { in setConditionalTailCall()
264 uint32_t MCPlusBuilder::getOffsetWithDefault(const MCInst &Inst, in getOffsetWithDefault()
271 bool MCPlusBuilder::setOffset(MCInst &Inst, uint32_t Offset) const { in setOffset()
290 MCSymbol *MCPlusBuilder::getOrCreateInstLabel(MCInst &Inst, const Twine &Name, in getOrCreateInstLabel()
302 void MCPlusBuilder::setInstLabel(MCInst &Inst, MCSymbol *Label) const { in setInstLabel()
315 void MCPlusBuilder::setSize(MCInst &Inst, uint32_t Size) const { in setSize()
[all …]
|
| /llvm-project/llvm/lib/Target/AVR/Disassembler/ |
| H A D | AVRDisassembler.cpp | 70 DecodeGPR8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGPR8RegisterClass() argument
81 DecodeLD8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeLD8RegisterClass() argument
142 decodeFIOARr(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFIOARr() argument
155 decodeFIORdA(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFIORdA() argument
168 decodeFIOBIT(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFIOBIT() argument
177 decodeCallTarget(MCInst & Inst,unsigned Field,uint64_t Address,const MCDisassembler * Decoder) decodeCallTarget() argument
186 decodeFRd(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFRd() argument
195 decodeFLPMX(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFLPMX() argument
203 decodeFFMULRdRr(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFFMULRdRr() argument
217 decodeFMOVWRdRr(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFMOVWRdRr() argument
231 decodeFWRdK(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFWRdK() argument
247 decodeFMUL2RdRr(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFMUL2RdRr() argument
261 decodeMemri(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeMemri() argument
278 decodeFBRk(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeFBRk() argument
297 decodeCondBranch(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeCondBranch() argument
331 decodeLoadStore(MCInst & Inst,unsigned Insn,uint64_t Address,const MCDisassembler * Decoder) decodeLoadStore() argument
[all...] |
| /llvm-project/polly/include/polly/ |
| H A D | ScopDetectionDiagnostic.h | 282 Instruction *Inst; variable
286 ReportIndirectPredecessor(Instruction *Inst, DebugLoc DbgLoc) in ReportIndirectPredecessor()
336 ReportUndefCond(const Instruction *Inst, BasicBlock *BB) in ReportUndefCond()
361 ReportInvalidCond(const Instruction *Inst, BasicBlock *BB) in ReportInvalidCond()
384 ReportUndefOperand(BasicBlock *BB, const Instruction *Inst) in ReportUndefOperand()
414 const Instruction *Inst) in ReportNonAffBranch()
438 ReportNoBasePtr(const Instruction *Inst) in ReportNoBasePtr()
458 ReportUndefBasePtr(const Instruction *Inst) in ReportUndefBasePtr()
481 ReportVariantBasePtr(Value *BaseValue, const Instruction *Inst) in ReportVariantBasePtr()
509 ReportNonAffineAccess(const SCEV *AccessFunction, const Instruction *Inst, in ReportNonAffineAccess()
[all …]
|
| /llvm-project/llvm/lib/Target/Lanai/MCTargetDesc/ |
| H A D | LanaiMCCodeEmitter.cpp | 111 getMachineOpValue(const MCInst & Inst,const MCOperand & MCOp,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getMachineOpValue() argument
136 adjustPqBits(const MCInst & Inst,unsigned Value,unsigned PBitShift,unsigned QBitShift) adjustPqBits() argument
162 adjustPqBitsRmAndRrm(const MCInst & Inst,unsigned Value,const MCSubtargetInfo & STI) const adjustPqBitsRmAndRrm() argument
168 adjustPqBitsSpls(const MCInst & Inst,unsigned Value,const MCSubtargetInfo & STI) const adjustPqBitsSpls() argument
174 encodeInstruction(const MCInst & Inst,SmallVectorImpl<char> & CB,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const encodeInstruction() argument
186 getRiMemoryOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getRiMemoryOpValue() argument
218 getRrMemoryOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getRrMemoryOpValue() argument
256 getSplsOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getSplsOpValue() argument
289 getBranchTargetOpValue(const MCInst & Inst,unsigned OpNo,SmallVectorImpl<MCFixup> & Fixups,const MCSubtargetInfo & SubtargetInfo) const getBranchTargetOpValue() argument
[all...] |
| /llvm-project/llvm/lib/Target/XCore/Disassembler/ |
| H A D | XCoreDisassembler.cpp | 176 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeGRRegsRegisterClass()
186 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeRRegsRegisterClass()
196 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val, in DecodeBitpOperand()
208 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val, in DecodeNegImmOperand()
249 static DecodeStatus Decode2OpInstructionFail(MCInst &Inst, unsigned Insn, in Decode2OpInstructionFail()
319 static DecodeStatus Decode2RInstruction(MCInst &Inst, unsigned Insn, in Decode2RInstruction()
332 static DecodeStatus Decode2RImmInstruction(MCInst &Inst, unsigned Insn, in Decode2RImmInstruction()
345 static DecodeStatus DecodeR2RInstruction(MCInst &Inst, unsigned Insn, in DecodeR2RInstruction()
358 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst, unsigned Insn, in Decode2RSrcDstInstruction()
372 static DecodeStatus DecodeRUSInstruction(MCInst &Inst, unsigned Insn, in DecodeRUSInstruction()
[all …]
|
| /llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsAnalyzeImmediate.h | 19 struct Inst { struct
22 Inst(unsigned Opc, unsigned ImmOpnd); argument
|
| /llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
| H A D | HexagonDisassembler.cpp | 187 MCInst *Inst = getContext().createMCInst(); getInstruction() local
498 auto const &Inst = *i->getInst(); getSingleInstruction() local
529 MCInst const &Inst = HexagonMCInstrInfo::isDuplex(*MCII, MI) getSingleInstruction() local
539 DecodeRegisterClass(MCInst & Inst,unsigned RegNo,ArrayRef<MCPhysReg> Table) DecodeRegisterClass() argument
550 DecodeIntRegsLow8RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeIntRegsLow8RegisterClass() argument
555 DecodeIntRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeIntRegsRegisterClass() argument
571 DecodeGeneralSubRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t Address,const MCDisassembler * Decoder) DecodeGeneralSubRegsRegisterClass() argument
584 DecodeHvxVRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeHvxVRRegisterClass() argument
600 DecodeDoubleRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeDoubleRegsRegisterClass() argument
613 DecodeGeneralDoubleLow8RegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeGeneralDoubleLow8RegsRegisterClass() argument
623 DecodeHvxWRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeHvxWRRegisterClass() argument
641 DecodeHvxVQRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeHvxVQRRegisterClass() argument
651 DecodePredRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodePredRegsRegisterClass() argument
660 DecodeHvxQRRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeHvxQRRegisterClass() argument
669 DecodeCtrRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeCtrRegsRegisterClass() argument
698 DecodeCtrRegs64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeCtrRegs64RegisterClass() argument
725 DecodeModRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeModRegsRegisterClass() argument
809 DecodeSysRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeSysRegsRegisterClass() argument
837 DecodeSysRegs64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeSysRegs64RegisterClass() argument
852 DecodeGuestRegsRegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeGuestRegsRegisterClass() argument
878 DecodeGuestRegs64RegisterClass(MCInst & Inst,unsigned RegNo,uint64_t,const MCDisassembler * Decoder) DecodeGuestRegs64RegisterClass() argument
[all...] |
| /llvm-project/llvm/lib/Target/ARC/Disassembler/ |
| H A D | ARCDisassembler.cpp | 131 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo, in DecodeGPR32RegisterClass()
144 static DecodeStatus DecodeGBR32ShortRegister(MCInst &Inst, unsigned RegNo, in DecodeGBR32ShortRegister()
169 static DecodeStatus DecodeMEMrs9(MCInst &Inst, unsigned Insn, uint64_t Address, in DecodeMEMrs9()
179 static bool DecodeSymbolicOperand(MCInst &Inst, uint64_t Address, in DecodeSymbolicOperand()
187 static void DecodeSymbolicOperandOff(MCInst &Inst, uint64_t Address, in DecodeSymbolicOperandOff()
197 static DecodeStatus DecodeBranchTargetS(MCInst &Inst, unsigned InsnS, in DecodeBranchTargetS()
207 static DecodeStatus DecodeSignedOperand(MCInst &Inst, unsigned InsnS, in DecodeSignedOperand()
218 static DecodeStatus DecodeFromCyclicRange(MCInst &Inst, unsigned InsnS, in DecodeFromCyclicRange()
229 static DecodeStatus DecodeStLImmInstruction(MCInst &Inst, uint64_t Insn, in DecodeStLImmInstruction()
246 static DecodeStatus DecodeLdLImmInstruction(MCInst &Inst, uint64_t Insn, in DecodeLdLImmInstruction()
[all …]
|
| /llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
| H A D | SparcDisassembler.cpp | 141 static DecodeStatus DecodeIntRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeIntRegsRegisterClass()
151 static DecodeStatus DecodeI64RegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeI64RegsRegisterClass()
159 static DecodeStatus DecodePointerLikeRegClass0(MCInst &Inst, unsigned RegNo, in DecodePointerLikeRegClass0()
165 static DecodeStatus DecodeFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeFPRegsRegisterClass()
175 static DecodeStatus DecodeDFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeDFPRegsRegisterClass()
185 static DecodeStatus DecodeQFPRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeQFPRegsRegisterClass()
199 DecodeCoprocRegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address, in DecodeCoprocRegsRegisterClass()
208 static DecodeStatus DecodeFCCRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeFCCRegsRegisterClass()
217 static DecodeStatus DecodeASRRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodeASRRegsRegisterClass()
226 static DecodeStatus DecodePRRegsRegisterClass(MCInst &Inst, unsigned RegNo, in DecodePRRegsRegisterClass()
[all …]
|
| /llvm-project/bolt/lib/Target/RISCV/ |
| H A D | RISCVMCPlusBuilder.cpp | 154 reverseBranchCondition(MCInst & Inst,const MCSymbol * TBB,MCContext * Ctx) const reverseBranchCondition() argument
161 replaceBranchTarget(MCInst & Inst,const MCSymbol * TBB,MCContext * Ctx) const replaceBranchTarget() argument
200 convertJmpToTailCall(MCInst & Inst) convertJmpToTailCall() argument
227 createUncondBranch(MCInst & Inst,const MCSymbol * TBB,MCContext * Ctx) const createUncondBranch() argument
240 createCall(unsigned Opcode,MCInst & Inst,const MCSymbol * Target,MCContext * Ctx) createCall() argument
249 createCall(MCInst & Inst,const MCSymbol * Target,MCContext * Ctx) createCall() argument
254 createTailCall(MCInst & Inst,const MCSymbol * Target,MCContext * Ctx) createTailCall() argument
311 getSymbolRefOperandNum(const MCInst & Inst,unsigned & OpNum) const getSymbolRefOperandNum() argument
351 getTargetSymbol(const MCInst & Inst,unsigned OpNum=0) const getTargetSymbol() argument
363 lowerTailCall(MCInst & Inst) lowerTailCall() argument
405 replaceImmWithSymbolRef(MCInst & Inst,const MCSymbol * Symbol,int64_t Addend,MCContext * Ctx,int64_t & Value,uint64_t RelType) const replaceImmWithSymbolRef() argument
426 getTargetExprFor(MCInst & Inst,const MCExpr * Expr,MCContext & Ctx,uint64_t RelType) const getTargetExprFor() argument
452 evaluateMemOperandTarget(const MCInst & Inst,uint64_t & Target,uint64_t Address,uint64_t Size) const evaluateMemOperandTarget() argument
[all...] |
| /llvm-project/llvm/lib/MC/ |
| H A D | MCInstrAnalysis.cpp | 21 const MCInst &Inst, in clearsSuperRegisters()
34 const MCInst &Inst, const MCSubtargetInfo *STI, uint64_t Addr, in evaluateMemoryOperandAddress()
40 MCInstrAnalysis::getMemoryOperandRelocationOffset(const MCInst &Inst, in getMemoryOperandRelocationOffset()
|
| /llvm-project/bolt/lib/Target/AArch64/ |
| H A D | AArch64MCPlusBuilder.cpp | 42 Inst.addOperand(MCOperand::createImm(AArch64SysReg::NZCV)); in setSystemFlag() argument
49 Inst argument
35 getSystemFlag(MCInst & Inst,MCPhysReg RegName) getSystemFlag() argument
60 createPopRegisters(MCInst & Inst,MCPhysReg Reg1,MCPhysReg Reg2) createPopRegisters() argument
71 loadReg(MCInst & Inst,MCPhysReg To,MCPhysReg From) loadReg() argument
87 storeReg(MCInst & Inst,MCPhysReg From,MCPhysReg To) storeReg() argument
103 atomicAdd(MCInst & Inst,MCPhysReg RegTo,MCPhysReg RegCnt) atomicAdd() argument
112 createMovz(MCInst & Inst,MCPhysReg Reg,uint64_t Imm) createMovz() argument
160 getADRReg(const MCInst & Inst,MCPhysReg & RegName) const getADRReg() argument
317 isRegToRegMove(const MCInst & Inst,MCPhysReg & From,MCPhysReg & To) const isRegToRegMove() argument
393 evaluateADR(const MCInst & Inst,int64_t & Imm,const MCExpr ** DispExpr) const evaluateADR() argument
413 evaluateAArch64MemoryOperand(const MCInst & Inst,int64_t & DispImm,const MCExpr ** DispExpr=nullptr) const evaluateAArch64MemoryOperand() argument
437 evaluateMemOperandTarget(const MCInst & Inst,uint64_t & Target,uint64_t Address,uint64_t Size) const evaluateMemOperandTarget() argument
474 replaceMemOperandDisp(MCInst & Inst,MCOperand Operand) const replaceMemOperandDisp() argument
496 getTargetExprFor(MCInst & Inst,const MCExpr * Expr,MCContext & Ctx,uint64_t RelType) const getTargetExprFor() argument
543 getSymbolRefOperandNum(const MCInst & Inst,unsigned & OpNum) const getSymbolRefOperandNum() argument
575 getTargetSymbol(const MCInst & Inst,unsigned OpNum=0) const getTargetSymbol() argument
603 getTargetAddend(const MCInst & Inst,unsigned OpNum=0) const getTargetAddend() argument
615 replaceBranchTarget(MCInst & Inst,const MCSymbol * TBB,MCContext * Ctx) const replaceBranchTarget() argument
653 analyzeIndirectBranchFragment(const MCInst & Inst,DenseMap<const MCInst *,SmallVector<MCInst *,4>> & UDChain,const MCExpr * & JumpTable,int64_t & Offset,int64_t & ScaleValue,MCInst * & PCRelBase) const analyzeIndirectBranchFragment() argument
992 reverseBranchCondition(MCInst & Inst,const MCSymbol * TBB,MCContext * Ctx) const reverseBranchCondition() argument
1049 createTailCall(MCInst & Inst,const MCSymbol * Target,MCContext * Ctx) createTailCall() argument
1065 convertJmpToTailCall(MCInst & Inst) convertJmpToTailCall() argument
1070 convertTailCallToJmp(MCInst & Inst) convertTailCallToJmp() argument
1119 lowerTailCall(MCInst & Inst) lowerTailCall() argument
1139 createDirectCall(MCInst & Inst,const MCSymbol * Target,MCContext * Ctx,bool IsTailCall) createDirectCall() argument
1211 MCInst Inst; createLongJmp() local
1269 MCInst &Inst = Insts.back(); createShortJmp() local
1333 replaceImmWithSymbolRef(MCInst & Inst,const MCSymbol * Symbol,int64_t Addend,MCContext * Ctx,int64_t & Value,uint64_t RelType) const replaceImmWithSymbolRef() argument
1354 createUncondBranch(MCInst & Inst,const MCSymbol * TBB,MCContext * Ctx) const createUncondBranch() argument
1420 createStackPointerIncrement(MCInst & Inst,int Size,bool NoFlagsClobber=false) const createStackPointerIncrement() argument
1431 createStackPointerDecrement(MCInst & Inst,int Size,bool NoFlagsClobber=false) const createStackPointerDecrement() argument
1441 createIndirectBranch(MCInst & Inst,MCPhysReg MemBaseReg,int64_t Disp) const createIndirectBranch() argument
1500 convertIndirectCallToLoad(MCInst & Inst,MCPhysReg Reg) convertIndirectCallToLoad() argument
1528 createIndirectCallInst(MCInst & Inst,bool IsTailCall,MCPhysReg Reg) const createIndirectCallInst() argument
[all...] |