Lines Matching defs:Inst
39 static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
43 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
46 static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
49 static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
52 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
55 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
59 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
63 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
66 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
70 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
73 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
76 static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
79 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
82 static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm,
85 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
88 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
91 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
95 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
97 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
101 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
103 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
107 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
109 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
112 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
115 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
118 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
121 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
124 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
127 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
130 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
133 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
137 DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn,
141 DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn,
144 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
148 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
151 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
154 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
157 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
160 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
163 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
166 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
169 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
172 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
175 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
178 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
181 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
185 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
188 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
190 static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
194 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Address,
197 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
200 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
202 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
205 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
207 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
210 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
213 static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
338 static DecodeStatus DecodeSimpleRegisterClass(MCInst &Inst, unsigned RegNo,
346 Inst.addOperand(MCOperand::createReg(Register));
351 DecodeGPR64x8ClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
361 Inst.addOperand(MCOperand::createReg(Register));
366 static DecodeStatus DecodeZPRMul2_MinMax(MCInst &Inst, unsigned RegNo,
374 Inst.addOperand(MCOperand::createReg(Register));
379 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
388 Inst.addOperand(MCOperand::createReg(Register));
392 static DecodeStatus DecodeZK(MCInst &Inst, unsigned RegNo, uint64_t Address,
399 Inst.addOperand(MCOperand::createReg(Register));
403 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
410 Inst.addOperand(MCOperand::createReg(Register));
415 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
420 Inst.addOperand(MCOperand::createImm(RegMask));
436 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
442 Inst.addOperand(
447 static DecodeStatus DecodePPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
454 Inst.addOperand(MCOperand::createReg(Register));
458 static DecodeStatus DecodeFixedPointScaleImm32(MCInst &Inst, unsigned Imm,
463 Inst.addOperand(MCOperand::createImm(64 - Imm));
467 static DecodeStatus DecodeFixedPointScaleImm64(MCInst &Inst, unsigned Imm,
470 Inst.addOperand(MCOperand::createImm(64 - Imm));
474 static DecodeStatus DecodePCRelLabel16(MCInst &Inst, unsigned Imm,
483 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal << 2), Addr,
485 Inst.addOperand(MCOperand::createImm(ImmVal));
489 static DecodeStatus DecodePCRelLabel19(MCInst &Inst, unsigned Imm,
499 Inst, ImmVal * 4, Addr, Inst.getOpcode() != AArch64::LDRXl, 0, 0, 4))
500 Inst.addOperand(MCOperand::createImm(ImmVal));
504 static DecodeStatus DecodePCRelLabel9(MCInst &Inst, unsigned Imm, uint64_t Addr,
512 if (!Decoder->tryAddingSymbolicOperand(Inst, (ImmVal * 4), Addr,
514 Inst.addOperand(MCOperand::createImm(ImmVal));
518 static DecodeStatus DecodeMemExtend(MCInst &Inst, unsigned Imm,
521 Inst.addOperand(MCOperand::createImm((Imm >> 1) & 1));
522 Inst.addOperand(MCOperand::createImm(Imm & 1));
526 static DecodeStatus DecodeMRSSystemRegister(MCInst &Inst, unsigned Imm,
529 Inst.addOperand(MCOperand::createImm(Imm));
536 static DecodeStatus DecodeMSRSystemRegister(MCInst &Inst, unsigned Imm,
539 Inst.addOperand(MCOperand::createImm(Imm));
544 static DecodeStatus DecodeFMOVLaneInstruction(MCInst &Inst, unsigned Insn,
555 Inst, Rd, Address, Decoder);
557 Inst, Rn, Address, Decoder);
560 Inst, Rd, Address, Decoder);
562 Inst, Rn, Address, Decoder);
566 Inst.addOperand(MCOperand::createImm(1));
571 static DecodeStatus DecodeVecShiftRImm(MCInst &Inst, unsigned Imm,
573 Inst.addOperand(MCOperand::createImm(Add - Imm));
577 static DecodeStatus DecodeVecShiftLImm(MCInst &Inst, unsigned Imm,
579 Inst.addOperand(MCOperand::createImm((Imm + Add) & (Add - 1)));
583 static DecodeStatus DecodeVecShiftR64Imm(MCInst &Inst, unsigned Imm,
586 return DecodeVecShiftRImm(Inst, Imm, 64);
589 static DecodeStatus DecodeVecShiftR64ImmNarrow(MCInst &Inst, unsigned Imm,
592 return DecodeVecShiftRImm(Inst, Imm | 0x20, 64);
595 static DecodeStatus DecodeVecShiftR32Imm(MCInst &Inst, unsigned Imm,
598 return DecodeVecShiftRImm(Inst, Imm, 32);
601 static DecodeStatus DecodeVecShiftR32ImmNarrow(MCInst &Inst, unsigned Imm,
604 return DecodeVecShiftRImm(Inst, Imm | 0x10, 32);
607 static DecodeStatus DecodeVecShiftR16Imm(MCInst &Inst, unsigned Imm,
610 return DecodeVecShiftRImm(Inst, Imm, 16);
613 static DecodeStatus DecodeVecShiftR16ImmNarrow(MCInst &Inst, unsigned Imm,
616 return DecodeVecShiftRImm(Inst, Imm | 0x8, 16);
619 static DecodeStatus DecodeVecShiftR8Imm(MCInst &Inst, unsigned Imm,
622 return DecodeVecShiftRImm(Inst, Imm, 8);
625 static DecodeStatus DecodeVecShiftL64Imm(MCInst &Inst, unsigned Imm,
628 return DecodeVecShiftLImm(Inst, Imm, 64);
631 static DecodeStatus DecodeVecShiftL32Imm(MCInst &Inst, unsigned Imm,
634 return DecodeVecShiftLImm(Inst, Imm, 32);
637 static DecodeStatus DecodeVecShiftL16Imm(MCInst &Inst, unsigned Imm,
640 return DecodeVecShiftLImm(Inst, Imm, 16);
643 static DecodeStatus DecodeVecShiftL8Imm(MCInst &Inst, unsigned Imm,
646 return DecodeVecShiftLImm(Inst, Imm, 8);
650 DecodeThreeAddrSRegInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
658 switch (Inst.getOpcode()) {
680 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
682 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
684 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
704 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
706 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
708 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
713 Inst.addOperand(MCOperand::createImm(shift));
717 static DecodeStatus DecodeMoveImmInstruction(MCInst &Inst, uint32_t insn,
724 switch (Inst.getOpcode()) {
732 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
738 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
743 if (Inst.getOpcode() == AArch64::MOVKWi ||
744 Inst.getOpcode() == AArch64::MOVKXi)
745 Inst.addOperand(Inst.getOperand(0));
747 Inst.addOperand(MCOperand::createImm(imm));
748 Inst.addOperand(MCOperand::createImm(shift));
753 DecodeUnsignedLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
759 switch (Inst.getOpcode()) {
764 Inst.addOperand(MCOperand::createImm(Rt));
774 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
782 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
787 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
792 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
797 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
802 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
807 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
812 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
814 if (!Decoder->tryAddingSymbolicOperand(Inst, offset, Addr, Fail, 0, 0, 4))
815 Inst.addOperand(MCOperand::createImm(offset));
819 static DecodeStatus DecodeSignedLdStInstruction(MCInst &Inst, uint32_t insn,
832 switch (Inst.getOpcode()) {
881 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
886 switch (Inst.getOpcode()) {
891 Inst.addOperand(MCOperand::createImm(Rt));
933 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
961 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
970 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
979 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
988 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
997 DecodeSimpleRegisterClass<AArch64::FPR16RegClassID, 0, 32>(Inst, Rt, Addr,
1006 DecodeSimpleRegisterClass<AArch64::FPR8RegClassID, 0, 32>(Inst, Rt, Addr,
1011 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1013 Inst.addOperand(MCOperand::createImm(offset));
1027 DecodeExclusiveLdStInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1034 unsigned Opcode = Inst.getOpcode();
1044 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1065 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1070 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1079 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1084 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1089 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1091 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1096 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rs, Addr,
1101 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1103 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1108 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1120 static DecodeStatus DecodePairLdStInstruction(MCInst &Inst, uint32_t insn,
1134 unsigned Opcode = Inst.getOpcode();
1173 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1205 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1207 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1220 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1222 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1241 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt, Addr,
1243 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rt2, Addr,
1254 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1256 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rt2, Addr,
1267 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1269 DecodeSimpleRegisterClass<AArch64::FPR32RegClassID, 0, 32>(Inst, Rt2, Addr,
1274 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1276 Inst.addOperand(MCOperand::createImm(offset));
1290 static DecodeStatus DecodeAuthLoadInstruction(MCInst &Inst, uint32_t insn,
1299 switch (Inst.getOpcode()) {
1305 Inst, Rn /* writeback register */, Addr, Decoder);
1312 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1314 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1316 DecodeSImm<10>(Inst, offset, Addr, Decoder);
1325 static DecodeStatus DecodeAddSubERegInstruction(MCInst &Inst, uint32_t insn,
1337 switch (Inst.getOpcode()) {
1342 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rd, Addr,
1344 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1346 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1351 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1353 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1355 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1360 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1362 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1364 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1369 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1371 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1373 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1378 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rd, Addr,
1380 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1382 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1387 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1389 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1391 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1396 Inst.addOperand(MCOperand::createImm(extend));
1400 static DecodeStatus DecodeLogicalImmInstruction(MCInst &Inst, uint32_t insn,
1409 if (Inst.getOpcode() == AArch64::ANDSXri)
1410 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1414 Inst, Rd, Addr, Decoder);
1415 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rn, Addr,
1421 if (Inst.getOpcode() == AArch64::ANDSWri)
1422 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1426 Inst, Rd, Addr, Decoder);
1427 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rn, Addr,
1433 Inst.addOperand(MCOperand::createImm(imm));
1437 static DecodeStatus DecodeModImmInstruction(MCInst &Inst, uint32_t insn,
1445 if (Inst.getOpcode() == AArch64::MOVID)
1446 DecodeSimpleRegisterClass<AArch64::FPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1449 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1452 Inst.addOperand(MCOperand::createImm(imm));
1454 switch (Inst.getOpcode()) {
1465 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1471 Inst.addOperand(MCOperand::createImm((cmode & 1) ? 0x110 : 0x108));
1478 static DecodeStatus DecodeModImmTiedInstruction(MCInst &Inst, uint32_t insn,
1487 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1489 DecodeSimpleRegisterClass<AArch64::FPR128RegClassID, 0, 32>(Inst, Rd, Addr,
1492 Inst.addOperand(MCOperand::createImm(imm));
1493 Inst.addOperand(MCOperand::createImm((cmode & 6) << 2));
1498 static DecodeStatus DecodeAdrInstruction(MCInst &Inst, uint32_t insn,
1509 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1511 if (!Decoder->tryAddingSymbolicOperand(Inst, imm, Addr, Fail, 0, 0, 4))
1512 Inst.addOperand(MCOperand::createImm(imm));
1517 static DecodeStatus DecodeAddSubImmShift(MCInst &Inst, uint32_t insn,
1535 Inst, Rd, Addr, Decoder);
1537 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rd, Addr,
1539 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1544 Inst, Rd, Addr, Decoder);
1546 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rd, Addr,
1548 DecodeSimpleRegisterClass<AArch64::GPR32spRegClassID, 0, 32>(Inst, Rn, Addr,
1552 if (!Decoder->tryAddingSymbolicOperand(Inst, Imm, Addr, Fail, 0, 0, 4))
1553 Inst.addOperand(MCOperand::createImm(ImmVal));
1554 Inst.addOperand(MCOperand::createImm(12 * ShifterVal));
1558 static DecodeStatus DecodeUnconditionalBranch(MCInst &Inst, uint32_t insn,
1567 if (!Decoder->tryAddingSymbolicOperand(Inst, imm * 4, Addr, true, 0, 0, 4))
1568 Inst.addOperand(MCOperand::createImm(imm));
1580 DecodeSystemPStateImm0_15Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1590 Inst.addOperand(MCOperand::createImm(pstate_field));
1591 Inst.addOperand(MCOperand::createImm(imm));
1601 DecodeSystemPStateImm0_1Instruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1612 Inst.addOperand(MCOperand::createImm(pstate_field));
1613 Inst.addOperand(MCOperand::createImm(imm));
1622 static DecodeStatus DecodeTestAndBranch(MCInst &Inst, uint32_t insn,
1635 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rt, Addr,
1638 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1640 Inst.addOperand(MCOperand::createImm(bit));
1641 if (!Decoder->tryAddingSymbolicOperand(Inst, dst * 4, Addr, true, 0, 0, 4))
1642 Inst.addOperand(MCOperand::createImm(dst));
1648 DecodeGPRSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegClassID,
1656 Inst.addOperand(MCOperand::createReg(Reg));
1661 DecodeWSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1664 Inst, AArch64::WSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1668 DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr,
1671 Inst, AArch64::XSeqPairsClassRegClassID, RegNo, Addr, Decoder);
1674 static DecodeStatus DecodeSyspXzrInstruction(MCInst &Inst, uint32_t insn,
1685 Inst.addOperand(MCOperand::createImm(op1));
1686 Inst.addOperand(MCOperand::createImm(CRn));
1687 Inst.addOperand(MCOperand::createImm(CRm));
1688 Inst.addOperand(MCOperand::createImm(op2));
1689 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rt, Addr,
1696 DecodeSVELogicalImmInstruction(MCInst &Inst, uint32_t insn, uint64_t Addr,
1704 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1706 if (Inst.getOpcode() != AArch64::DUPM_ZI)
1707 DecodeSimpleRegisterClass<AArch64::ZPRRegClassID, 0, 32>(Inst, Zdn, Addr,
1709 Inst.addOperand(MCOperand::createImm(imm));
1714 static DecodeStatus DecodeSImm(MCInst &Inst, uint64_t Imm, uint64_t Address,
1723 Inst.addOperand(MCOperand::createImm(Imm));
1729 static DecodeStatus DecodeImm8OptLsl(MCInst &Inst, unsigned Imm, uint64_t Addr,
1735 Inst.addOperand(MCOperand::createImm(Val));
1736 Inst.addOperand(MCOperand::createImm(Shift));
1741 static DecodeStatus DecodeSVEIncDecImm(MCInst &Inst, unsigned Imm,
1744 Inst.addOperand(MCOperand::createImm(Imm + 1));
1748 static DecodeStatus DecodeSVCROp(MCInst &Inst, unsigned Imm, uint64_t Address,
1751 Inst.addOperand(MCOperand::createImm(Imm));
1757 static DecodeStatus DecodeCPYMemOpInstruction(MCInst &Inst, uint32_t insn,
1772 Inst, Rd, Addr, Decoder) ||
1774 Inst, Rs, Addr, Decoder) ||
1776 Inst, Rn, Addr, Decoder) ||
1778 Inst, Rd, Addr, Decoder) ||
1780 Inst, Rs, Addr, Decoder) ||
1782 Inst, Rn, Addr, Decoder))
1788 static DecodeStatus DecodeSETMemOpInstruction(MCInst &Inst, uint32_t insn,
1803 Inst, Rd, Addr, Decoder) ||
1805 Inst, Rn, Addr, Decoder) ||
1807 Inst, Rd, Addr, Decoder) ||
1809 Inst, Rn, Addr, Decoder) ||
1811 Inst, Rm, Addr, Decoder))
1817 static DecodeStatus DecodePRFMRegInstruction(MCInst &Inst, uint32_t insn,
1832 Inst.addOperand(MCOperand::createImm(Rt));
1833 DecodeSimpleRegisterClass<AArch64::GPR64spRegClassID, 0, 32>(Inst, Rn, Addr,
1836 switch (Inst.getOpcode()) {
1840 DecodeSimpleRegisterClass<AArch64::GPR32RegClassID, 0, 32>(Inst, Rm, Addr,
1844 DecodeSimpleRegisterClass<AArch64::GPR64RegClassID, 0, 32>(Inst, Rm, Addr,
1849 DecodeMemExtend(Inst, (Extend << 1) | Shift, Addr, Decoder);