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Revision tags: llvmorg-21-init, llvmorg-19.1.7, llvmorg-19.1.6, llvmorg-19.1.5, llvmorg-19.1.4 |
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ed8019d9 |
| 18-Nov-2024 |
Kazu Hirata <kazu@google.com> |
[Target] Remove unused includes (NFC) (#116577)
Identified with misc-include-cleaner.
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Revision tags: llvmorg-19.1.3, llvmorg-19.1.2, llvmorg-19.1.1, llvmorg-19.1.0, llvmorg-19.1.0-rc4, llvmorg-19.1.0-rc3, llvmorg-19.1.0-rc2, llvmorg-19.1.0-rc1, llvmorg-20-init, llvmorg-18.1.8, llvmorg-18.1.7, llvmorg-18.1.6, llvmorg-18.1.5, llvmorg-18.1.4, llvmorg-18.1.3, llvmorg-18.1.2, llvmorg-18.1.1, llvmorg-18.1.0, llvmorg-18.1.0-rc4, llvmorg-18.1.0-rc3, llvmorg-18.1.0-rc2, llvmorg-18.1.0-rc1, llvmorg-19-init, llvmorg-17.0.6, llvmorg-17.0.5, llvmorg-17.0.4, llvmorg-17.0.3, llvmorg-17.0.2, llvmorg-17.0.1, llvmorg-17.0.0, llvmorg-17.0.0-rc4, llvmorg-17.0.0-rc3, llvmorg-17.0.0-rc2, llvmorg-17.0.0-rc1, llvmorg-18-init |
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d6675b6a |
| 24-Jul-2023 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Add definition for LVZ/LBT instructions
This patch defines the `LVZ` and `LBT` extension instructions, which
provide enough definitions for llvm-mc and llvm-objdump to correctly
handle t
[LoongArch] Add definition for LVZ/LBT instructions
This patch defines the `LVZ` and `LBT` extension instructions, which
provide enough definitions for llvm-mc and llvm-objdump to correctly
handle these instructions.
It also defines the `SCR` (Scratchpad Register) register class, which
are used by the `LBT` extension instructions.
Reviewed By: SixWeining, xen0n
Differential Revision: https://reviews.llvm.org/D155917
show more ...
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f3d18b9d |
| 07-Jul-2023 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Add definition for LASX instructions
This patch adds the definition of the LASX instructions, providing
support only for assembly and disassembly, similar to D154183.
Depends on D154183
[LoongArch] Add definition for LASX instructions
This patch adds the definition of the LASX instructions, providing
support only for assembly and disassembly, similar to D154183.
Depends on D154183
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D154195
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1aa3b64e |
| 07-Jul-2023 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Add definition for LSX instructions
This patch adds the definition for the `LSX` registers and instructions.
It also adds handling for new immediate operands in the AsmParser. This
patch
[LoongArch] Add definition for LSX instructions
This patch adds the definition for the `LSX` registers and instructions.
It also adds handling for new immediate operands in the AsmParser. This
patch ensures that llvm-mc and llvm-objdump correctly handle the `LSX`
instructions.
We expand those pseudo-instructions `vrepli.{b,h,w,d}` in the
MCCodeEmitter. This increases the readability of the output when
generating assembly files.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D154183
show more ...
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Revision tags: llvmorg-16.0.6, llvmorg-16.0.5, llvmorg-16.0.4, llvmorg-16.0.3, llvmorg-16.0.2, llvmorg-16.0.1, llvmorg-16.0.0, llvmorg-16.0.0-rc4, llvmorg-16.0.0-rc3, llvmorg-16.0.0-rc2, llvmorg-16.0.0-rc1, llvmorg-17-init, llvmorg-15.0.7 |
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f292d53c |
| 11-Jan-2023 |
wanglei <wanglei@loongson.cn> |
[LoongArch] Fix undefined behavior: left shift of negative value
Fix undefined behavior in `decodeSImmOperand` where we were left shifting
a signed value.
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Revision tags: llvmorg-15.0.6, llvmorg-15.0.5, llvmorg-15.0.4, llvmorg-15.0.3, working, llvmorg-15.0.2, llvmorg-15.0.1, llvmorg-15.0.0, llvmorg-15.0.0-rc3, llvmorg-15.0.0-rc2, llvmorg-15.0.0-rc1, llvmorg-16-init |
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904a87ac |
| 26-Jul-2022 |
Weining Lu <luweining@loongson.cn> |
[LoongArch] Use `end namespace xxx` style comment. NFC
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Revision tags: llvmorg-14.0.6, llvmorg-14.0.5, llvmorg-14.0.4 |
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c644488a |
| 15-May-2022 |
Sheng <ox59616e@gmail.com> |
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
The name `MCFixedLenDisassembler.h` is out of date after D120958.
Rename it as `MCDecoderOps.h` to reflect the change.
Reviewed By: myhsu
Dif
Rename `MCFixedLenDisassembler.h` as `MCDecoderOps.h`
The name `MCFixedLenDisassembler.h` is out of date after D120958.
Rename it as `MCDecoderOps.h` to reflect the change.
Reviewed By: myhsu
Differential Revision: https://reviews.llvm.org/D124987
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Revision tags: llvmorg-14.0.3, llvmorg-14.0.2, llvmorg-14.0.1 |
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3a49ad71 |
| 29-Mar-2022 |
Weining Lu <luweining@loongson.cn> |
[LoongArch] Add basic floating-point instructions definition
These instructions are added by following the `LoongArch Reference
Manual Volume 1: Basic Architecture Version 1.00`.
Differential Revis
[LoongArch] Add basic floating-point instructions definition
These instructions are added by following the `LoongArch Reference
Manual Volume 1: Basic Architecture Version 1.00`.
Differential Revision: https://reviews.llvm.org/D123988
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4ae9745a |
| 21-Mar-2022 |
Maksim Panchenko <maks@fb.com> |
[Disassember][NFCI] Use strong type for instruction decoder
All LLVM backends use MCDisassembler as a base class for their
instruction decoders. Use "const MCDisassembler *" for the decoder
instead
[Disassember][NFCI] Use strong type for instruction decoder
All LLVM backends use MCDisassembler as a base class for their
instruction decoders. Use "const MCDisassembler *" for the decoder
instead of "const void *". Remove unnecessary static casts.
Reviewed By: skan
Differential Revision: https://reviews.llvm.org/D122245
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Revision tags: llvmorg-14.0.0, llvmorg-14.0.0-rc4, llvmorg-14.0.0-rc3 |
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7898587e |
| 10-Mar-2022 |
Weining Lu <luweining@loongson.cn> |
[LoongArch] Add basic support to Disassembler
With the addition of disassembler now we can do instructions 'round-trip' test
that assembles `.s` to obj with `llvm-mc` and disassembles it with `llvm-
[LoongArch] Add basic support to Disassembler
With the addition of disassembler now we can do instructions 'round-trip' test
that assembles `.s` to obj with `llvm-mc` and disassembles it with `llvm-objdump`
to check instruction mnemonics.
Reviewed By: xen0n, MaskRay
Differential Revision: https://reviews.llvm.org/D120477
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