Lines Matching defs:Inst
176 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
179 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
182 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
185 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
189 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
192 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
195 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
199 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
201 static DecodeStatus DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo,
205 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
207 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
210 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
213 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
216 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
220 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
222 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
225 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
228 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
231 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
234 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
237 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
240 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
243 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
246 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
249 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
252 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
255 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
259 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
262 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
265 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
268 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
271 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
274 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
278 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
281 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
285 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
287 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
290 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
293 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
296 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
299 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
304 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
307 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
310 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
313 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
316 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
319 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
322 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
325 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
328 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
331 static DecodeStatus DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn,
334 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
337 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
340 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
343 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
346 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
349 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
352 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
355 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
358 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
361 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
364 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
367 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
370 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
373 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
376 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
379 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
382 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
385 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Val,
388 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Val,
391 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
394 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
397 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
400 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
403 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
406 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
409 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
412 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
415 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
419 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
422 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
425 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
428 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
431 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, uint64_t Address,
433 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn,
436 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
439 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
442 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
445 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
448 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
451 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
454 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
456 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
458 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
460 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
462 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
464 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
466 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
468 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
470 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
472 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
474 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
476 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
478 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
480 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Insn,
484 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Val, uint64_t Address,
487 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
490 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
493 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
496 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
499 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
502 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
505 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
508 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
511 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
514 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
517 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
520 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
523 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
525 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
528 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
530 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
532 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
535 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
538 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
541 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
544 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
546 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
550 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
554 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
557 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
560 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
563 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
566 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
569 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
572 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
575 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
578 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
581 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
583 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
586 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
589 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, uint64_t Address,
591 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
594 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
597 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, uint64_t Address,
599 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
602 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
606 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
608 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
611 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
616 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned val,
619 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned val,
622 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
625 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
627 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
630 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
632 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
635 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned Val,
638 static DecodeStatus DecodeVpredNOperand(MCInst &Inst, unsigned Val,
642 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
645 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
648 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
651 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
654 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Insn,
658 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
662 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
666 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
670 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
675 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
677 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
680 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
683 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
686 typedef DecodeStatus OperandDecoder(MCInst &Inst, unsigned Val,
690 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
692 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
694 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
698 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
700 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
703 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
1297 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1304 Inst.addOperand(MCOperand::createReg(Register));
1308 static DecodeStatus DecodeCLRMGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1318 Inst.addOperand(MCOperand::createReg(Register));
1322 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
1330 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1335 static DecodeStatus DecodeGPRnospRegisterClass(MCInst &Inst, unsigned RegNo,
1343 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1349 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1355 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
1359 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1364 DecodeGPRwithZRRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1370 Inst.addOperand(MCOperand::createReg(ARM::ZR));
1377 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1382 DecodeGPRwithZRnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1387 Check(S, DecodeGPRwithZRRegisterClass(Inst, RegNo, Address, Decoder));
1391 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1396 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
1404 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
1418 Inst.addOperand(MCOperand::createReg(RegisterPair));
1423 DecodeGPRPairnospRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1429 Inst.addOperand(MCOperand::createReg(RegisterPair));
1436 static DecodeStatus DecodeGPRspRegisterClass(MCInst &Inst, unsigned RegNo,
1443 Inst.addOperand(MCOperand::createReg(Register));
1447 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1474 Inst.addOperand(MCOperand::createReg(Register));
1478 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
1489 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
1504 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1511 Inst.addOperand(MCOperand::createReg(Register));
1515 static DecodeStatus DecodeHPRRegisterClass(MCInst &Inst, unsigned RegNo,
1518 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1533 static bool PermitsD32(const MCInst &Inst, const MCDisassembler *Decoder) {
1534 if (Inst.getOpcode() == ARM::VSCCLRMD || Inst.getOpcode() == ARM::VSCCLRMS)
1541 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
1544 if (RegNo > (PermitsD32(Inst, Decoder) ? 31u : 15u))
1548 Inst.addOperand(MCOperand::createReg(Register));
1552 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1557 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1560 static DecodeStatus DecodeSPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
1565 return DecodeSPRRegisterClass(Inst, RegNo, Address, Decoder);
1568 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
1573 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
1583 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
1591 Inst.addOperand(MCOperand::createReg(Register));
1604 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
1611 Inst.addOperand(MCOperand::createReg(Register));
1627 DecodeDPairSpacedRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1633 Inst.addOperand(MCOperand::createReg(Register));
1637 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
1643 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1647 if (Val != ARMCC::AL && !MCII->get(Inst.getOpcode()).isPredicable())
1649 Inst.addOperand(MCOperand::createImm(Val));
1651 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
1653 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1657 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
1661 Inst.addOperand(MCOperand::createReg(ARM::CPSR));
1663 Inst.addOperand(MCOperand::createReg(ARM::NoRegister));
1667 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
1677 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
1700 Inst.addOperand(MCOperand::createImm(Op));
1705 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
1715 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
1717 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
1736 Inst.addOperand(MCOperand::createImm(Shift));
1741 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
1749 switch (Inst.getOpcode()) {
1761 WritebackReg = Inst.getOperand(0).getReg();
1773 if (!Check(S, DecodeCLRMGPRRegisterClass(Inst, i, Address, Decoder))) {
1777 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
1780 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg())
1789 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
1804 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
1807 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1814 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
1823 unsigned MaxReg = PermitsD32(Inst, Decoder) ? 32 : 16;
1831 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
1834 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
1841 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
1865 Inst.addOperand(MCOperand::createImm(~(msb_mask ^ lsb_mask)));
1869 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
1883 switch (Inst.getOpcode()) {
1955 Inst.addOperand(MCOperand::createImm(coproc));
1956 Inst.addOperand(MCOperand::createImm(CRd));
1957 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
1960 switch (Inst.getOpcode()) {
1994 Inst.addOperand(MCOperand::createImm(imm));
2017 Inst.addOperand(MCOperand::createImm(imm));
2021 switch (Inst.getOpcode()) {
2038 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2049 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
2063 switch (Inst.getOpcode()) {
2072 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2079 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2083 switch (Inst.getOpcode()) {
2092 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2099 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2117 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2141 Inst.addOperand(MCOperand::createImm(imm));
2143 Inst.addOperand(MCOperand::createReg(0));
2145 Inst.addOperand(MCOperand::createImm(tmp));
2148 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2154 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
2184 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2193 Inst.addOperand(MCOperand::createImm(shift));
2198 static DecodeStatus DecodeTSBInstruction(MCInst &Inst, unsigned Insn,
2201 if (Inst.getOpcode() != ARM::TSB && Inst.getOpcode() != ARM::t2TSB)
2207 Inst.addOperand(MCOperand::createImm(ARM_TSB::CSYNC));
2211 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
2230 switch (Inst.getOpcode()) {
2242 switch (Inst.getOpcode()) {
2329 switch (Inst.getOpcode()) {
2336 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2344 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
2346 switch (Inst.getOpcode()) {
2353 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
2362 switch (Inst.getOpcode()) {
2377 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2385 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2389 Inst.addOperand(MCOperand::createReg(0));
2390 Inst.addOperand(MCOperand::createImm(U | (imm << 4) | Rm));
2392 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2394 Inst.addOperand(MCOperand::createImm(U));
2397 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2403 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
2426 Inst.addOperand(MCOperand::createImm(mode));
2427 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2433 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
2444 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2446 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2448 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2450 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2452 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2458 DecodeMemMultipleWritebackInstruction(MCInst &Inst, unsigned Insn,
2469 switch (Inst.getOpcode()) {
2471 Inst.setOpcode(ARM::RFEDA);
2474 Inst.setOpcode(ARM::RFEDA_UPD);
2477 Inst.setOpcode(ARM::RFEDB);
2480 Inst.setOpcode(ARM::RFEDB_UPD);
2483 Inst.setOpcode(ARM::RFEIA);
2486 Inst.setOpcode(ARM::RFEIA_UPD);
2489 Inst.setOpcode(ARM::RFEIB);
2492 Inst.setOpcode(ARM::RFEIB_UPD);
2495 Inst.setOpcode(ARM::SRSDA);
2498 Inst.setOpcode(ARM::SRSDA_UPD);
2501 Inst.setOpcode(ARM::SRSDB);
2504 Inst.setOpcode(ARM::SRSDB_UPD);
2507 Inst.setOpcode(ARM::SRSIA);
2510 Inst.setOpcode(ARM::SRSIA_UPD);
2513 Inst.setOpcode(ARM::SRSIB);
2516 Inst.setOpcode(ARM::SRSIB_UPD);
2529 Inst.addOperand(
2534 return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
2537 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2539 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2541 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2543 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
2550 static DecodeStatus DecodeHINTInstruction(MCInst &Inst, unsigned Insn,
2560 Inst.addOperand(MCOperand::createImm(imm8));
2562 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2573 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
2598 Inst.setOpcode(ARM::CPS3p);
2599 Inst.addOperand(MCOperand::createImm(imod));
2600 Inst.addOperand(MCOperand::createImm(iflags));
2601 Inst.addOperand(MCOperand::createImm(mode));
2603 Inst.setOpcode(ARM::CPS2p);
2604 Inst.addOperand(MCOperand::createImm(imod));
2605 Inst.addOperand(MCOperand::createImm(iflags));
2608 Inst.setOpcode(ARM::CPS1p);
2609 Inst.addOperand(MCOperand::createImm(mode));
2613 Inst.setOpcode(ARM::CPS1p);
2614 Inst.addOperand(MCOperand::createImm(mode));
2621 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
2639 Inst.setOpcode(ARM::t2CPS3p);
2640 Inst.addOperand(MCOperand::createImm(imod));
2641 Inst.addOperand(MCOperand::createImm(iflags));
2642 Inst.addOperand(MCOperand::createImm(mode));
2644 Inst.setOpcode(ARM::t2CPS2p);
2645 Inst.addOperand(MCOperand::createImm(imod));
2646 Inst.addOperand(MCOperand::createImm(iflags));
2649 Inst.setOpcode(ARM::t2CPS1p);
2650 Inst.addOperand(MCOperand::createImm(mode));
2657 Inst.setOpcode(ARM::t2HINT);
2658 Inst.addOperand(MCOperand::createImm(imm));
2665 DecodeT2HintSpaceInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
2681 Inst.setOpcode(Opcode);
2683 Inst.addOperand(MCOperand::createImm(imm));
2689 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
2702 if (Inst.getOpcode() == ARM::t2MOVTi16)
2703 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2705 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
2708 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2709 Inst.addOperand(MCOperand::createImm(imm));
2714 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
2726 if (Inst.getOpcode() == ARM::MOVTi16)
2727 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2730 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2733 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
2734 Inst.addOperand(MCOperand::createImm(imm));
2736 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2742 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
2754 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
2756 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
2758 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
2760 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
2762 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
2765 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2771 static DecodeStatus DecodeTSTInstruction(MCInst &Inst, unsigned Insn,
2781 return DecodeSETPANInstruction(Inst, Insn, Address, Decoder);
2783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2787 if (!Check(S, DecodePredicateOperand(Inst, Pred, Address, Decoder)))
2793 static DecodeStatus DecodeSETPANInstruction(MCInst &Inst, unsigned Insn,
2816 Inst.setOpcode(ARM::SETPAN);
2817 Inst.addOperand(MCOperand::createImm(Imm));
2822 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
2831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2836 Inst.addOperand(MCOperand::createImm(imm));
2843 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
2853 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2857 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
2859 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
2864 static DecodeStatus DecodeAddrMode5FP16Operand(MCInst &Inst, unsigned Val,
2874 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
2878 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::add, imm)));
2880 Inst.addOperand(MCOperand::createImm(ARM_AM::getAM5FP16Opc(ARM_AM::sub, imm)));
2885 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
2888 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
2891 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
2912 true, 4, Inst, Decoder))
2913 Inst.addOperand(MCOperand::createImm(imm32));
2918 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
2927 Inst.setOpcode(ARM::BLXi);
2930 true, 4, Inst, Decoder))
2931 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2936 true, 4, Inst, Decoder))
2937 Inst.addOperand(MCOperand::createImm(SignExtend32<26>(imm)));
2941 if (Inst.getOpcode() != ARM::BL)
2942 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
2948 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
2959 Inst.addOperand(MCOperand::createImm(0));
2961 Inst.addOperand(MCOperand::createImm(4 << align));
2966 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
2979 switch (Inst.getOpcode()) {
2989 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3001 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3005 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3010 switch (Inst.getOpcode()) {
3023 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3038 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3046 switch(Inst.getOpcode()) {
3059 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3074 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3082 switch (Inst.getOpcode()) {
3089 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3098 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3106 switch (Inst.getOpcode()) {
3157 Inst.addOperand(MCOperand::createImm(0));
3171 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3179 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3183 switch (Inst.getOpcode()) {
3192 Inst.addOperand(MCOperand::createReg(0));
3225 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3243 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
3253 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3254 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3257 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
3269 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3270 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3273 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
3283 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3284 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3287 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
3294 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
3295 : DecodeVSTInstruction(Inst, Insn, Address, Decoder);
3298 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
3311 switch (Inst.getOpcode()) {
3364 Inst.addOperand(MCOperand::createImm(0));
3378 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
3386 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
3390 switch (Inst.getOpcode()) {
3393 Inst.addOperand(MCOperand::createReg(0));
3395 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3428 switch (Inst.getOpcode()) {
3450 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3462 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3466 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3471 switch (Inst.getOpcode()) {
3484 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
3499 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3507 switch (Inst.getOpcode()) {
3520 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
3535 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
3543 switch (Inst.getOpcode()) {
3550 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
3559 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
3569 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
3585 switch (Inst.getOpcode()) {
3590 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3594 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3599 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3603 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3605 Inst.addOperand(MCOperand::createImm(align));
3611 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3617 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
3630 switch (Inst.getOpcode()) {
3635 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
3642 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
3646 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3652 Inst.addOperand(MCOperand::createImm(0));
3654 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3656 Inst.addOperand(MCOperand::createImm(align));
3659 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3666 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
3677 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3679 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3681 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3684 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3688 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3690 Inst.addOperand(MCOperand::createImm(0));
3693 Inst.addOperand(MCOperand::createReg(0));
3695 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3702 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
3728 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3730 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
3732 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
3734 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
3737 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3741 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
3743 Inst.addOperand(MCOperand::createImm(align));
3746 Inst.addOperand(MCOperand::createReg(0));
3748 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
3755 static DecodeStatus DecodeVMOVModImmInstruction(MCInst &Inst, unsigned Insn,
3770 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3773 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3777 Inst.addOperand(MCOperand::createImm(imm));
3779 switch (Inst.getOpcode()) {
3784 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3791 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3801 static DecodeStatus DecodeMVEModImmInstruction(MCInst &Inst, unsigned Insn,
3815 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3818 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3821 Inst.addOperand(MCOperand::createImm(imm));
3823 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
3824 Inst.addOperand(MCOperand::createReg(0));
3825 Inst.addOperand(MCOperand::createImm(0));
3830 static DecodeStatus DecodeMVEVADCInstruction(MCInst &Inst, unsigned Insn,
3837 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
3839 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3843 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
3847 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
3850 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
3851 Inst.addOperand(MCOperand::createImm(Qd));
3856 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
3867 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
3869 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3871 Inst.addOperand(MCOperand::createImm(8 << size));
3876 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
3879 Inst.addOperand(MCOperand::createImm(8 - Val));
3883 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
3886 Inst.addOperand(MCOperand::createImm(16 - Val));
3890 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
3893 Inst.addOperand(MCOperand::createImm(32 - Val));
3897 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
3900 Inst.addOperand(MCOperand::createImm(64 - Val));
3904 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
3917 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3920 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
3924 switch (Inst.getOpcode()) {
3927 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
3931 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
3935 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
3941 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
3949 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
3952 switch(Inst.getOpcode()) {
3958 Inst.addOperand(MCOperand::createReg(ARM::SP));
3962 Inst.addOperand(MCOperand::createImm(imm));
3966 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
3970 true, 2, Inst, Decoder))
3971 Inst.addOperand(MCOperand::createImm(SignExtend32<12>(Val << 1)));
3975 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
3979 true, 4, Inst, Decoder))
3980 Inst.addOperand(MCOperand::createImm(SignExtend32<21>(Val)));
3984 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
3988 true, 2, Inst, Decoder))
3989 Inst.addOperand(MCOperand::createImm(Val << 1));
3993 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
4001 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4003 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
4009 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
4017 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4019 Inst.addOperand(MCOperand::createImm(imm));
4024 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
4029 Inst.addOperand(MCOperand::createImm(imm));
4035 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
4038 Inst.addOperand(MCOperand::createReg(ARM::SP));
4039 Inst.addOperand(MCOperand::createImm(Val));
4044 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
4054 switch (Inst.getOpcode()) {
4065 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4067 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4069 Inst.addOperand(MCOperand::createImm(imm));
4074 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
4089 switch (Inst.getOpcode()) {
4091 Inst.setOpcode(ARM::t2LDRBpci);
4094 Inst.setOpcode(ARM::t2LDRHpci);
4097 Inst.setOpcode(ARM::t2LDRSHpci);
4100 Inst.setOpcode(ARM::t2LDRSBpci);
4103 Inst.setOpcode(ARM::t2LDRpci);
4106 Inst.setOpcode(ARM::t2PLDpci);
4109 Inst.setOpcode(ARM::t2PLIpci);
4115 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4119 switch (Inst.getOpcode()) {
4123 Inst.setOpcode(ARM::t2PLDWs);
4126 Inst.setOpcode(ARM::t2PLIs);
4133 switch (Inst.getOpcode()) {
4145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4152 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
4158 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
4178 switch (Inst.getOpcode()) {
4180 Inst.setOpcode(ARM::t2LDRpci);
4183 Inst.setOpcode(ARM::t2LDRBpci);
4186 Inst.setOpcode(ARM::t2LDRSBpci);
4189 Inst.setOpcode(ARM::t2LDRHpci);
4192 Inst.setOpcode(ARM::t2LDRSHpci);
4195 Inst.setOpcode(ARM::t2PLDpci);
4198 Inst.setOpcode(ARM::t2PLIpci);
4203 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4207 switch (Inst.getOpcode()) {
4212 Inst.setOpcode(ARM::t2PLDWi8);
4215 Inst.setOpcode(ARM::t2PLIi8);
4222 switch (Inst.getOpcode()) {
4234 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4238 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4243 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
4260 switch (Inst.getOpcode()) {
4262 Inst.setOpcode(ARM::t2LDRpci);
4265 Inst.setOpcode(ARM::t2LDRHpci);
4268 Inst.setOpcode(ARM::t2LDRSHpci);
4271 Inst.setOpcode(ARM::t2LDRBpci);
4274 Inst.setOpcode(ARM::t2LDRSBpci);
4277 Inst.setOpcode(ARM::t2PLDpci);
4280 Inst.setOpcode(ARM::t2PLIpci);
4285 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4289 switch (Inst.getOpcode()) {
4293 Inst.setOpcode(ARM::t2PLDWi12);
4296 Inst.setOpcode(ARM::t2PLIi12);
4303 switch (Inst.getOpcode()) {
4315 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4319 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
4324 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, uint64_t Address,
4334 switch (Inst.getOpcode()) {
4336 Inst.setOpcode(ARM::t2LDRpci);
4339 Inst.setOpcode(ARM::t2LDRBpci);
4342 Inst.setOpcode(ARM::t2LDRHpci);
4345 Inst.setOpcode(ARM::t2LDRSBpci);
4348 Inst.setOpcode(ARM::t2LDRSHpci);
4353 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4356 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
4358 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
4363 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
4378 switch (Inst.getOpcode()) {
4381 Inst.setOpcode(ARM::t2PLDpci);
4384 Inst.setOpcode(ARM::t2PLIpci);
4393 switch(Inst.getOpcode()) {
4401 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4412 Inst.addOperand(MCOperand::createImm(imm));
4417 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, uint64_t Address,
4420 Inst.addOperand(MCOperand::createImm(INT32_MIN));
4425 Inst.addOperand(MCOperand::createImm(imm * 4));
4431 static DecodeStatus DecodeT2Imm7S4(MCInst &Inst, unsigned Val, uint64_t Address,
4434 Inst.addOperand(MCOperand::createImm(INT32_MIN));
4440 Inst.addOperand(MCOperand::createImm(imm * 4));
4446 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
4454 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4456 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
4462 static DecodeStatus DecodeT2AddrModeImm7s4(MCInst &Inst, unsigned Val,
4470 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4472 if (!Check(S, DecodeT2Imm7S4(Inst, imm, Address, Decoder)))
4478 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst, unsigned Val,
4486 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4489 Inst.addOperand(MCOperand::createImm(imm));
4494 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, uint64_t Address,
4501 Inst.addOperand(MCOperand::createImm(imm));
4507 static DecodeStatus DecodeT2Imm7(MCInst &Inst, unsigned Val, uint64_t Address,
4516 Inst.addOperand(MCOperand::createImm(imm));
4521 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
4530 switch (Inst.getOpcode()) {
4545 switch (Inst.getOpcode()) {
4560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4562 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
4569 static DecodeStatus DecodeTAddrModeImm7(MCInst &Inst, unsigned Val,
4577 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
4579 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4586 static DecodeStatus DecodeT2AddrModeImm7(MCInst &Inst, unsigned Val,
4594 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
4596 } else if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4598 if (!Check(S, DecodeT2Imm7<shift>(Inst, imm, Address, Decoder)))
4604 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
4617 switch (Inst.getOpcode()) {
4620 Inst.setOpcode(ARM::t2LDRpci);
4624 Inst.setOpcode(ARM::t2LDRBpci);
4628 Inst.setOpcode(ARM::t2LDRHpci);
4633 Inst.setOpcode(ARM::t2PLIpci);
4635 Inst.setOpcode(ARM::t2LDRSBpci);
4639 Inst.setOpcode(ARM::t2LDRSHpci);
4644 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
4648 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4652 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
4656 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4660 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
4666 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
4675 switch (Inst.getOpcode()) {
4686 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4688 Inst.addOperand(MCOperand::createImm(imm));
4693 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
4698 Inst.addOperand(MCOperand::createReg(ARM::SP));
4699 Inst.addOperand(MCOperand::createReg(ARM::SP));
4700 Inst.addOperand(MCOperand::createImm(imm));
4705 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
4710 if (Inst.getOpcode() == ARM::tADDrSP) {
4714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4716 Inst.addOperand(MCOperand::createReg(ARM::SP));
4717 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
4719 } else if (Inst.getOpcode() == ARM::tADDspr) {
4722 Inst.addOperand(MCOperand::createReg(ARM::SP));
4723 Inst.addOperand(MCOperand::createReg(ARM::SP));
4724 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
4731 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
4737 Inst.addOperand(MCOperand::createImm(imod));
4738 Inst.addOperand(MCOperand::createImm(flags));
4743 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
4750 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
4752 Inst.addOperand(MCOperand::createImm(add));
4757 static DecodeStatus DecodeMveAddrModeRQ(MCInst &Inst, unsigned Insn,
4764 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
4766 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4773 static DecodeStatus DecodeMveAddrModeQ(MCInst &Inst, unsigned Insn,
4780 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
4791 Inst.addOperand(MCOperand::createImm(imm));
4796 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
4816 true, 4, Inst, Decoder))
4817 Inst.addOperand(MCOperand::createImm(imm32));
4821 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
4833 Inst.addOperand(MCOperand::createImm(Val));
4837 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
4848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
4850 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
4855 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
4867 Inst.setOpcode(ARM::t2DSB);
4870 Inst.setOpcode(ARM::t2DMB);
4873 Inst.setOpcode(ARM::t2ISB);
4878 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
4887 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
4889 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
4898 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, uint64_t Address,
4906 Inst.addOperand(MCOperand::createImm(imm));
4909 Inst.addOperand(MCOperand::createImm((imm << 16) | imm));
4912 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 8)));
4915 Inst.addOperand(MCOperand::createImm((imm << 24) | (imm << 16) |
4923 Inst.addOperand(MCOperand::createImm(imm));
4929 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
4933 true, 2, Inst, Decoder))
4934 Inst.addOperand(MCOperand::createImm(SignExtend32<9>(Val << 1)));
4938 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
4957 true, 4, Inst, Decoder))
4958 Inst.addOperand(MCOperand::createImm(imm32));
4962 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
4968 Inst.addOperand(MCOperand::createImm(Val));
4972 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
4978 Inst.addOperand(MCOperand::createImm(Val));
4982 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, uint64_t Address,
5054 if (Inst.getOpcode() == ARM::t2MSR_M) {
5079 Inst.addOperand(MCOperand::createImm(Val));
5083 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val,
5095 Inst.addOperand(MCOperand::createImm(Val));
5099 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
5111 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
5113 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5115 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5121 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
5131 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
5137 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
5139 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5141 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5147 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
5161 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5163 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5165 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5167 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5173 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
5189 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5191 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5193 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5195 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5201 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
5215 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5217 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5219 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
5221 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5227 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
5241 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5243 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
5245 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
5247 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5253 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5296 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5299 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5302 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5304 Inst.addOperand(MCOperand::createImm(align));
5307 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5310 Inst.addOperand(MCOperand::createReg(0));
5313 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5315 Inst.addOperand(MCOperand::createImm(index));
5320 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5364 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5367 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5369 Inst.addOperand(MCOperand::createImm(align));
5372 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5375 Inst.addOperand(MCOperand::createReg(0));
5378 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5380 Inst.addOperand(MCOperand::createImm(index));
5385 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5424 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5426 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5429 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5432 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5434 Inst.addOperand(MCOperand::createImm(align));
5437 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5440 Inst.addOperand(MCOperand::createReg(0));
5443 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5445 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5447 Inst.addOperand(MCOperand::createImm(index));
5452 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5492 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5495 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5497 Inst.addOperand(MCOperand::createImm(align));
5500 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5503 Inst.addOperand(MCOperand::createReg(0));
5506 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5508 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5510 Inst.addOperand(MCOperand::createImm(index));
5515 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5552 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5554 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5556 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5560 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5563 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5565 Inst.addOperand(MCOperand::createImm(align));
5568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5571 Inst.addOperand(MCOperand::createReg(0));
5574 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5576 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5578 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5580 Inst.addOperand(MCOperand::createImm(index));
5585 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5623 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5626 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5628 Inst.addOperand(MCOperand::createImm(align));
5631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5634 Inst.addOperand(MCOperand::createReg(0));
5637 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5639 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5641 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5643 Inst.addOperand(MCOperand::createImm(index));
5648 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5692 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5694 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5696 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5698 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5702 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5705 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5707 Inst.addOperand(MCOperand::createImm(align));
5710 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5713 Inst.addOperand(MCOperand::createReg(0));
5716 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5718 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5720 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5722 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5724 Inst.addOperand(MCOperand::createImm(index));
5729 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, uint64_t Address,
5774 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5777 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
5779 Inst.addOperand(MCOperand::createImm(align));
5782 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
5785 Inst.addOperand(MCOperand::createReg(0));
5788 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
5790 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
5792 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
5794 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
5796 Inst.addOperand(MCOperand::createImm(index));
5801 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, uint64_t Address,
5813 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5815 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5817 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5819 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5821 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5827 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, uint64_t Address,
5839 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
5841 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
5843 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
5845 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
5847 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
5853 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, uint64_t Address,
5877 Inst.addOperand(MCOperand::createImm(pred));
5878 Inst.addOperand(MCOperand::createImm(mask));
5882 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
5904 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5907 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5910 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5913 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5919 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
5939 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
5942 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
5945 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
5948 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
5954 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, uint64_t Address,
5960 assert(Inst.getNumOperands() == 0 && "We should receive an empty Inst");
5961 DecodeStatus S = DecoderGPRRegisterClass(Inst, Rd, Address, Decoder);
5971 Inst.setOpcode(ARM::t2SUBri12);
5972 Inst.addOperand(MCOperand::createReg(ARM::PC));
5976 Inst.addOperand(MCOperand::createImm(Val));
5980 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
5987 Inst.addOperand(MCOperand::createImm(Val));
5991 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, uint64_t Address,
5999 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
6006 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6008 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
6010 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6012 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
6018 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, uint64_t Address,
6038 Inst.setOpcode(ARM::VMOVv2f32);
6043 Inst.setOpcode(ARM::VMOVv1i64);
6045 Inst.setOpcode(ARM::VMOVv8i8);
6050 Inst.setOpcode(ARM::VMVNv2i32);
6052 Inst.setOpcode(ARM::VMOVv2i32);
6057 Inst.setOpcode(ARM::VMVNv2i32);
6059 Inst.setOpcode(ARM::VMOVv2i32);
6063 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
6068 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
6070 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
6072 Inst.addOperand(MCOperand::createImm(64 - imm));
6077 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, uint64_t Address,
6097 Inst.setOpcode(ARM::VMOVv4f32);
6102 Inst.setOpcode(ARM::VMOVv2i64);
6104 Inst.setOpcode(ARM::VMOVv16i8);
6109 Inst.setOpcode(ARM::VMVNv4i32);
6111 Inst.setOpcode(ARM::VMOVv4i32);
6116 Inst.setOpcode(ARM::VMVNv4i32);
6118 Inst.setOpcode(ARM::VMOVv4i32);
6122 return DecodeVMOVModImmInstruction(Inst, Insn, Address, Decoder);
6127 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
6129 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
6131 Inst.addOperand(MCOperand::createImm(64 - imm));
6137 DecodeNEONComplexLane64Instruction(MCInst &Inst, unsigned Insn,
6153 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
6155 if (!Check(S, DestRegDecoder(Inst, Vd, Address, Decoder)))
6157 if (!Check(S, DestRegDecoder(Inst, Vn, Address, Decoder)))
6159 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
6163 Inst.addOperand(MCOperand::createImm(0));
6164 Inst.addOperand(MCOperand::createImm(rotate));
6169 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, uint64_t Address,
6182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6186 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
6188 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
6190 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
6196 static DecodeStatus DecoderForMRRC2AndMCRR2(MCInst &Inst, unsigned Val,
6215 // Inst. Reason is because MRRC2 stores to two
6223 if (Inst.getOpcode() == ARM::MRRC2) {
6224 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6226 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
6229 Inst.addOperand(MCOperand::createImm(cop));
6230 Inst.addOperand(MCOperand::createImm(opc1));
6231 if (Inst.getOpcode() == ARM::MCRR2) {
6232 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
6234 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
6237 Inst.addOperand(MCOperand::createImm(CRm));
6242 static DecodeStatus DecodeForVMRSandVMSR(MCInst &Inst, unsigned Val,
6251 switch (Inst.getOpcode()) {
6253 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
6256 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6260 if (Inst.getOpcode() != ARM::FMSTAT) {
6266 Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder));
6268 Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder));
6272 switch (Inst.getOpcode()) {
6274 Inst.addOperand(MCOperand::createReg(ARM::FPSCR_NZCV));
6277 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6282 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6283 Inst.addOperand(MCOperand::createReg(0));
6286 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
6294 static DecodeStatus DecodeBFLabelOperand(MCInst &Inst, unsigned Val,
6307 if (!tryAddingSymbolicOperand(Address, Address + DecVal + 4, true, 4, Inst,
6309 Inst.addOperand(MCOperand::createImm(isNeg ? -DecVal : DecVal));
6313 static DecodeStatus DecodeBFAfterTargetOperand(MCInst &Inst, unsigned Val,
6317 uint64_t LocImm = Inst.getOperand(0).getImm();
6319 if (!tryAddingSymbolicOperand(Address, Address + Val + 4, true, 4, Inst,
6321 Inst.addOperand(MCOperand::createImm(Val));
6325 static DecodeStatus DecodePredNoALOperand(MCInst &Inst, unsigned Val,
6330 Inst.addOperand(MCOperand::createImm(Val));
6334 static DecodeStatus DecodeLOLoop(MCInst &Inst, unsigned Insn, uint64_t Address,
6338 if (Inst.getOpcode() == ARM::MVE_LCTP)
6343 switch (Inst.getOpcode()) {
6346 Inst.addOperand(MCOperand::createReg(ARM::LR));
6347 Inst.addOperand(MCOperand::createReg(ARM::LR));
6351 Inst, Imm, Address, Decoder)))
6359 Inst.addOperand(MCOperand::createReg(ARM::LR));
6361 DecoderGPRRegisterClass(Inst, fieldFromInstruction(Insn, 16, 4),
6364 Inst, Imm, Address, Decoder)))
6383 Inst.setOpcode(ARM::MVE_LCTP);
6385 Inst.addOperand(MCOperand::createReg(ARM::LR));
6386 if (!Check(S, DecoderGPRRegisterClass(Inst,
6396 static DecodeStatus DecodeLongShiftOperand(MCInst &Inst, unsigned Val,
6404 Inst.addOperand(MCOperand::createImm(Val));
6409 static DecodeStatus DecodetGPROddRegisterClass(MCInst &Inst, unsigned RegNo,
6416 Inst.addOperand(MCOperand::createReg(Register));
6420 static DecodeStatus DecodetGPREvenRegisterClass(MCInst &Inst, unsigned RegNo,
6427 Inst.addOperand(MCOperand::createReg(Register));
6432 DecodeGPRwithAPSR_NZCVnospRegisterClass(MCInst &Inst, unsigned RegNo,
6436 Inst.addOperand(MCOperand::createReg(ARM::APSR_NZCV));
6441 Inst.addOperand(MCOperand::createReg(Register));
6449 static DecodeStatus DecodeVSCCLRM(MCInst &Inst, unsigned Insn, uint64_t Address,
6453 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6454 Inst.addOperand(MCOperand::createReg(0));
6458 } else if (Inst.getOpcode() == ARM::VSCCLRMD) {
6461 if (!Check(S, DecodeDPRRegListOperand(Inst, reglist, Address, Decoder))) {
6475 if (!Check(S, DecodeSPRRegisterClass(Inst, i, Address, Decoder)))
6478 if (!Check(S, DecodeDPRRegisterClass(Inst, i, Address, Decoder)))
6481 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6486 static DecodeStatus DecodeMQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6493 Inst.addOperand(MCOperand::createReg(Register));
6502 static DecodeStatus DecodeMQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6509 Inst.addOperand(MCOperand::createReg(Register));
6518 static DecodeStatus DecodeMQQQQPRRegisterClass(MCInst &Inst, unsigned RegNo,
6525 Inst.addOperand(MCOperand::createReg(Register));
6529 static DecodeStatus DecodeVPTMaskOperand(MCInst &Inst, unsigned Val,
6555 Inst.addOperand(MCOperand::createImm(Imm));
6560 static DecodeStatus DecodeVpredROperand(MCInst &Inst, unsigned RegNo,
6574 DecodeVpredNOperand(MCInst &Inst, unsigned RegNo, uint64_t Address,
6585 DecodeRestrictedIPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6587 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::EQ : ARMCC::NE));
6592 DecodeRestrictedSPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6609 Inst.addOperand(MCOperand::createImm(Code));
6614 DecodeRestrictedUPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6616 Inst.addOperand(MCOperand::createImm((Val & 0x1) == 0 ? ARMCC::HS : ARMCC::HI));
6621 DecodeRestrictedFPPredicateOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6647 Inst.addOperand(MCOperand::createImm(Code));
6651 static DecodeStatus DecodeVCVTImmOperand(MCInst &Inst, unsigned Val,
6658 switch (Inst.getOpcode()) {
6675 Inst.addOperand(MCOperand::createImm(64 - Val));
6702 static DecodeStatus DecodeVSTRVLDR_SYSREG(MCInst &Inst, unsigned Val,
6705 switch (Inst.getOpcode()) {
6726 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
6727 Inst.addOperand(MCOperand::createReg(Sysreg));
6733 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
6736 if (!Check(S, DecodeT2AddrModeImm7s4(Inst, addr, Address, Decoder)))
6739 Inst.addOperand(MCOperand::createImm(ARMCC::AL));
6740 Inst.addOperand(MCOperand::createReg(0));
6746 DecodeMVE_MEM_pre(MCInst &Inst, unsigned Val, uint64_t Address,
6755 if (!Check(S, RnDecoder(Inst, Rn, Address, Decoder)))
6757 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6759 if (!Check(S, AddrDecoder(Inst, addr, Address, Decoder)))
6766 static DecodeStatus DecodeMVE_MEM_1_pre(MCInst &Inst, unsigned Val,
6769 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6776 static DecodeStatus DecodeMVE_MEM_2_pre(MCInst &Inst, unsigned Val,
6779 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6786 static DecodeStatus DecodeMVE_MEM_3_pre(MCInst &Inst, unsigned Val,
6789 return DecodeMVE_MEM_pre(Inst, Val, Address, Decoder,
6796 static DecodeStatus DecodePowerTwoOperand(MCInst &Inst, unsigned Val,
6804 Inst.addOperand(MCOperand::createImm(1LL << Val));
6810 DecodeMVEPairVectorIndexOperand(MCInst &Inst, unsigned Val, uint64_t Address,
6814 Inst.addOperand(MCOperand::createImm(start + Val));
6819 static DecodeStatus DecodeMVEVMOVQtoDReg(MCInst &Inst, unsigned Insn,
6829 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6831 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6833 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6835 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6837 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6843 static DecodeStatus DecodeMVEVMOVDRegtoQ(MCInst &Inst, unsigned Insn,
6853 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6855 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6857 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
6859 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2, Address, Decoder)))
6861 if (!Check(S, DecodeMVEPairVectorIndexOperand<2>(Inst, index, Address, Decoder)))
6863 if (!Check(S, DecodeMVEPairVectorIndexOperand<0>(Inst, index, Address, Decoder)))
6870 DecodeMVEOverlappingLongShift(MCInst &Inst, unsigned Insn, uint64_t Address,
6886 switch (Inst.getOpcode()) {
6889 Inst.setOpcode(ARM::MVE_SQRSHR);
6893 Inst.setOpcode(ARM::MVE_UQRSHL);
6900 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6904 if (!Check(S, DecoderGPRRegisterClass(Inst, Rda, Address, Decoder)))
6908 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6921 // put into Inst. Those all look the same:
6924 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6926 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6930 if (!Check(S, DecodetGPREvenRegisterClass(Inst, RdaLo, Address, Decoder)))
6932 if (!Check(S, DecodetGPROddRegisterClass(Inst, RdaHi, Address, Decoder)))
6936 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
6939 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6940 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
6943 Inst.addOperand(MCOperand::createImm(Saturate));
6949 static DecodeStatus DecodeMVEVCVTt1fp(MCInst &Inst, unsigned Insn,
6959 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qd, Address, Decoder)))
6961 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6963 if (!Check(S, DecodeVCVTImmOperand(Inst, imm6, Address, Decoder)))
6970 static DecodeStatus DecodeMVEVCMP(MCInst &Inst, unsigned Insn, uint64_t Address,
6973 Inst.addOperand(MCOperand::createReg(ARM::VPR));
6975 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qn, Address, Decoder)))
6985 if (!Check(S, DecodeGPRwithZRRegisterClass(Inst, Rm, Address, Decoder)))
6993 if (!Check(S, DecodeMQPRRegisterClass(Inst, Qm, Address, Decoder)))
6997 if (!Check(S, predicate_decoder(Inst, fc, Address, Decoder)))
7000 Inst.addOperand(MCOperand::createImm(ARMVCC::None));
7001 Inst.addOperand(MCOperand::createReg(0));
7002 Inst.addOperand(MCOperand::createImm(0));
7007 static DecodeStatus DecodeMveVCTP(MCInst &Inst, unsigned Insn, uint64_t Address,
7010 Inst.addOperand(MCOperand::createReg(ARM::VPR));
7012 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
7017 static DecodeStatus DecodeMVEVPNOT(MCInst &Inst, unsigned Insn,
7021 Inst.addOperand(MCOperand::createReg(ARM::VPR));
7022 Inst.addOperand(MCOperand::createReg(ARM::VPR));
7026 static DecodeStatus DecodeT2AddSubSPImm(MCInst &Inst, unsigned Insn,
7044 DecodeGPRspRegisterClass(Inst, Rd, Address, Decoder))) || // dst
7045 (!Check(DS, DecodeGPRspRegisterClass(Inst, Rn, Address, Decoder))))
7048 Inst.setOpcode(sign1 ? ARM::t2SUBspImm12 : ARM::t2ADDspImm12);
7049 Inst.addOperand(MCOperand::createImm(Imm12)); // zext imm12
7051 Inst.setOpcode(sign1 ? ARM::t2SUBspImm : ARM::t2ADDspImm);
7052 if (!Check(DS, DecodeT2SOImm(Inst, Imm12, Address, Decoder))) // imm12
7054 if (!Check(DS, DecodeCCOutOperand(Inst, S, Address, Decoder))) // cc_out
7061 static DecodeStatus DecodeLazyLoadStoreMul(MCInst &Inst, unsigned Insn,
7070 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
7073 DecodePredicateOperand(Inst, ARMCC::AL, Address, Decoder);
7076 Inst.addOperand(MCOperand::createImm(0)); // Arbitrary value, has no effect.