Lines Matching defs:Inst
67 static DecodeStatus DecodeGPR8RegisterClass(MCInst &Inst, unsigned RegNo,
74 Inst.addOperand(MCOperand::createReg(Register));
78 static DecodeStatus DecodeLD8RegisterClass(MCInst &Inst, unsigned RegNo,
85 Inst.addOperand(MCOperand::createReg(Register));
89 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
92 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
95 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
98 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Insn,
102 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
105 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
108 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
112 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
116 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
119 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
123 static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
126 static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address,
129 static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn,
133 static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
139 static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
145 Inst.addOperand(MCOperand::createImm(addr));
146 if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
152 static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
158 if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
161 Inst.addOperand(MCOperand::createImm(addr));
165 static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
169 Inst.addOperand(MCOperand::createImm(addr));
170 Inst.addOperand(MCOperand::createImm(b));
174 static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
179 Inst.addOperand(MCOperand::createImm(Field << 1));
183 static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
186 if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
192 static DecodeStatus decodeFLPMX(MCInst &Inst, unsigned Insn, uint64_t Address,
194 if (decodeFRd(Inst, Insn, Address, Decoder) == MCDisassembler::Fail)
196 Inst.addOperand(MCOperand::createReg(AVR::R31R30));
200 static DecodeStatus decodeFFMULRdRr(MCInst &Inst, unsigned Insn,
205 if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
208 if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
214 static DecodeStatus decodeFMOVWRdRr(MCInst &Inst, unsigned Insn,
219 if (DecodeGPR8RegisterClass(Inst, r, Address, Decoder) ==
222 if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
228 static DecodeStatus decodeFWRdK(MCInst &Inst, unsigned Insn, uint64_t Address,
234 if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
237 if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
240 Inst.addOperand(MCOperand::createImm(k));
244 static DecodeStatus decodeFMUL2RdRr(MCInst &Inst, unsigned Insn,
249 if (DecodeGPR8RegisterClass(Inst, rd, Address, Decoder) ==
252 if (DecodeGPR8RegisterClass(Inst, rr, Address, Decoder) ==
258 static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
267 Inst.addOperand(
270 Inst.addOperand(MCOperand::createImm(Insn & 0x3f));
275 static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address,
280 Inst.setOpcode(AVR::RJMPk);
283 Inst.setOpcode(AVR::RCALLk);
290 Inst.addOperand(MCOperand::createImm(Offset));
294 static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn,
316 Inst.setOpcode(It->second);
317 Inst.addOperand(MCOperand::createImm(Offset));
320 Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk);
321 Inst.addOperand(MCOperand::createImm(Insn & 7));
322 Inst.addOperand(MCOperand::createImm(Offset));
328 static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
339 Inst.setOpcode(AVR::LDDRdPtrQ);
340 Inst.addOperand(MCOperand::createReg(RegVal));
341 Inst.addOperand(MCOperand::createReg(RegBase));
342 Inst.addOperand(MCOperand::createImm(Offset));
344 Inst.setOpcode(AVR::STDPtrQRr);
345 Inst.addOperand(MCOperand::createReg(RegBase));
346 Inst.addOperand(MCOperand::createImm(Offset));
347 Inst.addOperand(MCOperand::createReg(RegVal));
392 Inst.setOpcode(AVR::STPtrRr);
393 Inst.addOperand(MCOperand::createReg(RegBase));
394 Inst.addOperand(MCOperand::createReg(RegVal));
397 Inst.setOpcode(AVR::STPtrPiRr);
400 Inst.setOpcode(AVR::STPtrPdRr);
403 Inst.setOpcode(AVR::LDRdPtr);
404 Inst.addOperand(MCOperand::createReg(RegVal));
405 Inst.addOperand(MCOperand::createReg(RegBase));
408 Inst.setOpcode(AVR::LDRdPtrPi);
411 Inst.setOpcode(AVR::LDRdPtrPd);
419 Inst.addOperand(MCOperand::createReg(RegVal));
420 Inst.addOperand(MCOperand::createReg(RegBase));
421 Inst.addOperand(MCOperand::createReg(RegBase));
423 Inst.addOperand(MCOperand::createReg(RegBase));
424 Inst.addOperand(MCOperand::createReg(RegBase));
425 Inst.addOperand(MCOperand::createReg(RegVal));
427 Inst.addOperand(MCOperand::createImm(1));