Lines Matching defs:Inst
81 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
85 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo,
89 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
94 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
98 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
101 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
105 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned Insn,
109 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
113 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
117 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
121 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
125 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
129 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
133 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned Insn,
137 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
141 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
145 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
149 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
153 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
157 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
161 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
165 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
169 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
173 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
177 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
181 static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
185 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
189 static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
193 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
197 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
201 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
207 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
213 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
219 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
225 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
231 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
237 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
241 static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
244 static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
247 static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
251 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
254 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
258 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
262 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
266 static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
269 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
273 static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
276 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
280 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
284 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
288 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
292 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
296 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
300 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
304 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
308 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
311 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
315 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
318 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
321 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
325 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
329 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
333 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
337 static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
341 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
346 static DecodeStatus DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
351 static DecodeStatus DecodeUImmWithOffset(MCInst &Inst, unsigned Value,
354 return DecodeUImmWithOffsetAndScale<Bits, Offset, 1>(Inst, Value, Address,
359 static DecodeStatus DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value,
363 static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
366 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
370 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
374 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
377 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
381 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
472 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
476 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
480 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
484 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
488 static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,
1337 DecodeCPU16RegsRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1342 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst, unsigned RegNo,
1349 Inst.addOperand(MCOperand::createReg(Reg));
1353 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst, unsigned RegNo,
1359 Inst.addOperand(MCOperand::createReg(Reg));
1364 DecodeGPRMM16ZeroRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1369 Inst.addOperand(MCOperand::createReg(Reg));
1374 DecodeGPRMM16MovePRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Address,
1379 Inst.addOperand(MCOperand::createReg(Reg));
1383 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst, unsigned RegNo,
1389 Inst.addOperand(MCOperand::createReg(Reg));
1393 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst, unsigned RegNo,
1397 return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
1399 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1402 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst, unsigned RegNo,
1405 return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
1408 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
1415 Inst.addOperand(MCOperand::createReg(Reg));
1419 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst, unsigned RegNo,
1426 Inst.addOperand(MCOperand::createReg(Reg));
1430 static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst, unsigned RegNo,
1436 Inst.addOperand(MCOperand::createReg(Reg));
1440 static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
1446 Inst.addOperand(MCOperand::createReg(Reg));
1450 static DecodeStatus DecodeFGRCCRegisterClass(MCInst &Inst, unsigned RegNo,
1457 Inst.addOperand(MCOperand::createReg(Reg));
1461 static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1470 if (Inst.getOpcode() == Mips::SC ||
1471 Inst.getOpcode() == Mips::SCD)
1472 Inst.addOperand(MCOperand::createReg(Reg));
1474 Inst.addOperand(MCOperand::createReg(Reg));
1475 Inst.addOperand(MCOperand::createReg(Base));
1476 Inst.addOperand(MCOperand::createImm(Offset));
1481 static DecodeStatus DecodeMemEVA(MCInst &Inst, unsigned Insn, uint64_t Address,
1490 if (Inst.getOpcode() == Mips::SCE)
1491 Inst.addOperand(MCOperand::createReg(Reg));
1493 Inst.addOperand(MCOperand::createReg(Reg));
1494 Inst.addOperand(MCOperand::createReg(Base));
1495 Inst.addOperand(MCOperand::createImm(Offset));
1500 static DecodeStatus DecodeLoadByte15(MCInst &Inst, unsigned Insn,
1510 Inst.addOperand(MCOperand::createReg(Reg));
1511 Inst.addOperand(MCOperand::createReg(Base));
1512 Inst.addOperand(MCOperand::createImm(Offset));
1517 static DecodeStatus DecodeCacheOp(MCInst &Inst, unsigned Insn, uint64_t Address,
1525 Inst.addOperand(MCOperand::createReg(Base));
1526 Inst.addOperand(MCOperand::createImm(Offset));
1527 Inst.addOperand(MCOperand::createImm(Hint));
1532 static DecodeStatus DecodeCacheOpMM(MCInst &Inst, unsigned Insn,
1541 Inst.addOperand(MCOperand::createReg(Base));
1542 Inst.addOperand(MCOperand::createImm(Offset));
1543 Inst.addOperand(MCOperand::createImm(Hint));
1548 static DecodeStatus DecodePrefeOpMM(MCInst &Inst, unsigned Insn,
1557 Inst.addOperand(MCOperand::createReg(Base));
1558 Inst.addOperand(MCOperand::createImm(Offset));
1559 Inst.addOperand(MCOperand::createImm(Hint));
1564 static DecodeStatus DecodeCacheeOp_CacheOpR6(MCInst &Inst, unsigned Insn,
1573 Inst.addOperand(MCOperand::createReg(Base));
1574 Inst.addOperand(MCOperand::createImm(Offset));
1575 Inst.addOperand(MCOperand::createImm(Hint));
1580 static DecodeStatus DecodeSyncI(MCInst &Inst, unsigned Insn, uint64_t Address,
1587 Inst.addOperand(MCOperand::createReg(Base));
1588 Inst.addOperand(MCOperand::createImm(Offset));
1593 static DecodeStatus DecodeSyncI_MM(MCInst &Inst, unsigned Insn,
1601 Inst.addOperand(MCOperand::createReg(Base));
1602 Inst.addOperand(MCOperand::createImm(Offset));
1607 static DecodeStatus DecodeSynciR6(MCInst &Inst, unsigned Insn, uint64_t Address,
1614 Inst.addOperand(MCOperand::createReg(Base));
1615 Inst.addOperand(MCOperand::createImm(Immediate));
1620 static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
1630 Inst.addOperand(MCOperand::createReg(Reg));
1631 Inst.addOperand(MCOperand::createReg(Base));
1640 switch(Inst.getOpcode())
1648 Inst.addOperand(MCOperand::createImm(Offset));
1652 Inst.addOperand(MCOperand::createImm(Offset * 2));
1656 Inst.addOperand(MCOperand::createImm(Offset * 4));
1660 Inst.addOperand(MCOperand::createImm(Offset * 8));
1667 static DecodeStatus DecodeMemMMImm4(MCInst &Inst, unsigned Insn,
1674 switch (Inst.getOpcode()) {
1678 if (DecodeGPRMM16RegisterClass(Inst, Reg, Address, Decoder)
1688 if (DecodeGPRMM16ZeroRegisterClass(Inst, Reg, Address, Decoder)
1694 if (DecodeGPRMM16RegisterClass(Inst, Base, Address, Decoder)
1698 switch (Inst.getOpcode()) {
1701 Inst.addOperand(MCOperand::createImm(-1));
1703 Inst.addOperand(MCOperand::createImm(Offset));
1707 Inst.addOperand(MCOperand::createImm(Offset));
1712 Inst.addOperand(MCOperand::createImm(Offset << 1));
1717 Inst.addOperand(MCOperand::createImm(Offset << 2));
1724 static DecodeStatus DecodeMemMMSPImm5Lsl2(MCInst &Inst, unsigned Insn,
1732 Inst.addOperand(MCOperand::createReg(Reg));
1733 Inst.addOperand(MCOperand::createReg(Mips::SP));
1734 Inst.addOperand(MCOperand::createImm(Offset << 2));
1739 static DecodeStatus DecodeMemMMGPImm7Lsl2(MCInst &Inst, unsigned Insn,
1747 Inst.addOperand(MCOperand::createReg(Reg));
1748 Inst.addOperand(MCOperand::createReg(Mips::GP));
1749 Inst.addOperand(MCOperand::createImm(Offset << 2));
1754 static DecodeStatus DecodeMemMMReglistImm4Lsl2(MCInst &Inst, unsigned Insn,
1758 switch (Inst.getOpcode()) {
1768 if (DecodeRegListOperand16(Inst, Insn, Address, Decoder)
1772 Inst.addOperand(MCOperand::createReg(Mips::SP));
1773 Inst.addOperand(MCOperand::createImm(Offset << 2));
1778 static DecodeStatus DecodeMemMMImm9(MCInst &Inst, unsigned Insn,
1788 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1789 Inst.addOperand(MCOperand::createReg(Reg));
1791 Inst.addOperand(MCOperand::createReg(Reg));
1792 Inst.addOperand(MCOperand::createReg(Base));
1793 Inst.addOperand(MCOperand::createImm(Offset));
1798 static DecodeStatus DecodeMemMMImm12(MCInst &Inst, unsigned Insn,
1808 switch (Inst.getOpcode()) {
1811 if (DecodeRegListOperand(Inst, Insn, Address, Decoder)
1814 Inst.addOperand(MCOperand::createReg(Base));
1815 Inst.addOperand(MCOperand::createImm(Offset));
1818 Inst.addOperand(MCOperand::createReg(Reg));
1821 Inst.addOperand(MCOperand::createReg(Reg));
1822 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1823 Inst.addOperand(MCOperand::createReg(Reg+1));
1825 Inst.addOperand(MCOperand::createReg(Base));
1826 Inst.addOperand(MCOperand::createImm(Offset));
1832 static DecodeStatus DecodeMemMMImm16(MCInst &Inst, unsigned Insn,
1842 Inst.addOperand(MCOperand::createReg(Reg));
1843 Inst.addOperand(MCOperand::createReg(Base));
1844 Inst.addOperand(MCOperand::createImm(Offset));
1849 static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn, uint64_t Address,
1858 Inst.addOperand(MCOperand::createReg(Reg));
1859 Inst.addOperand(MCOperand::createReg(Base));
1860 Inst.addOperand(MCOperand::createImm(Offset));
1865 static DecodeStatus DecodeFMemMMR2(MCInst &Inst, unsigned Insn,
1877 Inst.addOperand(MCOperand::createReg(Reg));
1878 Inst.addOperand(MCOperand::createReg(Base));
1879 Inst.addOperand(MCOperand::createImm(Offset));
1884 static DecodeStatus DecodeFMem2(MCInst &Inst, unsigned Insn, uint64_t Address,
1893 Inst.addOperand(MCOperand::createReg(Reg));
1894 Inst.addOperand(MCOperand::createReg(Base));
1895 Inst.addOperand(MCOperand::createImm(Offset));
1900 static DecodeStatus DecodeFMem3(MCInst &Inst, unsigned Insn, uint64_t Address,
1909 Inst.addOperand(MCOperand::createReg(Reg));
1910 Inst.addOperand(MCOperand::createReg(Base));
1911 Inst.addOperand(MCOperand::createImm(Offset));
1916 static DecodeStatus DecodeFMemCop2R6(MCInst &Inst, unsigned Insn,
1926 Inst.addOperand(MCOperand::createReg(Reg));
1927 Inst.addOperand(MCOperand::createReg(Base));
1928 Inst.addOperand(MCOperand::createImm(Offset));
1933 static DecodeStatus DecodeFMemCop2MMR6(MCInst &Inst, unsigned Insn,
1943 Inst.addOperand(MCOperand::createReg(Reg));
1944 Inst.addOperand(MCOperand::createReg(Base));
1945 Inst.addOperand(MCOperand::createImm(Offset));
1950 static DecodeStatus DecodeSpecial3LlSc(MCInst &Inst, unsigned Insn,
1960 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
1961 Inst.addOperand(MCOperand::createReg(Rt));
1964 Inst.addOperand(MCOperand::createReg(Rt));
1965 Inst.addOperand(MCOperand::createReg(Base));
1966 Inst.addOperand(MCOperand::createImm(Offset));
1971 static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst, unsigned RegNo,
1977 Inst.addOperand(MCOperand::createReg(Mips::HWR29));
1981 static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst, unsigned RegNo,
1988 Inst.addOperand(MCOperand::createReg(Reg));
1992 static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst, unsigned RegNo,
1999 Inst.addOperand(MCOperand::createReg(Reg));
2003 static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
2010 Inst.addOperand(MCOperand::createReg(Reg));
2014 static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst, unsigned RegNo,
2021 Inst.addOperand(MCOperand::createReg(Reg));
2025 static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst, unsigned RegNo,
2032 Inst.addOperand(MCOperand::createReg(Reg));
2036 static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst, unsigned RegNo,
2043 Inst.addOperand(MCOperand::createReg(Reg));
2047 static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst, unsigned RegNo,
2054 Inst.addOperand(MCOperand::createReg(Reg));
2058 static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst, unsigned RegNo,
2065 Inst.addOperand(MCOperand::createReg(Reg));
2069 static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst, unsigned RegNo,
2076 Inst.addOperand(MCOperand::createReg(Reg));
2080 static DecodeStatus DecodeCOP0RegisterClass(MCInst &Inst, unsigned RegNo,
2087 Inst.addOperand(MCOperand::createReg(Reg));
2091 static DecodeStatus DecodeCOP2RegisterClass(MCInst &Inst, unsigned RegNo,
2098 Inst.addOperand(MCOperand::createReg(Reg));
2102 static DecodeStatus DecodeBranchTarget(MCInst &Inst, unsigned Offset,
2106 Inst.addOperand(MCOperand::createImm(BranchOffset));
2110 static DecodeStatus DecodeBranchTarget1SImm16(MCInst &Inst, unsigned Offset,
2114 Inst.addOperand(MCOperand::createImm(BranchOffset));
2118 static DecodeStatus DecodeJumpTarget(MCInst &Inst, unsigned Insn,
2122 Inst.addOperand(MCOperand::createImm(JumpOffset));
2126 static DecodeStatus DecodeBranchTarget21(MCInst &Inst, unsigned Offset,
2131 Inst.addOperand(MCOperand::createImm(BranchOffset));
2135 static DecodeStatus DecodeBranchTarget21MM(MCInst &Inst, unsigned Offset,
2140 Inst.addOperand(MCOperand::createImm(BranchOffset));
2144 static DecodeStatus DecodeBranchTarget26(MCInst &Inst, unsigned Offset,
2149 Inst.addOperand(MCOperand::createImm(BranchOffset));
2153 static DecodeStatus DecodeBranchTarget7MM(MCInst &Inst, unsigned Offset,
2157 Inst.addOperand(MCOperand::createImm(BranchOffset));
2161 static DecodeStatus DecodeBranchTarget10MM(MCInst &Inst, unsigned Offset,
2165 Inst.addOperand(MCOperand::createImm(BranchOffset));
2169 static DecodeStatus DecodeBranchTargetMM(MCInst &Inst, unsigned Offset,
2173 Inst.addOperand(MCOperand::createImm(BranchOffset));
2177 static DecodeStatus DecodeBranchTarget26MM(MCInst &Inst, unsigned Offset,
2182 Inst.addOperand(MCOperand::createImm(BranchOffset));
2186 static DecodeStatus DecodeJumpTargetMM(MCInst &Inst, unsigned Insn,
2190 Inst.addOperand(MCOperand::createImm(JumpOffset));
2194 static DecodeStatus DecodeJumpTargetXMM(MCInst &Inst, unsigned Insn,
2198 Inst.addOperand(MCOperand::createImm(JumpOffset));
2202 static DecodeStatus DecodeAddiur2Simm7(MCInst &Inst, unsigned Value,
2206 Inst.addOperand(MCOperand::createImm(1));
2208 Inst.addOperand(MCOperand::createImm(-1));
2210 Inst.addOperand(MCOperand::createImm(Value << 2));
2214 static DecodeStatus DecodeLi16Imm(MCInst &Inst, unsigned Value,
2218 Inst.addOperand(MCOperand::createImm(-1));
2220 Inst.addOperand(MCOperand::createImm(Value));
2224 static DecodeStatus DecodePOOL16BEncodedField(MCInst &Inst, unsigned Value,
2227 Inst.addOperand(MCOperand::createImm(Value == 0x0 ? 8 : Value));
2233 DecodeUImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
2237 Inst.addOperand(MCOperand::createImm(Value + Offset));
2243 DecodeSImmWithOffsetAndScale(MCInst &Inst, unsigned Value, uint64_t Address,
2246 Inst.addOperand(MCOperand::createImm(Imm + Offset));
2250 static DecodeStatus DecodeInsSize(MCInst &Inst, unsigned Insn, uint64_t Address,
2255 int Pos = Inst.getOperand(2).getImm();
2257 Inst.addOperand(MCOperand::createImm(SignExtend32<16>(Size)));
2261 static DecodeStatus DecodeSimm19Lsl2(MCInst &Inst, unsigned Insn,
2264 Inst.addOperand(MCOperand::createImm(SignExtend32<19>(Insn) * 4));
2268 static DecodeStatus DecodeSimm18Lsl3(MCInst &Inst, unsigned Insn,
2271 Inst.addOperand(MCOperand::createImm(SignExtend32<18>(Insn) * 8));
2275 static DecodeStatus DecodeSimm9SP(MCInst &Inst, unsigned Insn, uint64_t Address,
2285 Inst.addOperand(MCOperand::createImm(DecodedValue * 4));
2289 static DecodeStatus DecodeANDI16Imm(MCInst &Inst, unsigned Insn,
2296 Inst.addOperand(MCOperand::createImm(DecodedValues[Insn]));
2300 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Insn,
2320 Inst.addOperand(MCOperand::createReg(Regs[i]));
2323 Inst.addOperand(MCOperand::createReg(Mips::RA));
2328 static DecodeStatus DecodeRegListOperand16(MCInst &Inst, unsigned Insn,
2333 switch(Inst.getOpcode()) {
2345 Inst.addOperand(MCOperand::createReg(Regs[i]));
2347 Inst.addOperand(MCOperand::createReg(Mips::RA));
2352 static DecodeStatus DecodeMovePOperands(MCInst &Inst, unsigned Insn,
2356 if (DecodeMovePRegPair(Inst, RegPair, Address, Decoder) ==
2366 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRs, Address, Decoder) ==
2371 if (DecodeGPRMM16MovePRegisterClass(Inst, RegRt, Address, Decoder) ==
2378 static DecodeStatus DecodeMovePRegPair(MCInst &Inst, unsigned RegPair,
2385 Inst.addOperand(MCOperand::createReg(Mips::A1));
2386 Inst.addOperand(MCOperand::createReg(Mips::A2));
2389 Inst.addOperand(MCOperand::createReg(Mips::A1));
2390 Inst.addOperand(MCOperand::createReg(Mips::A3));
2393 Inst.addOperand(MCOperand::createReg(Mips::A2));
2394 Inst.addOperand(MCOperand::createReg(Mips::A3));
2397 Inst.addOperand(MCOperand::createReg(Mips::A0));
2398 Inst.addOperand(MCOperand::createReg(Mips::S5));
2401 Inst.addOperand(MCOperand::createReg(Mips::A0));
2402 Inst.addOperand(MCOperand::createReg(Mips::S6));
2405 Inst.addOperand(MCOperand::createReg(Mips::A0));
2406 Inst.addOperand(MCOperand::createReg(Mips::A1));
2409 Inst.addOperand(MCOperand::createReg(Mips::A0));
2410 Inst.addOperand(MCOperand::createReg(Mips::A2));
2413 Inst.addOperand(MCOperand::createReg(Mips::A0));
2414 Inst.addOperand(MCOperand::createReg(Mips::A3));
2421 static DecodeStatus DecodeSimm23Lsl2(MCInst &Inst, unsigned Insn,
2424 Inst.addOperand(MCOperand::createImm(SignExtend32<25>(Insn << 2)));
2523 static DecodeStatus DecodeFIXMEInstruction(MCInst &Inst, unsigned Insn,