crypto/qat: add GMAC capability

Added Galois Message Authentication Code (GMAC) capability to
QuickAssist Technology symmetric cryptographic driver.
GMAC is authentication only variant of Galois Cou

crypto/qat: add GMAC capability

Added Galois Message Authentication Code (GMAC) capability to
QuickAssist Technology symmetric cryptographic driver.
GMAC is authentication only variant of Galois Counter Mode (GCM)
where all plaintext is provided with AAD pointer only.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

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crypto/qat: add C3xxx device

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add C62x device

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add KASUMI

This patch add kasumi support in Intel(R)
QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

doc: fix names of supported crypto algorithms

Update documentation with correct names of supported algorithms.

Fixes: 1703e94ac5cee ("qat: add driver for QuickAssist devices")
Fixes: 3aafc423cf4d (

doc: fix names of supported crypto algorithms

Update documentation with correct names of supported algorithms.

Fixes: 1703e94ac5cee ("qat: add driver for QuickAssist devices")
Fixes: 3aafc423cf4d ("snow3g: add driver for SNOW 3G library")
Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto")
Fixes: 2773c86d061a ("crypto/kasumi: add driver for KASUMI library")

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

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doc: add instructions to enable qat

Signed-off-by: Eoin Breen <eoin.breen@intel.com>
Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add NULL capability

Enabled NULL crypto for Intel(R) QuickAssist Technology.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

crypto/qat: add aes-sha384-hmac capability

Enable support of aes-sha384-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.

crypto/qat: add aes-sha384-hmac capability

Enable support of aes-sha384-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

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crypto/qat: add aes-sha224-hmac capability

Added support of aes-sha224-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.t

crypto/qat: add aes-sha224-hmac capability

Added support of aes-sha224-hmac in Intel(R) QuickAssist driver.

Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

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crypto/qat: add MD5 HMAC capability

Added posibility to compute MD5 HMAC digest with Intel QuickAssist
Technology driver.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Signed-off-by: D

crypto/qat: add MD5 HMAC capability

Added posibility to compute MD5 HMAC digest with Intel QuickAssist
Technology driver.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Signed-off-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: Fiona Trahe <fiona.trahe@intel.com>

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drivers: make driver names consistent

As discussed in the past release, driver names are modified
to be more consistent, and the future driver should follow
this new convention.

Driver names consis

drivers: make driver names consistent

As discussed in the past release, driver names are modified
to be more consistent, and the future driver should follow
this new convention.

Driver names consist of:
"driver category"_"driver folder name"_"optional extra name".

For example:
- Crypto null driver -> "crypto_null"
- Network IXGBE VF driver -> "net_ixgbe_vf"

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crypto/kasumi: restrict cipher bit-level operations

KASUMI PMD only supports bit-level cipher operations
when destination buffer is different from the source
(out of place operations). This commit a

crypto/kasumi: restrict cipher bit-level operations

KASUMI PMD only supports bit-level cipher operations
when destination buffer is different from the source
(out of place operations). This commit adds a check
in the code to prevent the user from trying to perform
in-place bit-level ciphering.

Fixes: 2773c86d061a ("crypto/kasumi: add driver for KASUMI library")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crypto/snow3g: support bit-level operations

Underlying libsso_snow3g library now supports bit-level
operations, so PMD has been updated to allow them.

Signed-off-by: Pablo de Lara <pablo.de.lara.gu

crypto/snow3g: support bit-level operations

Underlying libsso_snow3g library now supports bit-level
operations, so PMD has been updated to allow them.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

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doc: update build instructions for libsso_snow3g

With the library update, the way to compile the library
has changed, so documentation reflects this change.
Also, the patch to fix the compilation is

doc: update build instructions for libsso_snow3g

With the library update, the way to compile the library
has changed, so documentation reflects this change.
Also, the patch to fix the compilation issues present with gcc > 5.0
has been removed, as the issues have been fixed in the library.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

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crypto/snow3g: rename libsso reference due to library update

The underlying libsso library that SNOW3G PMD uses has been updated,
so now it is called libsso_snow3g. Also, the path to the library
has

crypto/snow3g: rename libsso reference due to library update

The underlying libsso library that SNOW3G PMD uses has been updated,
so now it is called libsso_snow3g. Also, the path to the library
has been renamed to reflect this changes (now called LIBSSO_SNOW3G_PATH).

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

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crypto/kasumi: add driver for KASUMI library

Added new SW PMD which makes use of the libsso_kasumi SW library,
which provides wireless algorithms KASUMI F8 and F9
in software.

This PMD supports cip

crypto/kasumi: add driver for KASUMI library

Added new SW PMD which makes use of the libsso_kasumi SW library,
which provides wireless algorithms KASUMI F8 and F9
in software.

This PMD supports cipher-only, hash-only and chained operations
("cipher then hash" and "hash then cipher") of the following
algorithms:
- RTE_CRYPTO_SYM_CIPHER_KASUMI_F8
- RTE_CRYPTO_SYM_AUTH_KASUMI_F9

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

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doc: fix crypto feature table

Some crypto PMDs that support symmetric crypto were not marked
as supported in the supported feature flags table.

Fixes: 2373c0661b2f0 ("doc: add cryptodevs guide over

doc: fix crypto feature table

Some crypto PMDs that support symmetric crypto were not marked
as supported in the supported feature flags table.

Fixes: 2373c0661b2f0 ("doc: add cryptodevs guide overview")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>

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aesni_mb: add AES-CTR

This patch provides counter mode support to AES-NI multi-buffer library.

The following cipher algorithm is enabled:
- RTE_CRYPTO_CIPHER_AES_CTR

Signed-off-by: Fan Zhang <roy.

aesni_mb: add AES-CTR

This patch provides counter mode support to AES-NI multi-buffer library.

The following cipher algorithm is enabled:
- RTE_CRYPTO_CIPHER_AES_CTR

Signed-off-by: Fan Zhang <roy.fan.zhang@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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qat: add AES-CTR capability

Added possibility for AES to work in counter mode

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Deepak Kumar Jain <deepak.k.jain@intel.com>

doc: fix supported AES-CBC key lengths

AES-NI MB PMD supports 128, 192 and 256-bit keys,
not 128, 256 and 512-bit keys.

Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto")

S

doc: fix supported AES-CBC key lengths

AES-NI MB PMD supports 128, 192 and 256-bit keys,
not 128, 256 and 512-bit keys.

Fixes: 924e84f87306 ("aesni_mb: add driver for multi buffer based crypto")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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doc: add cryptodevs guide overview

Details supported device features and algorithms for each crypto PMD.

Signed-off-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Pablo de Lara <pablo.de.l

doc: add cryptodevs guide overview

Details supported device features and algorithms for each crypto PMD.

Signed-off-by: Declan Doherty <declan.doherty@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: John McNamara <john.mcnamara@intel.com>

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doc: add initialization section for crypto vdevs

Explain how to create/initialize virtual crypto PMDs,
through command line and within an application.

Signed-off-by: Pablo de Lara <pablo.de.lara.gu

doc: add initialization section for crypto vdevs

Explain how to create/initialize virtual crypto PMDs,
through command line and within an application.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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doc: fix typos in crypto titles

Fixes: eec136f3c54f ("aesni_gcm: add driver for AES-GCM crypto operations")
Fixes: 94b0ad8e0aa5 ("null_crypto: add driver for null crypto operations")

Signed-off-by:

doc: fix typos in crypto titles

Fixes: eec136f3c54f ("aesni_gcm: add driver for AES-GCM crypto operations")
Fixes: 94b0ad8e0aa5 ("null_crypto: add driver for null crypto operations")

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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doc: update libsso link for SNOW 3G

A new process to request the libsso library required by the SNOW3G PMD
has been put in place, through a website, replacing the previous email method.
This commit

doc: update libsso link for SNOW 3G

A new process to request the libsso library required by the SNOW3G PMD
has been put in place, through a website, replacing the previous email method.
This commit updates the SNOW3G documentation, to reflect this change.

Since the library does not support newer gcc versions, the documentation
also contains a patch to make the library work with gcc > 5.0.

Signed-off-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Declan Doherty <declan.doherty@intel.com>

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qat: add out-of-place symmetric operations

This patch adds out-of-place operations to qat symmetric crypto PMD,
i.e. the result of the operation can be written to the destination buffer
instead of o

qat: add out-of-place symmetric operations

This patch adds out-of-place operations to qat symmetric crypto PMD,
i.e. the result of the operation can be written to the destination buffer
instead of overwriting the source buffer as done in "in-place" operation.
Both buffers can be of different sizes.
Previously the qat PMD assumed that m_src and m_dst in rte_crypto_sym_op
were identical.

Signed-off-by: Arek Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: John Griffin <john.griffin@intel.com>

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