1 /*- 2 * BSD LICENSE 3 * 4 * Copyright(c) 2014-2016 Chelsio Communications. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of Chelsio Communications nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/queue.h> 35 #include <stdio.h> 36 #include <errno.h> 37 #include <stdint.h> 38 #include <string.h> 39 #include <unistd.h> 40 #include <stdarg.h> 41 #include <inttypes.h> 42 #include <netinet/in.h> 43 44 #include <rte_byteorder.h> 45 #include <rte_common.h> 46 #include <rte_cycles.h> 47 #include <rte_interrupts.h> 48 #include <rte_log.h> 49 #include <rte_debug.h> 50 #include <rte_pci.h> 51 #include <rte_atomic.h> 52 #include <rte_branch_prediction.h> 53 #include <rte_memory.h> 54 #include <rte_memzone.h> 55 #include <rte_tailq.h> 56 #include <rte_eal.h> 57 #include <rte_alarm.h> 58 #include <rte_ether.h> 59 #include <rte_ethdev.h> 60 #include <rte_atomic.h> 61 #include <rte_malloc.h> 62 #include <rte_random.h> 63 #include <rte_dev.h> 64 65 #include "common.h" 66 #include "t4_regs.h" 67 #include "t4_msg.h" 68 #include "cxgbe.h" 69 70 /* 71 * Response queue handler for the FW event queue. 72 */ 73 static int fwevtq_handler(struct sge_rspq *q, const __be64 *rsp, 74 __rte_unused const struct pkt_gl *gl) 75 { 76 u8 opcode = ((const struct rss_header *)rsp)->opcode; 77 78 rsp++; /* skip RSS header */ 79 80 /* 81 * FW can send EGR_UPDATEs encapsulated in a CPL_FW4_MSG. 82 */ 83 if (unlikely(opcode == CPL_FW4_MSG && 84 ((const struct cpl_fw4_msg *)rsp)->type == 85 FW_TYPE_RSSCPL)) { 86 rsp++; 87 opcode = ((const struct rss_header *)rsp)->opcode; 88 rsp++; 89 if (opcode != CPL_SGE_EGR_UPDATE) { 90 dev_err(q->adapter, "unexpected FW4/CPL %#x on FW event queue\n", 91 opcode); 92 goto out; 93 } 94 } 95 96 if (likely(opcode == CPL_SGE_EGR_UPDATE)) { 97 /* do nothing */ 98 } else if (opcode == CPL_FW6_MSG || opcode == CPL_FW4_MSG) { 99 const struct cpl_fw6_msg *msg = (const void *)rsp; 100 101 t4_handle_fw_rpl(q->adapter, msg->data); 102 } else { 103 dev_err(adapter, "unexpected CPL %#x on FW event queue\n", 104 opcode); 105 } 106 out: 107 return 0; 108 } 109 110 int setup_sge_fwevtq(struct adapter *adapter) 111 { 112 struct sge *s = &adapter->sge; 113 int err = 0; 114 int msi_idx = 0; 115 116 err = t4_sge_alloc_rxq(adapter, &s->fw_evtq, true, adapter->eth_dev, 117 msi_idx, NULL, fwevtq_handler, -1, NULL, 0, 118 rte_socket_id()); 119 return err; 120 } 121 122 static int closest_timer(const struct sge *s, int time) 123 { 124 unsigned int i, match = 0; 125 int delta, min_delta = INT_MAX; 126 127 for (i = 0; i < ARRAY_SIZE(s->timer_val); i++) { 128 delta = time - s->timer_val[i]; 129 if (delta < 0) 130 delta = -delta; 131 if (delta < min_delta) { 132 min_delta = delta; 133 match = i; 134 } 135 } 136 return match; 137 } 138 139 static int closest_thres(const struct sge *s, int thres) 140 { 141 unsigned int i, match = 0; 142 int delta, min_delta = INT_MAX; 143 144 for (i = 0; i < ARRAY_SIZE(s->counter_val); i++) { 145 delta = thres - s->counter_val[i]; 146 if (delta < 0) 147 delta = -delta; 148 if (delta < min_delta) { 149 min_delta = delta; 150 match = i; 151 } 152 } 153 return match; 154 } 155 156 /** 157 * cxgb4_set_rspq_intr_params - set a queue's interrupt holdoff parameters 158 * @q: the Rx queue 159 * @us: the hold-off time in us, or 0 to disable timer 160 * @cnt: the hold-off packet count, or 0 to disable counter 161 * 162 * Sets an Rx queue's interrupt hold-off time and packet count. At least 163 * one of the two needs to be enabled for the queue to generate interrupts. 164 */ 165 int cxgb4_set_rspq_intr_params(struct sge_rspq *q, unsigned int us, 166 unsigned int cnt) 167 { 168 struct adapter *adap = q->adapter; 169 unsigned int timer_val; 170 171 if (cnt) { 172 int err; 173 u32 v, new_idx; 174 175 new_idx = closest_thres(&adap->sge, cnt); 176 if (q->desc && q->pktcnt_idx != new_idx) { 177 /* the queue has already been created, update it */ 178 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) | 179 V_FW_PARAMS_PARAM_X( 180 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH) | 181 V_FW_PARAMS_PARAM_YZ(q->cntxt_id); 182 err = t4_set_params(adap, adap->mbox, adap->pf, 0, 1, 183 &v, &new_idx); 184 if (err) 185 return err; 186 } 187 q->pktcnt_idx = new_idx; 188 } 189 190 timer_val = (us == 0) ? X_TIMERREG_RESTART_COUNTER : 191 closest_timer(&adap->sge, us); 192 193 if ((us | cnt) == 0) 194 q->intr_params = V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX); 195 else 196 q->intr_params = V_QINTR_TIMER_IDX(timer_val) | 197 V_QINTR_CNT_EN(cnt > 0); 198 return 0; 199 } 200 201 static inline bool is_x_1g_port(const struct link_config *lc) 202 { 203 return (lc->supported & FW_PORT_CAP_SPEED_1G) != 0; 204 } 205 206 static inline bool is_x_10g_port(const struct link_config *lc) 207 { 208 return ((lc->supported & FW_PORT_CAP_SPEED_10G) != 0 || 209 (lc->supported & FW_PORT_CAP_SPEED_40G) != 0 || 210 (lc->supported & FW_PORT_CAP_SPEED_100G) != 0); 211 } 212 213 inline void init_rspq(struct adapter *adap, struct sge_rspq *q, 214 unsigned int us, unsigned int cnt, 215 unsigned int size, unsigned int iqe_size) 216 { 217 q->adapter = adap; 218 cxgb4_set_rspq_intr_params(q, us, cnt); 219 q->iqe_len = iqe_size; 220 q->size = size; 221 } 222 223 int cfg_queue_count(struct rte_eth_dev *eth_dev) 224 { 225 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 226 struct adapter *adap = pi->adapter; 227 struct sge *s = &adap->sge; 228 unsigned int max_queues = s->max_ethqsets / adap->params.nports; 229 230 if ((eth_dev->data->nb_rx_queues < 1) || 231 (eth_dev->data->nb_tx_queues < 1)) 232 return -EINVAL; 233 234 if ((eth_dev->data->nb_rx_queues > max_queues) || 235 (eth_dev->data->nb_tx_queues > max_queues)) 236 return -EINVAL; 237 238 if (eth_dev->data->nb_rx_queues > pi->rss_size) 239 return -EINVAL; 240 241 /* We must configure RSS, since config has changed*/ 242 pi->flags &= ~PORT_RSS_DONE; 243 244 pi->n_rx_qsets = eth_dev->data->nb_rx_queues; 245 pi->n_tx_qsets = eth_dev->data->nb_tx_queues; 246 247 return 0; 248 } 249 250 void cfg_queues(struct rte_eth_dev *eth_dev) 251 { 252 struct rte_config *config = rte_eal_get_configuration(); 253 struct port_info *pi = (struct port_info *)(eth_dev->data->dev_private); 254 struct adapter *adap = pi->adapter; 255 struct sge *s = &adap->sge; 256 unsigned int i, nb_ports = 0, qidx = 0; 257 unsigned int q_per_port = 0; 258 259 if (!(adap->flags & CFG_QUEUES)) { 260 for_each_port(adap, i) { 261 struct port_info *tpi = adap2pinfo(adap, i); 262 263 nb_ports += (is_x_10g_port(&tpi->link_cfg)) || 264 is_x_1g_port(&tpi->link_cfg) ? 1 : 0; 265 } 266 267 /* 268 * We default up to # of cores queues per 1G/10G port. 269 */ 270 if (nb_ports) 271 q_per_port = (MAX_ETH_QSETS - 272 (adap->params.nports - nb_ports)) / 273 nb_ports; 274 275 if (q_per_port > config->lcore_count) 276 q_per_port = config->lcore_count; 277 278 for_each_port(adap, i) { 279 struct port_info *pi = adap2pinfo(adap, i); 280 281 pi->first_qset = qidx; 282 283 /* Initially n_rx_qsets == n_tx_qsets */ 284 pi->n_rx_qsets = (is_x_10g_port(&pi->link_cfg) || 285 is_x_1g_port(&pi->link_cfg)) ? 286 q_per_port : 1; 287 pi->n_tx_qsets = pi->n_rx_qsets; 288 289 if (pi->n_rx_qsets > pi->rss_size) 290 pi->n_rx_qsets = pi->rss_size; 291 292 qidx += pi->n_rx_qsets; 293 } 294 295 s->max_ethqsets = qidx; 296 297 for (i = 0; i < ARRAY_SIZE(s->ethrxq); i++) { 298 struct sge_eth_rxq *r = &s->ethrxq[i]; 299 300 init_rspq(adap, &r->rspq, 0, 0, 1024, 64); 301 r->usembufs = 1; 302 r->fl.size = (r->usembufs ? 1024 : 72); 303 } 304 305 for (i = 0; i < ARRAY_SIZE(s->ethtxq); i++) 306 s->ethtxq[i].q.size = 1024; 307 308 init_rspq(adap, &adap->sge.fw_evtq, 0, 0, 1024, 64); 309 adap->flags |= CFG_QUEUES; 310 } 311 } 312 313 void cxgbe_stats_get(struct port_info *pi, struct port_stats *stats) 314 { 315 t4_get_port_stats_offset(pi->adapter, pi->tx_chan, stats, 316 &pi->stats_base); 317 } 318 319 void cxgbe_stats_reset(struct port_info *pi) 320 { 321 t4_clr_port_stats(pi->adapter, pi->tx_chan); 322 } 323 324 static void setup_memwin(struct adapter *adap) 325 { 326 u32 mem_win0_base; 327 328 /* For T5, only relative offset inside the PCIe BAR is passed */ 329 mem_win0_base = MEMWIN0_BASE; 330 331 /* 332 * Set up memory window for accessing adapter memory ranges. (Read 333 * back MA register to ensure that changes propagate before we attempt 334 * to use the new values.) 335 */ 336 t4_write_reg(adap, 337 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 338 MEMWIN_NIC), 339 mem_win0_base | V_BIR(0) | 340 V_WINDOW(ilog2(MEMWIN0_APERTURE) - X_WINDOW_SHIFT)); 341 t4_read_reg(adap, 342 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 343 MEMWIN_NIC)); 344 } 345 346 static int init_rss(struct adapter *adap) 347 { 348 unsigned int i; 349 int err; 350 351 err = t4_init_rss_mode(adap, adap->mbox); 352 if (err) 353 return err; 354 355 for_each_port(adap, i) { 356 struct port_info *pi = adap2pinfo(adap, i); 357 358 pi->rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 359 if (!pi->rss) 360 return -ENOMEM; 361 } 362 return 0; 363 } 364 365 static void print_port_info(struct adapter *adap) 366 { 367 int i; 368 char buf[80]; 369 struct rte_pci_addr *loc = &adap->pdev->addr; 370 371 for_each_port(adap, i) { 372 const struct port_info *pi = &adap->port[i]; 373 char *bufp = buf; 374 375 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_100M) 376 bufp += sprintf(bufp, "100/"); 377 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_1G) 378 bufp += sprintf(bufp, "1000/"); 379 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) 380 bufp += sprintf(bufp, "10G/"); 381 if (pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) 382 bufp += sprintf(bufp, "40G/"); 383 if (bufp != buf) 384 --bufp; 385 sprintf(bufp, "BASE-%s", 386 t4_get_port_type_description( 387 (enum fw_port_type)pi->port_type)); 388 389 dev_info(adap, 390 " " PCI_PRI_FMT " Chelsio rev %d %s %s\n", 391 loc->domain, loc->bus, loc->devid, loc->function, 392 CHELSIO_CHIP_RELEASE(adap->params.chip), buf, 393 (adap->flags & USING_MSIX) ? " MSI-X" : 394 (adap->flags & USING_MSI) ? " MSI" : ""); 395 } 396 } 397 398 /* 399 * Tweak configuration based on system architecture, etc. Most of these have 400 * defaults assigned to them by Firmware Configuration Files (if we're using 401 * them) but need to be explicitly set if we're using hard-coded 402 * initialization. So these are essentially common tweaks/settings for 403 * Configuration Files and hard-coded initialization ... 404 */ 405 static int adap_init0_tweaks(struct adapter *adapter) 406 { 407 u8 rx_dma_offset; 408 409 /* 410 * Fix up various Host-Dependent Parameters like Page Size, Cache 411 * Line Size, etc. The firmware default is for a 4KB Page Size and 412 * 64B Cache Line Size ... 413 */ 414 t4_fixup_host_params_compat(adapter, CXGBE_PAGE_SIZE, L1_CACHE_BYTES, 415 T5_LAST_REV); 416 417 /* 418 * Keep the chip default offset to deliver Ingress packets into our 419 * DMA buffers to zero 420 */ 421 rx_dma_offset = 0; 422 t4_set_reg_field(adapter, A_SGE_CONTROL, V_PKTSHIFT(M_PKTSHIFT), 423 V_PKTSHIFT(rx_dma_offset)); 424 425 t4_set_reg_field(adapter, A_SGE_FLM_CFG, 426 V_CREDITCNT(M_CREDITCNT) | M_CREDITCNTPACKING, 427 V_CREDITCNT(3) | V_CREDITCNTPACKING(1)); 428 429 t4_set_reg_field(adapter, A_SGE_CONTROL2, V_IDMAARBROUNDROBIN(1U), 430 V_IDMAARBROUNDROBIN(1U)); 431 432 /* 433 * Don't include the "IP Pseudo Header" in CPL_RX_PKT checksums: Linux 434 * adds the pseudo header itself. 435 */ 436 t4_tp_wr_bits_indirect(adapter, A_TP_INGRESS_CONFIG, 437 F_CSUM_HAS_PSEUDO_HDR, 0); 438 439 return 0; 440 } 441 442 /* 443 * Attempt to initialize the adapter via a Firmware Configuration File. 444 */ 445 static int adap_init0_config(struct adapter *adapter, int reset) 446 { 447 struct fw_caps_config_cmd caps_cmd; 448 unsigned long mtype = 0, maddr = 0; 449 u32 finiver, finicsum, cfcsum; 450 int ret; 451 int config_issued = 0; 452 int cfg_addr; 453 char config_name[20]; 454 455 /* 456 * Reset device if necessary. 457 */ 458 if (reset) { 459 ret = t4_fw_reset(adapter, adapter->mbox, 460 F_PIORSTMODE | F_PIORST); 461 if (ret < 0) { 462 dev_warn(adapter, "Firmware reset failed, error %d\n", 463 -ret); 464 goto bye; 465 } 466 } 467 468 cfg_addr = t4_flash_cfg_addr(adapter); 469 if (cfg_addr < 0) { 470 ret = cfg_addr; 471 dev_warn(adapter, "Finding address for firmware config file in flash failed, error %d\n", 472 -ret); 473 goto bye; 474 } 475 476 strcpy(config_name, "On Flash"); 477 mtype = FW_MEMTYPE_CF_FLASH; 478 maddr = cfg_addr; 479 480 /* 481 * Issue a Capability Configuration command to the firmware to get it 482 * to parse the Configuration File. We don't use t4_fw_config_file() 483 * because we want the ability to modify various features after we've 484 * processed the configuration file ... 485 */ 486 memset(&caps_cmd, 0, sizeof(caps_cmd)); 487 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 488 F_FW_CMD_REQUEST | F_FW_CMD_READ); 489 caps_cmd.cfvalid_to_len16 = 490 cpu_to_be32(F_FW_CAPS_CONFIG_CMD_CFVALID | 491 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) | 492 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(maddr >> 16) | 493 FW_LEN16(caps_cmd)); 494 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 495 &caps_cmd); 496 /* 497 * If the CAPS_CONFIG failed with an ENOENT (for a Firmware 498 * Configuration File in FLASH), our last gasp effort is to use the 499 * Firmware Configuration File which is embedded in the firmware. A 500 * very few early versions of the firmware didn't have one embedded 501 * but we can ignore those. 502 */ 503 if (ret == -ENOENT) { 504 dev_info(adapter, "%s: Going for embedded config in firmware..\n", 505 __func__); 506 507 memset(&caps_cmd, 0, sizeof(caps_cmd)); 508 caps_cmd.op_to_write = 509 cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 510 F_FW_CMD_REQUEST | F_FW_CMD_READ); 511 caps_cmd.cfvalid_to_len16 = cpu_to_be32(FW_LEN16(caps_cmd)); 512 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, 513 sizeof(caps_cmd), &caps_cmd); 514 strcpy(config_name, "Firmware Default"); 515 } 516 517 config_issued = 1; 518 if (ret < 0) 519 goto bye; 520 521 finiver = be32_to_cpu(caps_cmd.finiver); 522 finicsum = be32_to_cpu(caps_cmd.finicsum); 523 cfcsum = be32_to_cpu(caps_cmd.cfcsum); 524 if (finicsum != cfcsum) 525 dev_warn(adapter, "Configuration File checksum mismatch: [fini] csum=%#x, computed csum=%#x\n", 526 finicsum, cfcsum); 527 528 /* 529 * If we're a pure NIC driver then disable all offloading facilities. 530 * This will allow the firmware to optimize aspects of the hardware 531 * configuration which will result in improved performance. 532 */ 533 caps_cmd.niccaps &= cpu_to_be16(~(FW_CAPS_CONFIG_NIC_HASHFILTER | 534 FW_CAPS_CONFIG_NIC_ETHOFLD)); 535 caps_cmd.toecaps = 0; 536 caps_cmd.iscsicaps = 0; 537 caps_cmd.rdmacaps = 0; 538 caps_cmd.fcoecaps = 0; 539 540 /* 541 * And now tell the firmware to use the configuration we just loaded. 542 */ 543 caps_cmd.op_to_write = cpu_to_be32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) | 544 F_FW_CMD_REQUEST | F_FW_CMD_WRITE); 545 caps_cmd.cfvalid_to_len16 = htonl(FW_LEN16(caps_cmd)); 546 ret = t4_wr_mbox(adapter, adapter->mbox, &caps_cmd, sizeof(caps_cmd), 547 NULL); 548 if (ret < 0) { 549 dev_warn(adapter, "Unable to finalize Firmware Capabilities %d\n", 550 -ret); 551 goto bye; 552 } 553 554 /* 555 * Tweak configuration based on system architecture, etc. 556 */ 557 ret = adap_init0_tweaks(adapter); 558 if (ret < 0) { 559 dev_warn(adapter, "Unable to do init0-tweaks %d\n", -ret); 560 goto bye; 561 } 562 563 /* 564 * And finally tell the firmware to initialize itself using the 565 * parameters from the Configuration File. 566 */ 567 ret = t4_fw_initialize(adapter, adapter->mbox); 568 if (ret < 0) { 569 dev_warn(adapter, "Initializing Firmware failed, error %d\n", 570 -ret); 571 goto bye; 572 } 573 574 /* 575 * Return successfully and note that we're operating with parameters 576 * not supplied by the driver, rather than from hard-wired 577 * initialization constants burried in the driver. 578 */ 579 dev_info(adapter, 580 "Successfully configured using Firmware Configuration File \"%s\", version %#x, computed checksum %#x\n", 581 config_name, finiver, cfcsum); 582 583 return 0; 584 585 /* 586 * Something bad happened. Return the error ... (If the "error" 587 * is that there's no Configuration File on the adapter we don't 588 * want to issue a warning since this is fairly common.) 589 */ 590 bye: 591 if (config_issued && ret != -ENOENT) 592 dev_warn(adapter, "\"%s\" configuration file error %d\n", 593 config_name, -ret); 594 595 dev_debug(adapter, "%s: returning ret = %d ..\n", __func__, ret); 596 return ret; 597 } 598 599 static int adap_init0(struct adapter *adap) 600 { 601 int ret = 0; 602 u32 v, port_vec; 603 enum dev_state state; 604 u32 params[7], val[7]; 605 int reset = 1; 606 int mbox = adap->mbox; 607 608 /* 609 * Contact FW, advertising Master capability. 610 */ 611 ret = t4_fw_hello(adap, adap->mbox, adap->mbox, MASTER_MAY, &state); 612 if (ret < 0) { 613 dev_err(adap, "%s: could not connect to FW, error %d\n", 614 __func__, -ret); 615 goto bye; 616 } 617 618 CXGBE_DEBUG_MBOX(adap, "%s: adap->mbox = %d; ret = %d\n", __func__, 619 adap->mbox, ret); 620 621 if (ret == mbox) 622 adap->flags |= MASTER_PF; 623 624 if (state == DEV_STATE_INIT) { 625 /* 626 * Force halt and reset FW because a previous instance may have 627 * exited abnormally without properly shutting down 628 */ 629 ret = t4_fw_halt(adap, adap->mbox, reset); 630 if (ret < 0) { 631 dev_err(adap, "Failed to halt. Exit.\n"); 632 goto bye; 633 } 634 635 ret = t4_fw_restart(adap, adap->mbox, reset); 636 if (ret < 0) { 637 dev_err(adap, "Failed to restart. Exit.\n"); 638 goto bye; 639 } 640 state = (enum dev_state)((unsigned)state & ~DEV_STATE_INIT); 641 } 642 643 t4_get_fw_version(adap, &adap->params.fw_vers); 644 t4_get_tp_version(adap, &adap->params.tp_vers); 645 646 dev_info(adap, "fw: %u.%u.%u.%u, TP: %u.%u.%u.%u\n", 647 G_FW_HDR_FW_VER_MAJOR(adap->params.fw_vers), 648 G_FW_HDR_FW_VER_MINOR(adap->params.fw_vers), 649 G_FW_HDR_FW_VER_MICRO(adap->params.fw_vers), 650 G_FW_HDR_FW_VER_BUILD(adap->params.fw_vers), 651 G_FW_HDR_FW_VER_MAJOR(adap->params.tp_vers), 652 G_FW_HDR_FW_VER_MINOR(adap->params.tp_vers), 653 G_FW_HDR_FW_VER_MICRO(adap->params.tp_vers), 654 G_FW_HDR_FW_VER_BUILD(adap->params.tp_vers)); 655 656 ret = t4_get_core_clock(adap, &adap->params.vpd); 657 if (ret < 0) { 658 dev_err(adap, "%s: could not get core clock, error %d\n", 659 __func__, -ret); 660 goto bye; 661 } 662 663 /* 664 * Find out what ports are available to us. Note that we need to do 665 * this before calling adap_init0_no_config() since it needs nports 666 * and portvec ... 667 */ 668 v = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | 669 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_PORTVEC); 670 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, &v, &port_vec); 671 if (ret < 0) { 672 dev_err(adap, "%s: failure in t4_queury_params; error = %d\n", 673 __func__, ret); 674 goto bye; 675 } 676 677 adap->params.nports = hweight32(port_vec); 678 adap->params.portvec = port_vec; 679 680 dev_debug(adap, "%s: adap->params.nports = %u\n", __func__, 681 adap->params.nports); 682 683 /* 684 * If the firmware is initialized already (and we're not forcing a 685 * master initialization), note that we're living with existing 686 * adapter parameters. Otherwise, it's time to try initializing the 687 * adapter ... 688 */ 689 if (state == DEV_STATE_INIT) { 690 dev_info(adap, "Coming up as %s: Adapter already initialized\n", 691 adap->flags & MASTER_PF ? "MASTER" : "SLAVE"); 692 } else { 693 dev_info(adap, "Coming up as MASTER: Initializing adapter\n"); 694 695 ret = adap_init0_config(adap, reset); 696 if (ret == -ENOENT) { 697 dev_err(adap, 698 "No Configuration File present on adapter. Using hard-wired configuration parameters.\n"); 699 goto bye; 700 } 701 } 702 if (ret < 0) { 703 dev_err(adap, "could not initialize adapter, error %d\n", -ret); 704 goto bye; 705 } 706 707 /* 708 * Give the SGE code a chance to pull in anything that it needs ... 709 * Note that this must be called after we retrieve our VPD parameters 710 * in order to know how to convert core ticks to seconds, etc. 711 */ 712 ret = t4_sge_init(adap); 713 if (ret < 0) { 714 dev_err(adap, "t4_sge_init failed with error %d\n", 715 -ret); 716 goto bye; 717 } 718 719 /* 720 * Grab some of our basic fundamental operating parameters. 721 */ 722 #define FW_PARAM_DEV(param) \ 723 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \ 724 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param)) 725 726 #define FW_PARAM_PFVF(param) \ 727 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \ 728 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param) | \ 729 V_FW_PARAMS_PARAM_Y(0) | \ 730 V_FW_PARAMS_PARAM_Z(0)) 731 732 /* If we're running on newer firmware, let it know that we're 733 * prepared to deal with encapsulated CPL messages. Older 734 * firmware won't understand this and we'll just get 735 * unencapsulated messages ... 736 */ 737 params[0] = FW_PARAM_PFVF(CPLFW4MSG_ENCAP); 738 val[0] = 1; 739 (void)t4_set_params(adap, adap->mbox, adap->pf, 0, 1, params, val); 740 741 /* 742 * Find out whether we're allowed to use the T5+ ULPTX MEMWRITE DSGL 743 * capability. Earlier versions of the firmware didn't have the 744 * ULPTX_MEMWRITE_DSGL so we'll interpret a query failure as no 745 * permission to use ULPTX MEMWRITE DSGL. 746 */ 747 if (is_t4(adap->params.chip)) { 748 adap->params.ulptx_memwrite_dsgl = false; 749 } else { 750 params[0] = FW_PARAM_DEV(ULPTX_MEMWRITE_DSGL); 751 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 752 1, params, val); 753 adap->params.ulptx_memwrite_dsgl = (ret == 0 && val[0] != 0); 754 } 755 756 /* 757 * The MTU/MSS Table is initialized by now, so load their values. If 758 * we're initializing the adapter, then we'll make any modifications 759 * we want to the MTU/MSS Table and also initialize the congestion 760 * parameters. 761 */ 762 t4_read_mtu_tbl(adap, adap->params.mtus, NULL); 763 if (state != DEV_STATE_INIT) { 764 int i; 765 766 /* 767 * The default MTU Table contains values 1492 and 1500. 768 * However, for TCP, it's better to have two values which are 769 * a multiple of 8 +/- 4 bytes apart near this popular MTU. 770 * This allows us to have a TCP Data Payload which is a 771 * multiple of 8 regardless of what combination of TCP Options 772 * are in use (always a multiple of 4 bytes) which is 773 * important for performance reasons. For instance, if no 774 * options are in use, then we have a 20-byte IP header and a 775 * 20-byte TCP header. In this case, a 1500-byte MSS would 776 * result in a TCP Data Payload of 1500 - 40 == 1460 bytes 777 * which is not a multiple of 8. So using an MSS of 1488 in 778 * this case results in a TCP Data Payload of 1448 bytes which 779 * is a multiple of 8. On the other hand, if 12-byte TCP Time 780 * Stamps have been negotiated, then an MTU of 1500 bytes 781 * results in a TCP Data Payload of 1448 bytes which, as 782 * above, is a multiple of 8 bytes ... 783 */ 784 for (i = 0; i < NMTUS; i++) 785 if (adap->params.mtus[i] == 1492) { 786 adap->params.mtus[i] = 1488; 787 break; 788 } 789 790 t4_load_mtus(adap, adap->params.mtus, adap->params.a_wnd, 791 adap->params.b_wnd); 792 } 793 t4_init_sge_params(adap); 794 t4_init_tp_params(adap); 795 796 adap->params.drv_memwin = MEMWIN_NIC; 797 adap->flags |= FW_OK; 798 dev_debug(adap, "%s: returning zero..\n", __func__); 799 return 0; 800 801 /* 802 * Something bad happened. If a command timed out or failed with EIO 803 * FW does not operate within its spec or something catastrophic 804 * happened to HW/FW, stop issuing commands. 805 */ 806 bye: 807 if (ret != -ETIMEDOUT && ret != -EIO) 808 t4_fw_bye(adap, adap->mbox); 809 return ret; 810 } 811 812 /** 813 * t4_os_portmod_changed - handle port module changes 814 * @adap: the adapter associated with the module change 815 * @port_id: the port index whose module status has changed 816 * 817 * This is the OS-dependent handler for port module changes. It is 818 * invoked when a port module is removed or inserted for any OS-specific 819 * processing. 820 */ 821 void t4_os_portmod_changed(const struct adapter *adap, int port_id) 822 { 823 static const char * const mod_str[] = { 824 NULL, "LR", "SR", "ER", "passive DA", "active DA", "LRM" 825 }; 826 827 const struct port_info *pi = &adap->port[port_id]; 828 829 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE) 830 dev_info(adap, "Port%d: port module unplugged\n", pi->port_id); 831 else if (pi->mod_type < ARRAY_SIZE(mod_str)) 832 dev_info(adap, "Port%d: %s port module inserted\n", pi->port_id, 833 mod_str[pi->mod_type]); 834 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED) 835 dev_info(adap, "Port%d: unsupported optical port module inserted\n", 836 pi->port_id); 837 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN) 838 dev_info(adap, "Port%d: unknown port module inserted, forcing TWINAX\n", 839 pi->port_id); 840 else if (pi->mod_type == FW_PORT_MOD_TYPE_ERROR) 841 dev_info(adap, "Port%d: transceiver module error\n", 842 pi->port_id); 843 else 844 dev_info(adap, "Port%d: unknown module type %d inserted\n", 845 pi->port_id, pi->mod_type); 846 } 847 848 /** 849 * link_start - enable a port 850 * @dev: the port to enable 851 * 852 * Performs the MAC and PHY actions needed to enable a port. 853 */ 854 int link_start(struct port_info *pi) 855 { 856 struct adapter *adapter = pi->adapter; 857 int ret; 858 unsigned int mtu; 859 860 mtu = pi->eth_dev->data->dev_conf.rxmode.max_rx_pkt_len - 861 (ETHER_HDR_LEN + ETHER_CRC_LEN); 862 863 /* 864 * We do not set address filters and promiscuity here, the stack does 865 * that step explicitly. 866 */ 867 ret = t4_set_rxmode(adapter, adapter->mbox, pi->viid, mtu, -1, -1, 868 -1, 1, true); 869 if (ret == 0) { 870 ret = t4_change_mac(adapter, adapter->mbox, pi->viid, 871 pi->xact_addr_filt, 872 (u8 *)&pi->eth_dev->data->mac_addrs[0], 873 true, true); 874 if (ret >= 0) { 875 pi->xact_addr_filt = ret; 876 ret = 0; 877 } 878 } 879 if (ret == 0) 880 ret = t4_link_l1cfg(adapter, adapter->mbox, pi->tx_chan, 881 &pi->link_cfg); 882 if (ret == 0) { 883 /* 884 * Enabling a Virtual Interface can result in an interrupt 885 * during the processing of the VI Enable command and, in some 886 * paths, result in an attempt to issue another command in the 887 * interrupt context. Thus, we disable interrupts during the 888 * course of the VI Enable command ... 889 */ 890 ret = t4_enable_vi_params(adapter, adapter->mbox, pi->viid, 891 true, true, false); 892 } 893 return ret; 894 } 895 896 /** 897 * cxgb4_write_rss - write the RSS table for a given port 898 * @pi: the port 899 * @queues: array of queue indices for RSS 900 * 901 * Sets up the portion of the HW RSS table for the port's VI to distribute 902 * packets to the Rx queues in @queues. 903 */ 904 int cxgb4_write_rss(const struct port_info *pi, const u16 *queues) 905 { 906 u16 *rss; 907 int i, err; 908 struct adapter *adapter = pi->adapter; 909 const struct sge_eth_rxq *rxq; 910 911 /* Should never be called before setting up sge eth rx queues */ 912 BUG_ON(!(adapter->flags & FULL_INIT_DONE)); 913 914 rxq = &adapter->sge.ethrxq[pi->first_qset]; 915 rss = rte_zmalloc(NULL, pi->rss_size * sizeof(u16), 0); 916 if (!rss) 917 return -ENOMEM; 918 919 /* map the queue indices to queue ids */ 920 for (i = 0; i < pi->rss_size; i++, queues++) 921 rss[i] = rxq[*queues].rspq.abs_id; 922 923 err = t4_config_rss_range(adapter, adapter->pf, pi->viid, 0, 924 pi->rss_size, rss, pi->rss_size); 925 /* 926 * If Tunnel All Lookup isn't specified in the global RSS 927 * Configuration, then we need to specify a default Ingress 928 * Queue for any ingress packets which aren't hashed. We'll 929 * use our first ingress queue ... 930 */ 931 if (!err) 932 err = t4_config_vi_rss(adapter, adapter->mbox, pi->viid, 933 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN | 934 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN | 935 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN | 936 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | 937 F_FW_RSS_VI_CONFIG_CMD_UDPEN, 938 rss[0]); 939 rte_free(rss); 940 return err; 941 } 942 943 /** 944 * setup_rss - configure RSS 945 * @adapter: the adapter 946 * 947 * Sets up RSS to distribute packets to multiple receive queues. We 948 * configure the RSS CPU lookup table to distribute to the number of HW 949 * receive queues, and the response queue lookup table to narrow that 950 * down to the response queues actually configured for each port. 951 * We always configure the RSS mapping for all ports since the mapping 952 * table has plenty of entries. 953 */ 954 int setup_rss(struct port_info *pi) 955 { 956 int j, err; 957 struct adapter *adapter = pi->adapter; 958 959 dev_debug(adapter, "%s: pi->rss_size = %u; pi->n_rx_qsets = %u\n", 960 __func__, pi->rss_size, pi->n_rx_qsets); 961 962 if (!pi->flags & PORT_RSS_DONE) { 963 if (adapter->flags & FULL_INIT_DONE) { 964 /* Fill default values with equal distribution */ 965 for (j = 0; j < pi->rss_size; j++) 966 pi->rss[j] = j % pi->n_rx_qsets; 967 968 err = cxgb4_write_rss(pi, pi->rss); 969 if (err) 970 return err; 971 pi->flags |= PORT_RSS_DONE; 972 } 973 } 974 return 0; 975 } 976 977 /* 978 * Enable NAPI scheduling and interrupt generation for all Rx queues. 979 */ 980 static void enable_rx(struct adapter *adap) 981 { 982 struct sge *s = &adap->sge; 983 struct sge_rspq *q = &s->fw_evtq; 984 int i, j; 985 986 /* 0-increment GTS to start the timer and enable interrupts */ 987 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS), 988 V_SEINTARM(q->intr_params) | 989 V_INGRESSQID(q->cntxt_id)); 990 991 for_each_port(adap, i) { 992 const struct port_info *pi = &adap->port[i]; 993 struct rte_eth_dev *eth_dev = pi->eth_dev; 994 995 for (j = 0; j < eth_dev->data->nb_rx_queues; j++) { 996 q = eth_dev->data->rx_queues[j]; 997 998 /* 999 * 0-increment GTS to start the timer and enable 1000 * interrupts 1001 */ 1002 t4_write_reg(adap, MYPF_REG(A_SGE_PF_GTS), 1003 V_SEINTARM(q->intr_params) | 1004 V_INGRESSQID(q->cntxt_id)); 1005 } 1006 } 1007 } 1008 1009 /** 1010 * cxgb_up - enable the adapter 1011 * @adap: adapter being enabled 1012 * 1013 * Called when the first port is enabled, this function performs the 1014 * actions necessary to make an adapter operational, such as completing 1015 * the initialization of HW modules, and enabling interrupts. 1016 */ 1017 int cxgbe_up(struct adapter *adap) 1018 { 1019 enable_rx(adap); 1020 t4_sge_tx_monitor_start(adap); 1021 t4_intr_enable(adap); 1022 adap->flags |= FULL_INIT_DONE; 1023 1024 /* TODO: deadman watchdog ?? */ 1025 return 0; 1026 } 1027 1028 /* 1029 * Close the port 1030 */ 1031 int cxgbe_down(struct port_info *pi) 1032 { 1033 struct adapter *adapter = pi->adapter; 1034 int err = 0; 1035 1036 err = t4_enable_vi(adapter, adapter->mbox, pi->viid, false, false); 1037 if (err) { 1038 dev_err(adapter, "%s: disable_vi failed: %d\n", __func__, err); 1039 return err; 1040 } 1041 1042 t4_reset_link_config(adapter, pi->port_id); 1043 return 0; 1044 } 1045 1046 /* 1047 * Release resources when all the ports have been stopped. 1048 */ 1049 void cxgbe_close(struct adapter *adapter) 1050 { 1051 struct port_info *pi; 1052 int i; 1053 1054 if (adapter->flags & FULL_INIT_DONE) { 1055 t4_intr_disable(adapter); 1056 t4_sge_tx_monitor_stop(adapter); 1057 t4_free_sge_resources(adapter); 1058 for_each_port(adapter, i) { 1059 pi = adap2pinfo(adapter, i); 1060 if (pi->viid != 0) 1061 t4_free_vi(adapter, adapter->mbox, 1062 adapter->pf, 0, pi->viid); 1063 rte_free(pi->eth_dev->data->mac_addrs); 1064 } 1065 adapter->flags &= ~FULL_INIT_DONE; 1066 } 1067 1068 if (adapter->flags & FW_OK) 1069 t4_fw_bye(adapter, adapter->mbox); 1070 } 1071 1072 int cxgbe_probe(struct adapter *adapter) 1073 { 1074 struct port_info *pi; 1075 int func, i; 1076 int err = 0; 1077 1078 func = G_SOURCEPF(t4_read_reg(adapter, A_PL_WHOAMI)); 1079 adapter->mbox = func; 1080 adapter->pf = func; 1081 1082 t4_os_lock_init(&adapter->mbox_lock); 1083 TAILQ_INIT(&adapter->mbox_list); 1084 1085 err = t4_prep_adapter(adapter); 1086 if (err) 1087 return err; 1088 1089 setup_memwin(adapter); 1090 err = adap_init0(adapter); 1091 if (err) { 1092 dev_err(adapter, "%s: Adapter initialization failed, error %d\n", 1093 __func__, err); 1094 goto out_free; 1095 } 1096 1097 if (!is_t4(adapter->params.chip)) { 1098 /* 1099 * The userspace doorbell BAR is split evenly into doorbell 1100 * regions, each associated with an egress queue. If this 1101 * per-queue region is large enough (at least UDBS_SEG_SIZE) 1102 * then it can be used to submit a tx work request with an 1103 * implied doorbell. Enable write combining on the BAR if 1104 * there is room for such work requests. 1105 */ 1106 int s_qpp, qpp, num_seg; 1107 1108 s_qpp = (S_QUEUESPERPAGEPF0 + 1109 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * 1110 adapter->pf); 1111 qpp = 1 << ((t4_read_reg(adapter, 1112 A_SGE_EGRESS_QUEUES_PER_PAGE_PF) >> s_qpp) 1113 & M_QUEUESPERPAGEPF0); 1114 num_seg = CXGBE_PAGE_SIZE / UDBS_SEG_SIZE; 1115 if (qpp > num_seg) 1116 dev_warn(adapter, "Incorrect SGE EGRESS QUEUES_PER_PAGE configuration, continuing in debug mode\n"); 1117 1118 adapter->bar2 = (void *)adapter->pdev->mem_resource[2].addr; 1119 if (!adapter->bar2) { 1120 dev_err(adapter, "cannot map device bar2 region\n"); 1121 err = -ENOMEM; 1122 goto out_free; 1123 } 1124 t4_write_reg(adapter, A_SGE_STAT_CFG, V_STATSOURCE_T5(7) | 1125 V_STATMODE(0)); 1126 } 1127 1128 for_each_port(adapter, i) { 1129 char name[RTE_ETH_NAME_MAX_LEN]; 1130 struct rte_eth_dev_data *data = NULL; 1131 const unsigned int numa_node = rte_socket_id(); 1132 1133 pi = &adapter->port[i]; 1134 pi->adapter = adapter; 1135 pi->xact_addr_filt = -1; 1136 pi->port_id = i; 1137 1138 snprintf(name, sizeof(name), "cxgbe%d", 1139 adapter->eth_dev->data->port_id + i); 1140 1141 if (i == 0) { 1142 /* First port is already allocated by DPDK */ 1143 pi->eth_dev = adapter->eth_dev; 1144 goto allocate_mac; 1145 } 1146 1147 /* 1148 * now do all data allocation - for eth_dev structure, 1149 * and internal (private) data for the remaining ports 1150 */ 1151 1152 /* reserve an ethdev entry */ 1153 pi->eth_dev = rte_eth_dev_allocate(name, RTE_ETH_DEV_PCI); 1154 if (!pi->eth_dev) 1155 goto out_free; 1156 1157 data = rte_zmalloc_socket(name, sizeof(*data), 0, numa_node); 1158 if (!data) 1159 goto out_free; 1160 1161 data->port_id = adapter->eth_dev->data->port_id + i; 1162 1163 pi->eth_dev->data = data; 1164 1165 allocate_mac: 1166 pi->eth_dev->pci_dev = adapter->pdev; 1167 pi->eth_dev->data->dev_private = pi; 1168 pi->eth_dev->driver = adapter->eth_dev->driver; 1169 pi->eth_dev->dev_ops = adapter->eth_dev->dev_ops; 1170 pi->eth_dev->tx_pkt_burst = adapter->eth_dev->tx_pkt_burst; 1171 pi->eth_dev->rx_pkt_burst = adapter->eth_dev->rx_pkt_burst; 1172 1173 rte_eth_copy_pci_info(pi->eth_dev, pi->eth_dev->pci_dev); 1174 1175 TAILQ_INIT(&pi->eth_dev->link_intr_cbs); 1176 1177 pi->eth_dev->data->mac_addrs = rte_zmalloc(name, 1178 ETHER_ADDR_LEN, 0); 1179 if (!pi->eth_dev->data->mac_addrs) { 1180 dev_err(adapter, "%s: Mem allocation failed for storing mac addr, aborting\n", 1181 __func__); 1182 err = -1; 1183 goto out_free; 1184 } 1185 } 1186 1187 if (adapter->flags & FW_OK) { 1188 err = t4_port_init(adapter, adapter->mbox, adapter->pf, 0); 1189 if (err) { 1190 dev_err(adapter, "%s: t4_port_init failed with err %d\n", 1191 __func__, err); 1192 goto out_free; 1193 } 1194 } 1195 1196 cfg_queues(adapter->eth_dev); 1197 1198 print_port_info(adapter); 1199 1200 err = init_rss(adapter); 1201 if (err) 1202 goto out_free; 1203 1204 return 0; 1205 1206 out_free: 1207 for_each_port(adapter, i) { 1208 pi = adap2pinfo(adapter, i); 1209 if (pi->viid != 0) 1210 t4_free_vi(adapter, adapter->mbox, adapter->pf, 1211 0, pi->viid); 1212 /* Skip first port since it'll be de-allocated by DPDK */ 1213 if (i == 0) 1214 continue; 1215 if (pi->eth_dev->data) 1216 rte_free(pi->eth_dev->data); 1217 } 1218 1219 if (adapter->flags & FW_OK) 1220 t4_fw_bye(adapter, adapter->mbox); 1221 return -err; 1222 } 1223