1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2016 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #ifndef _ENA_ETHDEV_H_ 35 #define _ENA_ETHDEV_H_ 36 37 #include <rte_pci.h> 38 39 #include "ena_com.h" 40 41 #define ENA_REGS_BAR 0 42 #define ENA_MEM_BAR 2 43 44 #define ENA_MAX_NUM_QUEUES 128 45 46 #define ENA_DEFAULT_TX_SW_DESCS (1024) 47 #define ENA_DEFAULT_TX_HW_DESCS (1024) 48 #define ENA_DEFAULT_RING_SIZE (1024) 49 50 #define ENA_MIN_FRAME_LEN 64 51 52 #define ENA_NAME_MAX_LEN 20 53 #define ENA_IRQNAME_SIZE 40 54 55 #define ENA_PKT_MAX_BUFS 17 56 57 #define ENA_CIRC_COUNT(head, tail, size) \ 58 (((uint16_t)((uint16_t)(head) - (uint16_t)(tail))) & ((size) - 1)) 59 60 #define ENA_CIRC_INC(index, step, size) \ 61 ((uint16_t)(index) + (uint16_t)(step)) 62 #define ENA_CIRC_INC_WRAP(index, step, size) \ 63 (((uint16_t)(index) + (uint16_t)(step)) & ((size) - 1)) 64 65 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) \ 66 ENA_CIRC_INC_WRAP(idx, 1, ring_size) 67 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) \ 68 ENA_CIRC_INC_WRAP(idx, 1, ring_size) 69 70 struct ena_adapter; 71 72 enum ena_ring_type { 73 ENA_RING_TYPE_RX = 1, 74 ENA_RING_TYPE_TX = 2, 75 }; 76 77 struct ena_tx_buffer { 78 struct rte_mbuf *mbuf; 79 unsigned int tx_descs; 80 unsigned int num_of_bufs; 81 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 82 }; 83 84 struct ena_ring { 85 u16 next_to_use; 86 u16 next_to_clean; 87 88 enum ena_ring_type type; 89 enum ena_admin_placement_policy_type tx_mem_queue_type; 90 /* Holds the empty requests for TX OOO completions */ 91 uint16_t *empty_tx_reqs; 92 union { 93 struct ena_tx_buffer *tx_buffer_info; /* contex of tx packet */ 94 struct rte_mbuf **rx_buffer_info; /* contex of rx packet */ 95 }; 96 unsigned int ring_size; /* number of tx/rx_buffer_info's entries */ 97 98 struct ena_com_io_cq *ena_com_io_cq; 99 struct ena_com_io_sq *ena_com_io_sq; 100 101 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS] 102 __rte_cache_aligned; 103 104 struct rte_mempool *mb_pool; 105 unsigned int port_id; 106 unsigned int id; 107 /* Max length PMD can push to device for LLQ */ 108 uint8_t tx_max_header_size; 109 int configured; 110 struct ena_adapter *adapter; 111 } __rte_cache_aligned; 112 113 enum ena_adapter_state { 114 ENA_ADAPTER_STATE_FREE = 0, 115 ENA_ADAPTER_STATE_INIT = 1, 116 ENA_ADAPTER_STATE_RUNNING = 2, 117 ENA_ADAPTER_STATE_STOPPED = 3, 118 ENA_ADAPTER_STATE_CONFIG = 4, 119 }; 120 121 struct ena_driver_stats { 122 rte_atomic64_t ierrors; 123 rte_atomic64_t oerrors; 124 rte_atomic64_t imcasts; 125 rte_atomic64_t rx_nombuf; 126 }; 127 128 /* board specific private data structure */ 129 struct ena_adapter { 130 /* OS defined structs */ 131 struct rte_pci_device *pdev; 132 struct rte_eth_dev_data *rte_eth_dev_data; 133 struct rte_eth_dev *rte_dev; 134 135 struct ena_com_dev ena_dev __rte_cache_aligned; 136 137 /* TX */ 138 struct ena_ring tx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 139 int tx_ring_size; 140 141 /* RX */ 142 struct ena_ring rx_ring[ENA_MAX_NUM_QUEUES] __rte_cache_aligned; 143 int rx_ring_size; 144 145 u16 num_queues; 146 u16 max_mtu; 147 148 int id_number; 149 char name[ENA_NAME_MAX_LEN]; 150 u8 mac_addr[ETHER_ADDR_LEN]; 151 152 void *regs; 153 void *dev_mem_base; 154 155 struct ena_driver_stats *drv_stats; 156 enum ena_adapter_state state; 157 158 }; 159 160 #endif /* _ENA_ETHDEV_H_ */ 161