crypto/ipsec_mb: bump minimum IPsec MB version

AESNI_MB SW PMDs increment Intel IPsec MB version to 1.4.
A minimum IPsec Multi-buffer version of 1.4 or greater is now required
for the 24.11 LTS rele

crypto/ipsec_mb: bump minimum IPsec MB version

AESNI_MB SW PMDs increment Intel IPsec MB version to 1.4.
A minimum IPsec Multi-buffer version of 1.4 or greater is now required
for the 24.11 LTS release.

Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Kai Ji <kai.ji@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>
Acked-by: Wathsala Vithanage <wathsala.vithanage@arm.com>

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cryptodev: add SM4-XTS

Added support for symmetric algorithm SM4-XTS in cryptodev.

Signed-off-by: Hanxiao Li <li.hanxiao@zte.com.cn>
Acked-by: Akhil Goyal <gakhil@marvell.com>

crypto/cnxk: support EdDSA

Support EdDSA crypto algorithm in CNXK PMD.

Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>

crypto/openssl: support EdDSA

Support EdDSA crypto algorithm in OpenSSL PMD.

Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Acked-by: Kai Ji <kai.ji@intel.com>

cryptodev: add EdDSA asymmetric algorithm

Add support for asymmetric EdDSA in cryptodev, as referenced in RFC:
https://datatracker.ietf.org/doc/html/rfc8032

Signed-off-by: Gowrishankar Muthukrishna

cryptodev: add EdDSA asymmetric algorithm

Add support for asymmetric EdDSA in cryptodev, as referenced in RFC:
https://datatracker.ietf.org/doc/html/rfc8032

Signed-off-by: Gowrishankar Muthukrishnan <gmuthukrishn@marvell.com>
Acked-by: Arkadiusz Kusztal <arkadiuszx.kusztal@intel.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

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crypto/ipsec_mb: support SM4 algorithm

This patch introduces SM4 CBC, SM4 ECB and SM4 CTR algorithm support to
the AESNI_MB PMD. SM4 CTR is available in the v2.0 release of
Intel IPsec MB.

Signed-o

crypto/ipsec_mb: support SM4 algorithm

This patch introduces SM4 CBC, SM4 ECB and SM4 CTR algorithm support to
the AESNI_MB PMD. SM4 CTR is available in the v2.0 release of
Intel IPsec MB.

Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crypto/ipsec_mb: support HMAC SM3 algorithm

This patch introduces HMAC SM3 algorithm support to the AESNI_MB PMD.

Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Pablo de Lara <pablo

crypto/ipsec_mb: support HMAC SM3 algorithm

This patch introduces HMAC SM3 algorithm support to the AESNI_MB PMD.

Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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crypto/ipsec_mb: support SM3 algorithm

This patch introduces SM3 algorithm support to the AESNI_MB PMD.

Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.g

crypto/ipsec_mb: support SM3 algorithm

This patch introduces SM3 algorithm support to the AESNI_MB PMD.

Signed-off-by: Brian Dooley <brian.dooley@intel.com>
Acked-by: Pablo de Lara <pablo.de.lara.guarch@intel.com>

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doc: update Arm IPsec-MB dependency version

Updates the tag of Arm IPsec-MB library to SECLIB-IPSEC-2024.07.08
in snow3g and zuc documentation.

Signed-off-by: Wathsala Vithanage <wathsala.vithanage

doc: update Arm IPsec-MB dependency version

Updates the tag of Arm IPsec-MB library to SECLIB-IPSEC-2024.07.08
in snow3g and zuc documentation.

Signed-off-by: Wathsala Vithanage <wathsala.vithanage@arm.com>
Reviewed-by: Dhruv Tripathi <dhruv.tripathi@arm.com>
Acked-by: Jack Bond-Preston <jack.bond-preston@foss.arm.com>

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crypto/mlx5: support IPsec out-of-place mode

The IPsec operation shrinks AAD directly before payload in
enqueue burst and restores the memory in dequeue burst.

This commit adds the support of OOP m

crypto/mlx5: support IPsec out-of-place mode

The IPsec operation shrinks AAD directly before payload in
enqueue burst and restores the memory in dequeue burst.

This commit adds the support of OOP mode follows the
similar strategy.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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crypto/mlx5: optimize AES-GCM IPsec operation

To optimize AES-GCM IPsec operation within crypto/mlx5,
the DPDK API typically supplies AES_GCM AAD/Payload/Digest
in separate locations, potentially di

crypto/mlx5: optimize AES-GCM IPsec operation

To optimize AES-GCM IPsec operation within crypto/mlx5,
the DPDK API typically supplies AES_GCM AAD/Payload/Digest
in separate locations, potentially disrupting their
contiguous layout. In cases where the memory layout fails
to meet hardware (HW) requirements, an UMR WQE is initiated
ahead of the GCM's GGA WQE to establish a continuous
AAD/Payload/Digest virtual memory space for the HW MMU.

For IPsec scenarios, where the memory layout consistently
adheres to the fixed order of AAD/IV/Payload/Digest,
directly shrinking memory for AAD proves more efficient
than preparing a UMR WQE. To address this, a new devarg
"crypto_mode" with mode "ipsec_opt" is introduced in the
commit, offering an optimization hint specifically for
IPsec cases. When enabled, the PMD copies AAD directly
before Payload in the enqueue_burst function instead of
employing the UMR WQE. Subsequently, in the dequeue_burst
function, the overridden IV before Payload is restored
from the GGA WQE. It's crucial for users to avoid utilizing
the input mbuf data during processing.

Signed-off-by: Suanming Mou <suanmingm@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>

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crypto/ionic: add datapath

This defines the main crypto operation enqueue and dequeue handlers.

Signed-off-by: Andrew Boyer <andrew.boyer@amd.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

crypto/ionic: introduce AMD Pensando driver

Introduce a new crypto PMD for AMD Pensando hardware accelerators.
It allows applications running directly on the AMD Pensando DSC
to offload cryptographi

crypto/ionic: introduce AMD Pensando driver

Introduce a new crypto PMD for AMD Pensando hardware accelerators.
It allows applications running directly on the AMD Pensando DSC
to offload cryptographic operations to hardware cryptographic blocks.

Add support for the cryptodevs to the common ionic library.
Add the driver skeleton.
Add a skeleton features list and guide.
Hook the new PMD up to the build.
Update MAINTAINERS.

Signed-off-by: Andrew Boyer <andrew.boyer@amd.com>
Acked-by: Akhil Goyal <gakhil@marvell.com>

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common/cnxk: fix segregation of logs based on module

Originally the logs were segregated under various labels which could be
selectively enabled. It was changed to use 'pmd.common.cnxk' while
changi

common/cnxk: fix segregation of logs based on module

Originally the logs were segregated under various labels which could be
selectively enabled. It was changed to use 'pmd.common.cnxk' while
changing the macro used for registering logging. Address the same by
restoring the segregation.

Current logs:
...
logtype3
pmd.common.cnxk
pmd.common.iavf
...

Changed to:
...
logtype3
pmd.common.cnxk.base
pmd.common.cnxk.crypto
pmd.common.cnxk.dpi
pmd.common.cnxk.esw
pmd.common.cnxk.event
pmd.common.cnxk.flow
pmd.common.cnxk.mbox
pmd.common.cnxk.mempool
pmd.common.cnxk.ml
pmd.common.cnxk.nix
pmd.common.cnxk.ree
pmd.common.cnxk.rep
pmd.common.cnxk.timer
pmd.common.cnxk.tm
pmd.common.iavf
...

Updated documentation also to reflect the same.

Fixes: 233692f550a1 ("dma/cnxk: rework DMA driver")
Cc: stable@dpdk.org

Signed-off-by: Anoob Joseph <anoobj@marvell.com>

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