1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 #include <sys/ioctl.h> 18 19 #include <rte_string_fns.h> 20 #include <rte_byteorder.h> 21 #include <rte_common.h> 22 #include <rte_interrupts.h> 23 #include <rte_log.h> 24 #include <rte_debug.h> 25 #include <rte_pci.h> 26 #include <rte_atomic.h> 27 #include <rte_branch_prediction.h> 28 #include <rte_memory.h> 29 #include <rte_tailq.h> 30 #include <rte_eal.h> 31 #include <rte_alarm.h> 32 #include <rte_ether.h> 33 #include <ethdev_driver.h> 34 #include <rte_malloc.h> 35 #include <rte_ring.h> 36 37 #include <bus_dpaa_driver.h> 38 #include <rte_dpaa_logs.h> 39 #include <dpaa_mempool.h> 40 41 #include <dpaa_ethdev.h> 42 #include <dpaa_rxtx.h> 43 #include <dpaa_flow.h> 44 #include <rte_pmd_dpaa.h> 45 46 #include <fsl_usd.h> 47 #include <fsl_qman.h> 48 #include <fsl_bman.h> 49 #include <fsl_fman.h> 50 #include <process.h> 51 #include <fmlib/fm_ext.h> 52 53 #define CHECK_INTERVAL 100 /* 100ms */ 54 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 55 56 /* Supported Rx offloads */ 57 static uint64_t dev_rx_offloads_sup = 58 RTE_ETH_RX_OFFLOAD_SCATTER; 59 60 /* Rx offloads which cannot be disabled */ 61 static uint64_t dev_rx_offloads_nodis = 62 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 63 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 64 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 65 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 66 RTE_ETH_RX_OFFLOAD_RSS_HASH; 67 68 /* Supported Tx offloads */ 69 static uint64_t dev_tx_offloads_sup = 70 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 71 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 72 73 /* Tx offloads which cannot be disabled */ 74 static uint64_t dev_tx_offloads_nodis = 75 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 76 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 77 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 78 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 79 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 80 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 81 82 /* Keep track of whether QMAN and BMAN have been globally initialized */ 83 static int is_global_init; 84 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 85 static int default_q; /* use default queue - FMC is not executed*/ 86 /* At present we only allow up to 4 push mode queues as default - as each of 87 * this queue need dedicated portal and we are short of portals. 88 */ 89 #define DPAA_MAX_PUSH_MODE_QUEUE 8 90 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 91 92 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 93 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 94 95 96 /* Per RX FQ Taildrop in frame count */ 97 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 98 99 /* Per TX FQ Taildrop in frame count, disabled by default */ 100 static unsigned int td_tx_threshold; 101 102 struct rte_dpaa_xstats_name_off { 103 char name[RTE_ETH_XSTATS_NAME_SIZE]; 104 uint32_t offset; 105 }; 106 107 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 108 {"rx_align_err", 109 offsetof(struct dpaa_if_stats, raln)}, 110 {"rx_valid_pause", 111 offsetof(struct dpaa_if_stats, rxpf)}, 112 {"rx_fcs_err", 113 offsetof(struct dpaa_if_stats, rfcs)}, 114 {"rx_vlan_frame", 115 offsetof(struct dpaa_if_stats, rvlan)}, 116 {"rx_frame_err", 117 offsetof(struct dpaa_if_stats, rerr)}, 118 {"rx_drop_err", 119 offsetof(struct dpaa_if_stats, rdrp)}, 120 {"rx_undersized", 121 offsetof(struct dpaa_if_stats, rund)}, 122 {"rx_oversize_err", 123 offsetof(struct dpaa_if_stats, rovr)}, 124 {"rx_fragment_pkt", 125 offsetof(struct dpaa_if_stats, rfrg)}, 126 {"tx_valid_pause", 127 offsetof(struct dpaa_if_stats, txpf)}, 128 {"tx_fcs_err", 129 offsetof(struct dpaa_if_stats, terr)}, 130 {"tx_vlan_frame", 131 offsetof(struct dpaa_if_stats, tvlan)}, 132 {"rx_undersized", 133 offsetof(struct dpaa_if_stats, tund)}, 134 }; 135 136 static struct rte_dpaa_driver rte_dpaa_pmd; 137 int dpaa_valid_dev; 138 struct rte_mempool *dpaa_tx_sg_pool; 139 140 static int 141 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 142 143 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 144 int wait_to_complete __rte_unused); 145 146 static void dpaa_interrupt_handler(void *param); 147 148 static inline void 149 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 150 { 151 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 152 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 153 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 154 QM_FQCTRL_PREFERINCACHE; 155 opts->fqd.context_a.stashing.exclusive = 0; 156 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 157 opts->fqd.context_a.stashing.annotation_cl = 158 DPAA_IF_RX_ANNOTATION_STASH; 159 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 160 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 161 } 162 163 static int 164 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 165 { 166 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 167 + VLAN_TAG_SIZE; 168 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 169 struct fman_if *fif = dev->process_private; 170 171 PMD_INIT_FUNC_TRACE(); 172 173 if (fif->is_shared_mac) { 174 DPAA_PMD_ERR("Cannot configure mtu from DPDK in VSP mode."); 175 return -ENOTSUP; 176 } 177 178 /* 179 * Refuse mtu that requires the support of scattered packets 180 * when this feature has not been enabled before. 181 */ 182 if (dev->data->min_rx_buf_size && 183 !dev->data->scattered_rx && frame_size > buffsz) { 184 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 185 return -EINVAL; 186 } 187 188 /* check <seg size> * <max_seg> >= max_frame */ 189 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 190 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 191 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 192 buffsz * DPAA_SGT_MAX_ENTRIES); 193 return -EINVAL; 194 } 195 196 fman_if_set_maxfrm(dev->process_private, frame_size); 197 198 return 0; 199 } 200 201 static int 202 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 203 { 204 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 205 uint64_t rx_offloads = eth_conf->rxmode.offloads; 206 uint64_t tx_offloads = eth_conf->txmode.offloads; 207 struct dpaa_if *dpaa_intf = dev->data->dev_private; 208 struct rte_device *rdev = dev->device; 209 struct rte_eth_link *link = &dev->data->dev_link; 210 struct rte_dpaa_device *dpaa_dev; 211 struct fman_if *fif = dev->process_private; 212 struct __fman_if *__fif; 213 struct rte_intr_handle *intr_handle; 214 uint32_t max_rx_pktlen; 215 int speed, duplex; 216 int ret, rx_status, socket_fd; 217 struct ifreq ifr; 218 219 PMD_INIT_FUNC_TRACE(); 220 221 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 222 intr_handle = dpaa_dev->intr_handle; 223 __fif = container_of(fif, struct __fman_if, __if); 224 225 /* Check if interface is enabled in case of shared MAC */ 226 if (fif->is_shared_mac) { 227 rx_status = fman_if_get_rx_status(fif); 228 if (!rx_status) { 229 DPAA_PMD_ERR("%s Interface not enabled in kernel!", 230 dpaa_intf->name); 231 return -EHOSTDOWN; 232 } 233 234 socket_fd = socket(AF_INET, SOCK_DGRAM, IPPROTO_IP); 235 if (socket_fd == -1) { 236 DPAA_PMD_ERR("Cannot open IF socket"); 237 return -errno; 238 } 239 240 strncpy(ifr.ifr_name, dpaa_intf->name, IFNAMSIZ - 1); 241 242 if (ioctl(socket_fd, SIOCGIFMTU, &ifr) < 0) { 243 DPAA_PMD_ERR("Cannot get interface mtu"); 244 close(socket_fd); 245 return -errno; 246 } 247 248 close(socket_fd); 249 DPAA_PMD_INFO("Using kernel configured mtu size(%u)", 250 ifr.ifr_mtu); 251 252 eth_conf->rxmode.mtu = ifr.ifr_mtu; 253 } 254 255 /* Rx offloads which are enabled by default */ 256 if (dev_rx_offloads_nodis & ~rx_offloads) { 257 DPAA_PMD_INFO( 258 "Some of rx offloads enabled by default - requested 0x%" PRIx64 259 " fixed are 0x%" PRIx64, 260 rx_offloads, dev_rx_offloads_nodis); 261 } 262 263 /* Tx offloads which are enabled by default */ 264 if (dev_tx_offloads_nodis & ~tx_offloads) { 265 DPAA_PMD_INFO( 266 "Some of tx offloads enabled by default - requested 0x%" PRIx64 267 " fixed are 0x%" PRIx64, 268 tx_offloads, dev_tx_offloads_nodis); 269 } 270 271 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 272 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 273 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 274 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 275 "supported is %d", 276 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 277 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 278 } 279 280 if (!fif->is_shared_mac) 281 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 282 283 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 284 DPAA_PMD_DEBUG("enabling scatter mode"); 285 fman_if_set_sg(dev->process_private, 1); 286 dev->data->scattered_rx = 1; 287 } 288 289 if (!(default_q || fmc_q)) { 290 if (dpaa_fm_config(dev, 291 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 292 dpaa_write_fm_config_to_file(); 293 DPAA_PMD_ERR("FM port configuration: Failed"); 294 return -1; 295 } 296 dpaa_write_fm_config_to_file(); 297 } 298 299 /* if the interrupts were configured on this devices*/ 300 if (intr_handle && rte_intr_fd_get(intr_handle)) { 301 if (dev->data->dev_conf.intr_conf.lsc != 0) 302 rte_intr_callback_register(intr_handle, 303 dpaa_interrupt_handler, 304 (void *)dev); 305 306 ret = dpaa_intr_enable(__fif->node_name, 307 rte_intr_fd_get(intr_handle)); 308 if (ret) { 309 if (dev->data->dev_conf.intr_conf.lsc != 0) { 310 rte_intr_callback_unregister(intr_handle, 311 dpaa_interrupt_handler, 312 (void *)dev); 313 if (ret == EINVAL) 314 DPAA_PMD_ERR("Failed to enable interrupt: Not Supported"); 315 else 316 DPAA_PMD_ERR("Failed to enable interrupt"); 317 } 318 dev->data->dev_conf.intr_conf.lsc = 0; 319 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 320 } 321 } 322 323 /* Wait for link status to get updated */ 324 if (!link->link_status) 325 sleep(1); 326 327 /* Configure link only if link is UP*/ 328 if (link->link_status) { 329 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 330 /* Start autoneg only if link is not in autoneg mode */ 331 if (!link->link_autoneg) 332 dpaa_restart_link_autoneg(__fif->node_name); 333 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 334 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 335 case RTE_ETH_LINK_SPEED_10M_HD: 336 speed = RTE_ETH_SPEED_NUM_10M; 337 duplex = RTE_ETH_LINK_HALF_DUPLEX; 338 break; 339 case RTE_ETH_LINK_SPEED_10M: 340 speed = RTE_ETH_SPEED_NUM_10M; 341 duplex = RTE_ETH_LINK_FULL_DUPLEX; 342 break; 343 case RTE_ETH_LINK_SPEED_100M_HD: 344 speed = RTE_ETH_SPEED_NUM_100M; 345 duplex = RTE_ETH_LINK_HALF_DUPLEX; 346 break; 347 case RTE_ETH_LINK_SPEED_100M: 348 speed = RTE_ETH_SPEED_NUM_100M; 349 duplex = RTE_ETH_LINK_FULL_DUPLEX; 350 break; 351 case RTE_ETH_LINK_SPEED_1G: 352 speed = RTE_ETH_SPEED_NUM_1G; 353 duplex = RTE_ETH_LINK_FULL_DUPLEX; 354 break; 355 case RTE_ETH_LINK_SPEED_2_5G: 356 speed = RTE_ETH_SPEED_NUM_2_5G; 357 duplex = RTE_ETH_LINK_FULL_DUPLEX; 358 break; 359 case RTE_ETH_LINK_SPEED_10G: 360 speed = RTE_ETH_SPEED_NUM_10G; 361 duplex = RTE_ETH_LINK_FULL_DUPLEX; 362 break; 363 default: 364 speed = RTE_ETH_SPEED_NUM_NONE; 365 duplex = RTE_ETH_LINK_FULL_DUPLEX; 366 break; 367 } 368 /* Set link speed */ 369 dpaa_update_link_speed(__fif->node_name, speed, duplex); 370 } else { 371 /* Manual autoneg - custom advertisement speed. */ 372 DPAA_PMD_ERR("Custom Advertisement speeds not supported"); 373 } 374 } 375 376 return 0; 377 } 378 379 static const uint32_t * 380 dpaa_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 381 { 382 static const uint32_t ptypes[] = { 383 RTE_PTYPE_L2_ETHER, 384 RTE_PTYPE_L2_ETHER_VLAN, 385 RTE_PTYPE_L2_ETHER_ARP, 386 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 387 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 388 RTE_PTYPE_L4_ICMP, 389 RTE_PTYPE_L4_TCP, 390 RTE_PTYPE_L4_UDP, 391 RTE_PTYPE_L4_FRAG, 392 RTE_PTYPE_L4_TCP, 393 RTE_PTYPE_L4_UDP, 394 RTE_PTYPE_L4_SCTP, 395 RTE_PTYPE_TUNNEL_ESP, 396 }; 397 398 PMD_INIT_FUNC_TRACE(); 399 400 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) { 401 *no_of_elements = RTE_DIM(ptypes); 402 return ptypes; 403 } 404 return NULL; 405 } 406 407 static void dpaa_interrupt_handler(void *param) 408 { 409 struct rte_eth_dev *dev = param; 410 struct rte_device *rdev = dev->device; 411 struct rte_dpaa_device *dpaa_dev; 412 struct rte_intr_handle *intr_handle; 413 uint64_t buf; 414 int bytes_read; 415 416 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 417 intr_handle = dpaa_dev->intr_handle; 418 419 if (rte_intr_fd_get(intr_handle) < 0) 420 return; 421 422 bytes_read = read(rte_intr_fd_get(intr_handle), &buf, 423 sizeof(uint64_t)); 424 if (bytes_read < 0) 425 DPAA_PMD_ERR("Error reading eventfd"); 426 dpaa_eth_link_update(dev, 0); 427 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 428 } 429 430 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 431 { 432 struct dpaa_if *dpaa_intf = dev->data->dev_private; 433 uint16_t i; 434 435 PMD_INIT_FUNC_TRACE(); 436 437 if (!(default_q || fmc_q)) 438 dpaa_write_fm_config_to_file(); 439 440 /* Change tx callback to the real one */ 441 if (dpaa_intf->cgr_tx) 442 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 443 else 444 dev->tx_pkt_burst = dpaa_eth_queue_tx; 445 446 fman_if_enable_rx(dev->process_private); 447 448 for (i = 0; i < dev->data->nb_rx_queues; i++) 449 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 450 for (i = 0; i < dev->data->nb_tx_queues; i++) 451 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 452 453 return 0; 454 } 455 456 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 457 { 458 struct fman_if *fif = dev->process_private; 459 uint16_t i; 460 461 PMD_INIT_FUNC_TRACE(); 462 dev->data->dev_started = 0; 463 464 if (!fif->is_shared_mac) 465 fman_if_disable_rx(fif); 466 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 467 468 for (i = 0; i < dev->data->nb_rx_queues; i++) 469 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 470 for (i = 0; i < dev->data->nb_tx_queues; i++) 471 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 472 473 return 0; 474 } 475 476 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 477 { 478 struct fman_if *fif = dev->process_private; 479 struct __fman_if *__fif; 480 struct rte_device *rdev = dev->device; 481 struct rte_dpaa_device *dpaa_dev; 482 struct rte_intr_handle *intr_handle; 483 struct rte_eth_link *link = &dev->data->dev_link; 484 struct dpaa_if *dpaa_intf = dev->data->dev_private; 485 int loop; 486 int ret; 487 488 PMD_INIT_FUNC_TRACE(); 489 490 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 491 return 0; 492 493 if (!dpaa_intf) { 494 DPAA_PMD_WARN("Already closed or not started"); 495 return -1; 496 } 497 498 /* DPAA FM deconfig */ 499 if (!(default_q || fmc_q)) { 500 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 501 DPAA_PMD_WARN("DPAA FM deconfig failed"); 502 } 503 504 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 505 intr_handle = dpaa_dev->intr_handle; 506 __fif = container_of(fif, struct __fman_if, __if); 507 508 ret = dpaa_eth_dev_stop(dev); 509 510 /* Reset link to autoneg */ 511 if (link->link_status && !link->link_autoneg) 512 dpaa_restart_link_autoneg(__fif->node_name); 513 514 if (intr_handle && rte_intr_fd_get(intr_handle) && 515 dev->data->dev_conf.intr_conf.lsc != 0) { 516 dpaa_intr_disable(__fif->node_name); 517 rte_intr_callback_unregister(intr_handle, 518 dpaa_interrupt_handler, 519 (void *)dev); 520 } 521 522 /* release configuration memory */ 523 rte_free(dpaa_intf->fc_conf); 524 525 /* Release RX congestion Groups */ 526 if (dpaa_intf->cgr_rx) { 527 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 528 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 529 } 530 531 rte_free(dpaa_intf->cgr_rx); 532 dpaa_intf->cgr_rx = NULL; 533 /* Release TX congestion Groups */ 534 if (dpaa_intf->cgr_tx) { 535 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 536 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 537 rte_free(dpaa_intf->cgr_tx); 538 dpaa_intf->cgr_tx = NULL; 539 } 540 541 rte_free(dpaa_intf->rx_queues); 542 dpaa_intf->rx_queues = NULL; 543 544 rte_free(dpaa_intf->tx_queues); 545 dpaa_intf->tx_queues = NULL; 546 547 return ret; 548 } 549 550 static int 551 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 552 char *fw_version, 553 size_t fw_size) 554 { 555 int ret; 556 FILE *svr_file = NULL; 557 unsigned int svr_ver = 0; 558 559 PMD_INIT_FUNC_TRACE(); 560 561 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 562 if (!svr_file) { 563 DPAA_PMD_ERR("Unable to open SoC device"); 564 return -ENOTSUP; /* Not supported on this infra */ 565 } 566 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 567 dpaa_svr_family = svr_ver & SVR_MASK; 568 else 569 DPAA_PMD_ERR("Unable to read SoC device"); 570 571 fclose(svr_file); 572 573 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 574 svr_ver, fman_ip_rev); 575 if (ret < 0) 576 return -EINVAL; 577 578 ret += 1; /* add the size of '\0' */ 579 if (fw_size < (size_t)ret) 580 return ret; 581 else 582 return 0; 583 } 584 585 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 586 struct rte_eth_dev_info *dev_info) 587 { 588 struct dpaa_if *dpaa_intf = dev->data->dev_private; 589 struct fman_if *fif = dev->process_private; 590 591 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 592 593 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 594 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 595 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 596 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 597 dev_info->max_hash_mac_addrs = 0; 598 dev_info->max_vfs = 0; 599 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 600 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 601 602 if (fif->mac_type == fman_mac_1g) { 603 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 604 | RTE_ETH_LINK_SPEED_10M 605 | RTE_ETH_LINK_SPEED_100M_HD 606 | RTE_ETH_LINK_SPEED_100M 607 | RTE_ETH_LINK_SPEED_1G; 608 } else if (fif->mac_type == fman_mac_2_5g) { 609 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 610 | RTE_ETH_LINK_SPEED_10M 611 | RTE_ETH_LINK_SPEED_100M_HD 612 | RTE_ETH_LINK_SPEED_100M 613 | RTE_ETH_LINK_SPEED_1G 614 | RTE_ETH_LINK_SPEED_2_5G; 615 } else if (fif->mac_type == fman_mac_10g) { 616 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 617 | RTE_ETH_LINK_SPEED_10M 618 | RTE_ETH_LINK_SPEED_100M_HD 619 | RTE_ETH_LINK_SPEED_100M 620 | RTE_ETH_LINK_SPEED_1G 621 | RTE_ETH_LINK_SPEED_2_5G 622 | RTE_ETH_LINK_SPEED_10G; 623 } else { 624 DPAA_PMD_ERR("invalid link_speed: %s, %d", 625 dpaa_intf->name, fif->mac_type); 626 return -EINVAL; 627 } 628 629 dev_info->rx_offload_capa = dev_rx_offloads_sup | 630 dev_rx_offloads_nodis; 631 dev_info->tx_offload_capa = dev_tx_offloads_sup | 632 dev_tx_offloads_nodis; 633 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 634 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 635 dev_info->default_rxportconf.nb_queues = 1; 636 dev_info->default_txportconf.nb_queues = 1; 637 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 638 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 639 640 return 0; 641 } 642 643 static int 644 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 645 __rte_unused uint16_t queue_id, 646 struct rte_eth_burst_mode *mode) 647 { 648 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 649 int ret = -EINVAL; 650 unsigned int i; 651 const struct burst_info { 652 uint64_t flags; 653 const char *output; 654 } rx_offload_map[] = { 655 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 656 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 657 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 658 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 659 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 660 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 661 }; 662 663 /* Update Rx offload info */ 664 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 665 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 666 snprintf(mode->info, sizeof(mode->info), "%s", 667 rx_offload_map[i].output); 668 ret = 0; 669 break; 670 } 671 } 672 return ret; 673 } 674 675 static int 676 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 677 __rte_unused uint16_t queue_id, 678 struct rte_eth_burst_mode *mode) 679 { 680 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 681 int ret = -EINVAL; 682 unsigned int i; 683 const struct burst_info { 684 uint64_t flags; 685 const char *output; 686 } tx_offload_map[] = { 687 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 688 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 689 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 690 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 691 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 692 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 693 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 694 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 695 }; 696 697 /* Update Tx offload info */ 698 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 699 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 700 snprintf(mode->info, sizeof(mode->info), "%s", 701 tx_offload_map[i].output); 702 ret = 0; 703 break; 704 } 705 } 706 return ret; 707 } 708 709 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 710 int wait_to_complete) 711 { 712 struct dpaa_if *dpaa_intf = dev->data->dev_private; 713 struct rte_eth_link *link = &dev->data->dev_link; 714 struct fman_if *fif = dev->process_private; 715 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 716 int ret, ioctl_version; 717 uint8_t count; 718 719 PMD_INIT_FUNC_TRACE(); 720 721 ioctl_version = dpaa_get_ioctl_version_number(); 722 723 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 724 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 725 ret = dpaa_get_link_status(__fif->node_name, link); 726 if (ret) 727 return ret; 728 if (link->link_status == RTE_ETH_LINK_DOWN && 729 wait_to_complete) 730 rte_delay_ms(CHECK_INTERVAL); 731 else 732 break; 733 } 734 } else { 735 link->link_status = dpaa_intf->valid; 736 } 737 738 if (ioctl_version < 2) { 739 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 740 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 741 742 if (fif->mac_type == fman_mac_1g) 743 link->link_speed = RTE_ETH_SPEED_NUM_1G; 744 else if (fif->mac_type == fman_mac_2_5g) 745 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 746 else if (fif->mac_type == fman_mac_10g) 747 link->link_speed = RTE_ETH_SPEED_NUM_10G; 748 else 749 DPAA_PMD_ERR("invalid link_speed: %s, %d", 750 dpaa_intf->name, fif->mac_type); 751 } 752 753 DPAA_PMD_INFO("Port %d Link is %s", dev->data->port_id, 754 link->link_status ? "Up" : "Down"); 755 return 0; 756 } 757 758 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 759 struct rte_eth_stats *stats) 760 { 761 PMD_INIT_FUNC_TRACE(); 762 763 fman_if_stats_get(dev->process_private, stats); 764 return 0; 765 } 766 767 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 768 { 769 PMD_INIT_FUNC_TRACE(); 770 771 fman_if_stats_reset(dev->process_private); 772 773 return 0; 774 } 775 776 static int 777 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 778 unsigned int n) 779 { 780 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 781 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 782 783 if (n < num) 784 return num; 785 786 if (xstats == NULL) 787 return 0; 788 789 fman_if_stats_get_all(dev->process_private, values, 790 sizeof(struct dpaa_if_stats) / 8); 791 792 for (i = 0; i < num; i++) { 793 xstats[i].id = i; 794 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 795 } 796 return i; 797 } 798 799 static int 800 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 801 struct rte_eth_xstat_name *xstats_names, 802 unsigned int limit) 803 { 804 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 805 806 if (limit < stat_cnt) 807 return stat_cnt; 808 809 if (xstats_names != NULL) 810 for (i = 0; i < stat_cnt; i++) 811 strlcpy(xstats_names[i].name, 812 dpaa_xstats_strings[i].name, 813 sizeof(xstats_names[i].name)); 814 815 return stat_cnt; 816 } 817 818 static int 819 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 820 uint64_t *values, unsigned int n) 821 { 822 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 823 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 824 825 if (!ids) { 826 if (n < stat_cnt) 827 return stat_cnt; 828 829 if (!values) 830 return 0; 831 832 fman_if_stats_get_all(dev->process_private, values_copy, 833 sizeof(struct dpaa_if_stats) / 8); 834 835 for (i = 0; i < stat_cnt; i++) 836 values[i] = 837 values_copy[dpaa_xstats_strings[i].offset / 8]; 838 839 return stat_cnt; 840 } 841 842 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 843 844 for (i = 0; i < n; i++) { 845 if (ids[i] >= stat_cnt) { 846 DPAA_PMD_ERR("id value isn't valid"); 847 return -1; 848 } 849 values[i] = values_copy[ids[i]]; 850 } 851 return n; 852 } 853 854 static int 855 dpaa_xstats_get_names_by_id( 856 struct rte_eth_dev *dev, 857 const uint64_t *ids, 858 struct rte_eth_xstat_name *xstats_names, 859 unsigned int limit) 860 { 861 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 862 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 863 864 if (!ids) 865 return dpaa_xstats_get_names(dev, xstats_names, limit); 866 867 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 868 869 for (i = 0; i < limit; i++) { 870 if (ids[i] >= stat_cnt) { 871 DPAA_PMD_ERR("id value isn't valid"); 872 return -1; 873 } 874 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 875 } 876 return limit; 877 } 878 879 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 880 { 881 PMD_INIT_FUNC_TRACE(); 882 883 fman_if_promiscuous_enable(dev->process_private); 884 885 return 0; 886 } 887 888 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 889 { 890 PMD_INIT_FUNC_TRACE(); 891 892 fman_if_promiscuous_disable(dev->process_private); 893 894 return 0; 895 } 896 897 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 898 { 899 PMD_INIT_FUNC_TRACE(); 900 901 fman_if_set_mcast_filter_table(dev->process_private); 902 903 return 0; 904 } 905 906 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 907 { 908 PMD_INIT_FUNC_TRACE(); 909 910 fman_if_reset_mcast_filter_table(dev->process_private); 911 912 return 0; 913 } 914 915 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 916 { 917 struct dpaa_if *dpaa_intf = dev->data->dev_private; 918 struct fman_if_ic_params icp; 919 uint32_t fd_offset; 920 uint32_t bp_size; 921 922 memset(&icp, 0, sizeof(icp)); 923 /* set ICEOF for to the default value , which is 0*/ 924 icp.iciof = DEFAULT_ICIOF; 925 icp.iceof = DEFAULT_RX_ICEOF; 926 icp.icsz = DEFAULT_ICSZ; 927 fman_if_set_ic_params(dev->process_private, &icp); 928 929 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 930 fman_if_set_fdoff(dev->process_private, fd_offset); 931 932 /* Buffer pool size should be equal to Dataroom Size*/ 933 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 934 935 fman_if_set_bp(dev->process_private, 936 dpaa_intf->bp_info->mp->size, 937 dpaa_intf->bp_info->bpid, bp_size); 938 } 939 940 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 941 int8_t vsp_id, uint32_t bpid) 942 { 943 struct dpaa_if *dpaa_intf = dev->data->dev_private; 944 struct fman_if *fif = dev->process_private; 945 946 if (fif->num_profiles) { 947 if (vsp_id < 0) 948 vsp_id = fif->base_profile_id; 949 } else { 950 if (vsp_id < 0) 951 vsp_id = 0; 952 } 953 954 if (dpaa_intf->vsp_bpid[vsp_id] && 955 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 956 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 957 958 return -1; 959 } 960 961 return 0; 962 } 963 964 static 965 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 966 uint16_t nb_desc, 967 unsigned int socket_id __rte_unused, 968 const struct rte_eth_rxconf *rx_conf, 969 struct rte_mempool *mp) 970 { 971 struct dpaa_if *dpaa_intf = dev->data->dev_private; 972 struct fman_if *fif = dev->process_private; 973 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 974 struct qm_mcc_initfq opts = {0}; 975 u32 flags = 0; 976 int ret; 977 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 978 uint32_t max_rx_pktlen; 979 980 PMD_INIT_FUNC_TRACE(); 981 982 if (queue_idx >= dev->data->nb_rx_queues) { 983 rte_errno = EOVERFLOW; 984 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 985 (void *)dev, queue_idx, dev->data->nb_rx_queues); 986 return -rte_errno; 987 } 988 989 /* Rx deferred start is not supported */ 990 if (rx_conf->rx_deferred_start) { 991 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 992 return -EINVAL; 993 } 994 rxq->nb_desc = UINT16_MAX; 995 rxq->offloads = rx_conf->offloads; 996 997 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 998 queue_idx, rxq->fqid); 999 1000 if (!fif->num_profiles) { 1001 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 1002 dpaa_intf->bp_info->mp != mp) { 1003 DPAA_PMD_WARN("Multiple pools on same interface not" 1004 " supported"); 1005 return -EINVAL; 1006 } 1007 } else { 1008 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 1009 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 1010 return -EINVAL; 1011 } 1012 } 1013 1014 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 1015 dpaa_intf->bp_info->mp != mp) { 1016 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 1017 return -EINVAL; 1018 } 1019 1020 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 1021 VLAN_TAG_SIZE; 1022 /* Max packet can fit in single buffer */ 1023 if (max_rx_pktlen <= buffsz) { 1024 ; 1025 } else if (dev->data->dev_conf.rxmode.offloads & 1026 RTE_ETH_RX_OFFLOAD_SCATTER) { 1027 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 1028 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 1029 "MaxSGlist %d", 1030 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 1031 rte_errno = EOVERFLOW; 1032 return -rte_errno; 1033 } 1034 } else { 1035 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 1036 " larger than a single mbuf (%u) and scattered" 1037 " mode has not been requested", max_rx_pktlen, buffsz); 1038 } 1039 1040 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 1041 1042 /* For shared interface, it's done in kernel, skip.*/ 1043 if (!fif->is_shared_mac) 1044 dpaa_fman_if_pool_setup(dev); 1045 1046 if (fif->num_profiles) { 1047 int8_t vsp_id = rxq->vsp_id; 1048 1049 if (vsp_id >= 0) { 1050 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 1051 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 1052 fif, buffsz + RTE_PKTMBUF_HEADROOM); 1053 if (ret) { 1054 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 1055 return ret; 1056 } 1057 } else { 1058 DPAA_PMD_INFO("Base profile is associated to" 1059 " RXQ fqid:%d", rxq->fqid); 1060 if (fif->is_shared_mac) { 1061 DPAA_PMD_ERR("Fatal: Base profile is associated" 1062 " to shared interface on DPDK."); 1063 return -EINVAL; 1064 } 1065 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1066 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1067 } 1068 } else { 1069 dpaa_intf->vsp_bpid[0] = 1070 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1071 } 1072 1073 dpaa_intf->valid = 1; 1074 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1075 fman_if_get_sg_enable(fif), max_rx_pktlen); 1076 /* checking if push mode only, no error check for now */ 1077 if (!rxq->is_static && 1078 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1079 struct qman_portal *qp; 1080 int q_fd; 1081 1082 dpaa_push_queue_idx++; 1083 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1084 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1085 QM_FQCTRL_CTXASTASHING | 1086 QM_FQCTRL_PREFERINCACHE; 1087 opts.fqd.context_a.stashing.exclusive = 0; 1088 /* In multicore scenario stashing becomes a bottleneck on LS1046. 1089 * So do not enable stashing in this case 1090 */ 1091 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1092 opts.fqd.context_a.stashing.annotation_cl = 1093 DPAA_IF_RX_ANNOTATION_STASH; 1094 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1095 opts.fqd.context_a.stashing.context_cl = 1096 DPAA_IF_RX_CONTEXT_STASH; 1097 1098 /*Create a channel and associate given queue with the channel*/ 1099 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1100 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1101 opts.fqd.dest.channel = rxq->ch_id; 1102 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1103 flags = QMAN_INITFQ_FLAG_SCHED; 1104 1105 /* Configure tail drop */ 1106 if (dpaa_intf->cgr_rx) { 1107 opts.we_mask |= QM_INITFQ_WE_CGID; 1108 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1109 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1110 } 1111 ret = qman_init_fq(rxq, flags, &opts); 1112 if (ret) { 1113 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1114 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1115 return ret; 1116 } 1117 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1118 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1119 } else { 1120 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1121 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1122 } 1123 1124 rxq->is_static = true; 1125 1126 /* Allocate qman specific portals */ 1127 qp = fsl_qman_fq_portal_create(&q_fd); 1128 if (!qp) { 1129 DPAA_PMD_ERR("Unable to alloc fq portal"); 1130 return -1; 1131 } 1132 rxq->qp = qp; 1133 1134 /* Set up the device interrupt handler */ 1135 if (dev->intr_handle == NULL) { 1136 struct rte_dpaa_device *dpaa_dev; 1137 struct rte_device *rdev = dev->device; 1138 1139 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1140 device); 1141 dev->intr_handle = dpaa_dev->intr_handle; 1142 if (rte_intr_vec_list_alloc(dev->intr_handle, 1143 NULL, dpaa_push_mode_max_queue)) { 1144 DPAA_PMD_ERR("intr_vec alloc failed"); 1145 return -ENOMEM; 1146 } 1147 if (rte_intr_nb_efd_set(dev->intr_handle, 1148 dpaa_push_mode_max_queue)) 1149 return -rte_errno; 1150 1151 if (rte_intr_max_intr_set(dev->intr_handle, 1152 dpaa_push_mode_max_queue)) 1153 return -rte_errno; 1154 } 1155 1156 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT)) 1157 return -rte_errno; 1158 1159 if (rte_intr_vec_list_index_set(dev->intr_handle, 1160 queue_idx, queue_idx + 1)) 1161 return -rte_errno; 1162 1163 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx, 1164 q_fd)) 1165 return -rte_errno; 1166 1167 rxq->q_fd = q_fd; 1168 } 1169 rxq->bp_array = rte_dpaa_bpid_info; 1170 dev->data->rx_queues[queue_idx] = rxq; 1171 1172 /* configure the CGR size as per the desc size */ 1173 if (dpaa_intf->cgr_rx) { 1174 struct qm_mcc_initcgr cgr_opts = {0}; 1175 1176 rxq->nb_desc = nb_desc; 1177 /* Enable tail drop with cgr on this queue */ 1178 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1179 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1180 if (ret) { 1181 DPAA_PMD_WARN( 1182 "rx taildrop modify fail on fqid %d (ret=%d)", 1183 rxq->fqid, ret); 1184 } 1185 } 1186 /* Enable main queue to receive error packets also by default */ 1187 fman_if_set_err_fqid(fif, rxq->fqid); 1188 return 0; 1189 } 1190 1191 int 1192 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1193 int eth_rx_queue_id, 1194 u16 ch_id, 1195 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1196 { 1197 int ret; 1198 u32 flags = 0; 1199 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1200 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1201 struct qm_mcc_initfq opts = {0}; 1202 1203 if (dpaa_push_mode_max_queue) { 1204 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible"); 1205 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.", 1206 dpaa_push_mode_max_queue); 1207 DPAA_PMD_WARN("To disable set DPAA_PUSH_QUEUES_NUMBER to 0"); 1208 } 1209 1210 dpaa_poll_queue_default_config(&opts); 1211 1212 switch (queue_conf->ev.sched_type) { 1213 case RTE_SCHED_TYPE_ATOMIC: 1214 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1215 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1216 * configuration with HOLD_ACTIVE setting 1217 */ 1218 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1219 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1220 break; 1221 case RTE_SCHED_TYPE_ORDERED: 1222 DPAA_PMD_ERR("Ordered queue schedule type is not supported"); 1223 return -1; 1224 default: 1225 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1226 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1227 break; 1228 } 1229 1230 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1231 opts.fqd.dest.channel = ch_id; 1232 opts.fqd.dest.wq = queue_conf->ev.priority; 1233 1234 if (dpaa_intf->cgr_rx) { 1235 opts.we_mask |= QM_INITFQ_WE_CGID; 1236 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1237 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1238 } 1239 1240 flags = QMAN_INITFQ_FLAG_SCHED; 1241 1242 ret = qman_init_fq(rxq, flags, &opts); 1243 if (ret) { 1244 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1245 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1246 return ret; 1247 } 1248 1249 /* copy configuration which needs to be filled during dequeue */ 1250 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1251 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1252 1253 return ret; 1254 } 1255 1256 int 1257 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1258 int eth_rx_queue_id) 1259 { 1260 struct qm_mcc_initfq opts = {0}; 1261 int ret; 1262 u32 flags = 0; 1263 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1264 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1265 1266 qman_retire_fq(rxq, NULL); 1267 qman_oos_fq(rxq); 1268 ret = qman_init_fq(rxq, flags, &opts); 1269 if (ret) { 1270 DPAA_PMD_ERR("detach rx fqid %d failed with ret: %d", 1271 rxq->fqid, ret); 1272 } 1273 1274 rxq->cb.dqrr_dpdk_cb = NULL; 1275 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1276 1277 return 0; 1278 } 1279 1280 static 1281 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1282 uint16_t nb_desc __rte_unused, 1283 unsigned int socket_id __rte_unused, 1284 const struct rte_eth_txconf *tx_conf) 1285 { 1286 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1287 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1288 1289 PMD_INIT_FUNC_TRACE(); 1290 1291 /* Tx deferred start is not supported */ 1292 if (tx_conf->tx_deferred_start) { 1293 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1294 return -EINVAL; 1295 } 1296 txq->nb_desc = UINT16_MAX; 1297 txq->offloads = tx_conf->offloads; 1298 1299 if (queue_idx >= dev->data->nb_tx_queues) { 1300 rte_errno = EOVERFLOW; 1301 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1302 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1303 return -rte_errno; 1304 } 1305 1306 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1307 queue_idx, txq->fqid); 1308 dev->data->tx_queues[queue_idx] = txq; 1309 1310 return 0; 1311 } 1312 1313 static uint32_t 1314 dpaa_dev_rx_queue_count(void *rx_queue) 1315 { 1316 struct qman_fq *rxq = rx_queue; 1317 u32 frm_cnt = 0; 1318 1319 PMD_INIT_FUNC_TRACE(); 1320 1321 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1322 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1323 rx_queue, frm_cnt); 1324 } 1325 return frm_cnt; 1326 } 1327 1328 static int dpaa_link_down(struct rte_eth_dev *dev) 1329 { 1330 struct fman_if *fif = dev->process_private; 1331 struct __fman_if *__fif; 1332 1333 PMD_INIT_FUNC_TRACE(); 1334 1335 __fif = container_of(fif, struct __fman_if, __if); 1336 1337 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1338 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1339 else 1340 return dpaa_eth_dev_stop(dev); 1341 return 0; 1342 } 1343 1344 static int dpaa_link_up(struct rte_eth_dev *dev) 1345 { 1346 struct fman_if *fif = dev->process_private; 1347 struct __fman_if *__fif; 1348 1349 PMD_INIT_FUNC_TRACE(); 1350 1351 __fif = container_of(fif, struct __fman_if, __if); 1352 1353 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1354 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1355 else 1356 dpaa_eth_dev_start(dev); 1357 return 0; 1358 } 1359 1360 static int 1361 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1362 struct rte_eth_fc_conf *fc_conf) 1363 { 1364 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1365 struct rte_eth_fc_conf *net_fc; 1366 1367 PMD_INIT_FUNC_TRACE(); 1368 1369 if (!(dpaa_intf->fc_conf)) { 1370 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1371 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1372 if (!dpaa_intf->fc_conf) { 1373 DPAA_PMD_ERR("unable to save flow control info"); 1374 return -ENOMEM; 1375 } 1376 } 1377 net_fc = dpaa_intf->fc_conf; 1378 1379 if (fc_conf->high_water < fc_conf->low_water) { 1380 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1381 return -EINVAL; 1382 } 1383 1384 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1385 return 0; 1386 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1387 fc_conf->mode == RTE_ETH_FC_FULL) { 1388 fman_if_set_fc_threshold(dev->process_private, 1389 fc_conf->high_water, 1390 fc_conf->low_water, 1391 dpaa_intf->bp_info->bpid); 1392 if (fc_conf->pause_time) 1393 fman_if_set_fc_quanta(dev->process_private, 1394 fc_conf->pause_time); 1395 } 1396 1397 /* Save the information in dpaa device */ 1398 net_fc->pause_time = fc_conf->pause_time; 1399 net_fc->high_water = fc_conf->high_water; 1400 net_fc->low_water = fc_conf->low_water; 1401 net_fc->send_xon = fc_conf->send_xon; 1402 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1403 net_fc->mode = fc_conf->mode; 1404 net_fc->autoneg = fc_conf->autoneg; 1405 1406 return 0; 1407 } 1408 1409 static int 1410 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1411 struct rte_eth_fc_conf *fc_conf) 1412 { 1413 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1414 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1415 int ret; 1416 1417 PMD_INIT_FUNC_TRACE(); 1418 1419 if (net_fc) { 1420 fc_conf->pause_time = net_fc->pause_time; 1421 fc_conf->high_water = net_fc->high_water; 1422 fc_conf->low_water = net_fc->low_water; 1423 fc_conf->send_xon = net_fc->send_xon; 1424 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1425 fc_conf->mode = net_fc->mode; 1426 fc_conf->autoneg = net_fc->autoneg; 1427 return 0; 1428 } 1429 ret = fman_if_get_fc_threshold(dev->process_private); 1430 if (ret) { 1431 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1432 fc_conf->pause_time = 1433 fman_if_get_fc_quanta(dev->process_private); 1434 } else { 1435 fc_conf->mode = RTE_ETH_FC_NONE; 1436 } 1437 1438 return 0; 1439 } 1440 1441 static int 1442 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1443 struct rte_ether_addr *addr, 1444 uint32_t index, 1445 __rte_unused uint32_t pool) 1446 { 1447 int ret; 1448 1449 PMD_INIT_FUNC_TRACE(); 1450 1451 ret = fman_if_add_mac_addr(dev->process_private, 1452 addr->addr_bytes, index); 1453 1454 if (ret) 1455 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1456 return 0; 1457 } 1458 1459 static void 1460 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1461 uint32_t index) 1462 { 1463 PMD_INIT_FUNC_TRACE(); 1464 1465 fman_if_clear_mac_addr(dev->process_private, index); 1466 } 1467 1468 static int 1469 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1470 struct rte_ether_addr *addr) 1471 { 1472 int ret; 1473 1474 PMD_INIT_FUNC_TRACE(); 1475 1476 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1477 if (ret) 1478 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1479 1480 return ret; 1481 } 1482 1483 static int 1484 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1485 struct rte_eth_rss_conf *rss_conf) 1486 { 1487 struct rte_eth_dev_data *data = dev->data; 1488 struct rte_eth_conf *eth_conf = &data->dev_conf; 1489 1490 PMD_INIT_FUNC_TRACE(); 1491 1492 if (!(default_q || fmc_q)) { 1493 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1494 DPAA_PMD_ERR("FM port configuration: Failed"); 1495 return -1; 1496 } 1497 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1498 } else { 1499 DPAA_PMD_ERR("Function not supported"); 1500 return -ENOTSUP; 1501 } 1502 return 0; 1503 } 1504 1505 static int 1506 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1507 struct rte_eth_rss_conf *rss_conf) 1508 { 1509 struct rte_eth_dev_data *data = dev->data; 1510 struct rte_eth_conf *eth_conf = &data->dev_conf; 1511 1512 /* dpaa does not support rss_key, so length should be 0*/ 1513 rss_conf->rss_key_len = 0; 1514 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1515 return 0; 1516 } 1517 1518 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1519 uint16_t queue_id) 1520 { 1521 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1522 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1523 1524 if (!rxq->is_static) 1525 return -EINVAL; 1526 1527 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1528 } 1529 1530 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1531 uint16_t queue_id) 1532 { 1533 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1534 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1535 uint32_t temp; 1536 ssize_t temp1; 1537 1538 if (!rxq->is_static) 1539 return -EINVAL; 1540 1541 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1542 1543 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1544 if (temp1 != sizeof(temp)) 1545 DPAA_PMD_DEBUG("read did not return anything"); 1546 1547 qman_fq_portal_thread_irq(rxq->qp); 1548 1549 return 0; 1550 } 1551 1552 static void 1553 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1554 struct rte_eth_rxq_info *qinfo) 1555 { 1556 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1557 struct qman_fq *rxq; 1558 int ret; 1559 1560 rxq = dev->data->rx_queues[queue_id]; 1561 1562 qinfo->mp = dpaa_intf->bp_info->mp; 1563 qinfo->scattered_rx = dev->data->scattered_rx; 1564 qinfo->nb_desc = rxq->nb_desc; 1565 1566 /* Report the HW Rx buffer length to user */ 1567 ret = fman_if_get_maxfrm(dev->process_private); 1568 if (ret > 0) 1569 qinfo->rx_buf_size = ret; 1570 1571 qinfo->conf.rx_free_thresh = 1; 1572 qinfo->conf.rx_drop_en = 1; 1573 qinfo->conf.rx_deferred_start = 0; 1574 qinfo->conf.offloads = rxq->offloads; 1575 } 1576 1577 static void 1578 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1579 struct rte_eth_txq_info *qinfo) 1580 { 1581 struct qman_fq *txq; 1582 1583 txq = dev->data->tx_queues[queue_id]; 1584 1585 qinfo->nb_desc = txq->nb_desc; 1586 qinfo->conf.tx_thresh.pthresh = 0; 1587 qinfo->conf.tx_thresh.hthresh = 0; 1588 qinfo->conf.tx_thresh.wthresh = 0; 1589 1590 qinfo->conf.tx_free_thresh = 0; 1591 qinfo->conf.tx_rs_thresh = 0; 1592 qinfo->conf.offloads = txq->offloads; 1593 qinfo->conf.tx_deferred_start = 0; 1594 } 1595 1596 static struct eth_dev_ops dpaa_devops = { 1597 .dev_configure = dpaa_eth_dev_configure, 1598 .dev_start = dpaa_eth_dev_start, 1599 .dev_stop = dpaa_eth_dev_stop, 1600 .dev_close = dpaa_eth_dev_close, 1601 .dev_infos_get = dpaa_eth_dev_info, 1602 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1603 1604 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1605 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1606 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1607 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1608 .rxq_info_get = dpaa_rxq_info_get, 1609 .txq_info_get = dpaa_txq_info_get, 1610 1611 .flow_ctrl_get = dpaa_flow_ctrl_get, 1612 .flow_ctrl_set = dpaa_flow_ctrl_set, 1613 1614 .link_update = dpaa_eth_link_update, 1615 .stats_get = dpaa_eth_stats_get, 1616 .xstats_get = dpaa_dev_xstats_get, 1617 .xstats_get_by_id = dpaa_xstats_get_by_id, 1618 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1619 .xstats_get_names = dpaa_xstats_get_names, 1620 .xstats_reset = dpaa_eth_stats_reset, 1621 .stats_reset = dpaa_eth_stats_reset, 1622 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1623 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1624 .allmulticast_enable = dpaa_eth_multicast_enable, 1625 .allmulticast_disable = dpaa_eth_multicast_disable, 1626 .mtu_set = dpaa_mtu_set, 1627 .dev_set_link_down = dpaa_link_down, 1628 .dev_set_link_up = dpaa_link_up, 1629 .mac_addr_add = dpaa_dev_add_mac_addr, 1630 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1631 .mac_addr_set = dpaa_dev_set_mac_addr, 1632 1633 .fw_version_get = dpaa_fw_version_get, 1634 1635 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1636 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1637 .rss_hash_update = dpaa_dev_rss_hash_update, 1638 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1639 }; 1640 1641 static bool 1642 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1643 { 1644 if (strcmp(dev->device->driver->name, 1645 drv->driver.name)) 1646 return false; 1647 1648 return true; 1649 } 1650 1651 static bool 1652 is_dpaa_supported(struct rte_eth_dev *dev) 1653 { 1654 return is_device_supported(dev, &rte_dpaa_pmd); 1655 } 1656 1657 int 1658 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1659 { 1660 struct rte_eth_dev *dev; 1661 1662 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1663 1664 dev = &rte_eth_devices[port]; 1665 1666 if (!is_dpaa_supported(dev)) 1667 return -ENOTSUP; 1668 1669 if (on) 1670 fman_if_loopback_enable(dev->process_private); 1671 else 1672 fman_if_loopback_disable(dev->process_private); 1673 1674 return 0; 1675 } 1676 1677 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1678 struct fman_if *fman_intf) 1679 { 1680 struct rte_eth_fc_conf *fc_conf; 1681 int ret; 1682 1683 PMD_INIT_FUNC_TRACE(); 1684 1685 if (!(dpaa_intf->fc_conf)) { 1686 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1687 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1688 if (!dpaa_intf->fc_conf) { 1689 DPAA_PMD_ERR("unable to save flow control info"); 1690 return -ENOMEM; 1691 } 1692 } 1693 fc_conf = dpaa_intf->fc_conf; 1694 ret = fman_if_get_fc_threshold(fman_intf); 1695 if (ret) { 1696 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1697 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1698 } else { 1699 fc_conf->mode = RTE_ETH_FC_NONE; 1700 } 1701 1702 return 0; 1703 } 1704 1705 /* Initialise an Rx FQ */ 1706 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1707 uint32_t fqid) 1708 { 1709 struct qm_mcc_initfq opts = {0}; 1710 int ret; 1711 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1712 struct qm_mcc_initcgr cgr_opts = { 1713 .we_mask = QM_CGR_WE_CS_THRES | 1714 QM_CGR_WE_CSTD_EN | 1715 QM_CGR_WE_MODE, 1716 .cgr = { 1717 .cstd_en = QM_CGR_EN, 1718 .mode = QMAN_CGR_MODE_FRAME 1719 } 1720 }; 1721 1722 if (fmc_q || default_q) { 1723 ret = qman_reserve_fqid(fqid); 1724 if (ret) { 1725 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1726 fqid, ret); 1727 return -EINVAL; 1728 } 1729 } 1730 1731 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1732 ret = qman_create_fq(fqid, flags, fq); 1733 if (ret) { 1734 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1735 fqid, ret); 1736 return ret; 1737 } 1738 fq->is_static = false; 1739 1740 dpaa_poll_queue_default_config(&opts); 1741 1742 if (cgr_rx) { 1743 /* Enable tail drop with cgr on this queue */ 1744 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1745 cgr_rx->cb = NULL; 1746 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1747 &cgr_opts); 1748 if (ret) { 1749 DPAA_PMD_WARN( 1750 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1751 fq->fqid, ret); 1752 goto without_cgr; 1753 } 1754 opts.we_mask |= QM_INITFQ_WE_CGID; 1755 opts.fqd.cgid = cgr_rx->cgrid; 1756 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1757 } 1758 without_cgr: 1759 ret = qman_init_fq(fq, 0, &opts); 1760 if (ret) 1761 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1762 return ret; 1763 } 1764 1765 /* Initialise a Tx FQ */ 1766 static int dpaa_tx_queue_init(struct qman_fq *fq, 1767 struct fman_if *fman_intf, 1768 struct qman_cgr *cgr_tx) 1769 { 1770 struct qm_mcc_initfq opts = {0}; 1771 struct qm_mcc_initcgr cgr_opts = { 1772 .we_mask = QM_CGR_WE_CS_THRES | 1773 QM_CGR_WE_CSTD_EN | 1774 QM_CGR_WE_MODE, 1775 .cgr = { 1776 .cstd_en = QM_CGR_EN, 1777 .mode = QMAN_CGR_MODE_FRAME 1778 } 1779 }; 1780 int ret; 1781 1782 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1783 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1784 if (ret) { 1785 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1786 return ret; 1787 } 1788 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1789 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1790 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1791 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1792 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1793 opts.fqd.context_b = 0; 1794 /* no tx-confirmation */ 1795 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1796 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1797 if (fman_ip_rev >= FMAN_V3) { 1798 /* Set B0V bit in contextA to set ASPID to 0 */ 1799 opts.fqd.context_a.hi |= 0x04000000; 1800 } 1801 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1802 1803 if (cgr_tx) { 1804 /* Enable tail drop with cgr on this queue */ 1805 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1806 td_tx_threshold, 0); 1807 cgr_tx->cb = NULL; 1808 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1809 &cgr_opts); 1810 if (ret) { 1811 DPAA_PMD_WARN( 1812 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1813 fq->fqid, ret); 1814 goto without_cgr; 1815 } 1816 opts.we_mask |= QM_INITFQ_WE_CGID; 1817 opts.fqd.cgid = cgr_tx->cgrid; 1818 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1819 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d", 1820 td_tx_threshold); 1821 } 1822 without_cgr: 1823 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1824 if (ret) 1825 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1826 return ret; 1827 } 1828 1829 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1830 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1831 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1832 { 1833 struct qm_mcc_initfq opts = {0}; 1834 int ret; 1835 1836 PMD_INIT_FUNC_TRACE(); 1837 1838 ret = qman_reserve_fqid(fqid); 1839 if (ret) { 1840 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1841 fqid, ret); 1842 return -EINVAL; 1843 } 1844 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1845 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1846 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1847 if (ret) { 1848 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1849 fqid, ret); 1850 return ret; 1851 } 1852 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1853 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1854 ret = qman_init_fq(fq, 0, &opts); 1855 if (ret) 1856 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1857 fqid, ret); 1858 return ret; 1859 } 1860 #endif 1861 1862 /* Initialise a network interface */ 1863 static int 1864 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1865 { 1866 struct rte_dpaa_device *dpaa_device; 1867 struct fm_eth_port_cfg *cfg; 1868 struct dpaa_if *dpaa_intf; 1869 struct fman_if *fman_intf; 1870 int dev_id; 1871 1872 PMD_INIT_FUNC_TRACE(); 1873 1874 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1875 dev_id = dpaa_device->id.dev_id; 1876 cfg = dpaa_get_eth_port_cfg(dev_id); 1877 fman_intf = cfg->fman_if; 1878 eth_dev->process_private = fman_intf; 1879 1880 /* Plugging of UCODE burst API not supported in Secondary */ 1881 dpaa_intf = eth_dev->data->dev_private; 1882 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1883 if (dpaa_intf->cgr_tx) 1884 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1885 else 1886 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1887 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1888 qman_set_fq_lookup_table( 1889 dpaa_intf->rx_queues->qman_fq_lookup_table); 1890 #endif 1891 1892 return 0; 1893 } 1894 1895 /* Initialise a network interface */ 1896 static int 1897 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1898 { 1899 int num_rx_fqs, fqid; 1900 int loop, ret = 0; 1901 int dev_id; 1902 struct rte_dpaa_device *dpaa_device; 1903 struct dpaa_if *dpaa_intf; 1904 struct fm_eth_port_cfg *cfg; 1905 struct fman_if *fman_intf; 1906 struct fman_if_bpool *bp, *tmp_bp; 1907 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1908 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1909 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1910 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1911 int8_t vsp_id = -1; 1912 1913 PMD_INIT_FUNC_TRACE(); 1914 1915 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1916 dev_id = dpaa_device->id.dev_id; 1917 dpaa_intf = eth_dev->data->dev_private; 1918 cfg = dpaa_get_eth_port_cfg(dev_id); 1919 fman_intf = cfg->fman_if; 1920 1921 dpaa_intf->name = dpaa_device->name; 1922 1923 /* save fman_if & cfg in the interface structure */ 1924 eth_dev->process_private = fman_intf; 1925 dpaa_intf->ifid = dev_id; 1926 dpaa_intf->cfg = cfg; 1927 1928 memset((char *)dev_rx_fqids, 0, 1929 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1930 1931 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1932 1933 /* Initialize Rx FQ's */ 1934 if (default_q) { 1935 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1936 } else if (fmc_q) { 1937 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1938 dev_vspids, 1939 DPAA_MAX_NUM_PCD_QUEUES); 1940 if (num_rx_fqs < 0) { 1941 DPAA_PMD_ERR("%s FMC initializes failed!", 1942 dpaa_intf->name); 1943 goto free_rx; 1944 } 1945 if (!num_rx_fqs) { 1946 DPAA_PMD_WARN("%s is not configured by FMC.", 1947 dpaa_intf->name); 1948 } 1949 } else { 1950 /* FMCLESS mode, load balance to multiple cores.*/ 1951 num_rx_fqs = rte_lcore_count(); 1952 } 1953 1954 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1955 * queues. 1956 */ 1957 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1958 DPAA_PMD_ERR("Invalid number of RX queues"); 1959 return -EINVAL; 1960 } 1961 1962 if (num_rx_fqs > 0) { 1963 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1964 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1965 if (!dpaa_intf->rx_queues) { 1966 DPAA_PMD_ERR("Failed to alloc mem for RX queues"); 1967 return -ENOMEM; 1968 } 1969 } else { 1970 dpaa_intf->rx_queues = NULL; 1971 } 1972 1973 memset(cgrid, 0, sizeof(cgrid)); 1974 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1975 1976 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1977 * Tx tail drop is disabled. 1978 */ 1979 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1980 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1981 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1982 td_tx_threshold); 1983 /* if a very large value is being configured */ 1984 if (td_tx_threshold > UINT16_MAX) 1985 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1986 } 1987 1988 /* If congestion control is enabled globally*/ 1989 if (num_rx_fqs > 0 && td_threshold) { 1990 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1991 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1992 if (!dpaa_intf->cgr_rx) { 1993 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx"); 1994 ret = -ENOMEM; 1995 goto free_rx; 1996 } 1997 1998 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1999 if (ret != num_rx_fqs) { 2000 DPAA_PMD_WARN("insufficient CGRIDs available"); 2001 ret = -EINVAL; 2002 goto free_rx; 2003 } 2004 } else { 2005 dpaa_intf->cgr_rx = NULL; 2006 } 2007 2008 if (!fmc_q && !default_q) { 2009 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 2010 num_rx_fqs, 0); 2011 if (ret < 0) { 2012 DPAA_PMD_ERR("Failed to alloc rx fqid's"); 2013 goto free_rx; 2014 } 2015 } 2016 2017 for (loop = 0; loop < num_rx_fqs; loop++) { 2018 if (default_q) 2019 fqid = cfg->rx_def; 2020 else 2021 fqid = dev_rx_fqids[loop]; 2022 2023 vsp_id = dev_vspids[loop]; 2024 2025 if (dpaa_intf->cgr_rx) 2026 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 2027 2028 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 2029 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 2030 fqid); 2031 if (ret) 2032 goto free_rx; 2033 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 2034 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 2035 } 2036 dpaa_intf->nb_rx_queues = num_rx_fqs; 2037 2038 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 2039 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 2040 MAX_DPAA_CORES, MAX_CACHELINE); 2041 if (!dpaa_intf->tx_queues) { 2042 DPAA_PMD_ERR("Failed to alloc mem for TX queues"); 2043 ret = -ENOMEM; 2044 goto free_rx; 2045 } 2046 2047 /* If congestion control is enabled globally*/ 2048 if (td_tx_threshold) { 2049 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 2050 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 2051 MAX_CACHELINE); 2052 if (!dpaa_intf->cgr_tx) { 2053 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx"); 2054 ret = -ENOMEM; 2055 goto free_rx; 2056 } 2057 2058 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 2059 1, 0); 2060 if (ret != MAX_DPAA_CORES) { 2061 DPAA_PMD_WARN("insufficient CGRIDs available"); 2062 ret = -EINVAL; 2063 goto free_rx; 2064 } 2065 } else { 2066 dpaa_intf->cgr_tx = NULL; 2067 } 2068 2069 2070 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2071 if (dpaa_intf->cgr_tx) 2072 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2073 2074 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2075 fman_intf, 2076 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2077 if (ret) 2078 goto free_tx; 2079 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2080 } 2081 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2082 2083 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2084 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2085 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2086 if (ret) { 2087 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2088 goto free_tx; 2089 } 2090 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2091 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2092 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2093 if (ret) { 2094 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2095 goto free_tx; 2096 } 2097 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2098 #endif 2099 2100 DPAA_PMD_DEBUG("All frame queues created"); 2101 2102 /* Get the initial configuration for flow control */ 2103 dpaa_fc_set_default(dpaa_intf, fman_intf); 2104 2105 /* reset bpool list, initialize bpool dynamically */ 2106 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2107 list_del(&bp->node); 2108 rte_free(bp); 2109 } 2110 2111 /* Populate ethdev structure */ 2112 eth_dev->dev_ops = &dpaa_devops; 2113 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2114 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2115 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2116 2117 /* Allocate memory for storing MAC addresses */ 2118 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2119 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2120 if (eth_dev->data->mac_addrs == NULL) { 2121 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2122 "store MAC addresses", 2123 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2124 ret = -ENOMEM; 2125 goto free_tx; 2126 } 2127 2128 /* copy the primary mac address */ 2129 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2130 2131 DPAA_PMD_INFO("net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT, 2132 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2133 2134 if (!fman_intf->is_shared_mac) { 2135 /* Configure error packet handling */ 2136 fman_if_receive_rx_errors(fman_intf, 2137 FM_FD_RX_STATUS_ERR_MASK); 2138 /* Disable RX mode */ 2139 fman_if_disable_rx(fman_intf); 2140 /* Disable promiscuous mode */ 2141 fman_if_promiscuous_disable(fman_intf); 2142 /* Disable multicast */ 2143 fman_if_reset_mcast_filter_table(fman_intf); 2144 /* Reset interface statistics */ 2145 fman_if_stats_reset(fman_intf); 2146 /* Disable SG by default */ 2147 fman_if_set_sg(fman_intf, 0); 2148 fman_if_set_maxfrm(fman_intf, 2149 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2150 } 2151 2152 return 0; 2153 2154 free_tx: 2155 rte_free(dpaa_intf->tx_queues); 2156 dpaa_intf->tx_queues = NULL; 2157 dpaa_intf->nb_tx_queues = 0; 2158 2159 free_rx: 2160 rte_free(dpaa_intf->cgr_rx); 2161 rte_free(dpaa_intf->cgr_tx); 2162 rte_free(dpaa_intf->rx_queues); 2163 dpaa_intf->rx_queues = NULL; 2164 dpaa_intf->nb_rx_queues = 0; 2165 return ret; 2166 } 2167 2168 static int 2169 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2170 struct rte_dpaa_device *dpaa_dev) 2171 { 2172 int diag; 2173 int ret; 2174 struct rte_eth_dev *eth_dev; 2175 2176 PMD_INIT_FUNC_TRACE(); 2177 2178 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2179 RTE_PKTMBUF_HEADROOM) { 2180 DPAA_PMD_ERR( 2181 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2182 RTE_PKTMBUF_HEADROOM, 2183 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2184 2185 return -1; 2186 } 2187 2188 /* In case of secondary process, the device is already configured 2189 * and no further action is required, except portal initialization 2190 * and verifying secondary attachment to port name. 2191 */ 2192 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2193 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2194 if (!eth_dev) 2195 return -ENOMEM; 2196 eth_dev->device = &dpaa_dev->device; 2197 eth_dev->dev_ops = &dpaa_devops; 2198 2199 ret = dpaa_dev_init_secondary(eth_dev); 2200 if (ret != 0) { 2201 DPAA_PMD_ERR("secondary dev init failed"); 2202 return ret; 2203 } 2204 2205 rte_eth_dev_probing_finish(eth_dev); 2206 return 0; 2207 } 2208 2209 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2210 if (access("/tmp/fmc.bin", F_OK) == -1) { 2211 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2212 default_q = 1; 2213 } 2214 2215 if (!(default_q || fmc_q)) { 2216 if (dpaa_fm_init()) { 2217 DPAA_PMD_ERR("FM init failed"); 2218 return -1; 2219 } 2220 } 2221 2222 /* disabling the default push mode for LS1043 */ 2223 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2224 dpaa_push_mode_max_queue = 0; 2225 2226 /* if push mode queues to be enabled. Currently we are allowing 2227 * only one queue per thread. 2228 */ 2229 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2230 dpaa_push_mode_max_queue = 2231 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2232 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2233 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2234 } 2235 2236 is_global_init = 1; 2237 } 2238 2239 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2240 ret = rte_dpaa_portal_init((void *)1); 2241 if (ret) { 2242 DPAA_PMD_ERR("Unable to initialize portal"); 2243 return ret; 2244 } 2245 } 2246 2247 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2248 if (!eth_dev) 2249 return -ENOMEM; 2250 2251 eth_dev->data->dev_private = 2252 rte_zmalloc("ethdev private structure", 2253 sizeof(struct dpaa_if), 2254 RTE_CACHE_LINE_SIZE); 2255 if (!eth_dev->data->dev_private) { 2256 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2257 rte_eth_dev_release_port(eth_dev); 2258 return -ENOMEM; 2259 } 2260 2261 eth_dev->device = &dpaa_dev->device; 2262 dpaa_dev->eth_dev = eth_dev; 2263 2264 qman_ern_register_cb(dpaa_free_mbuf); 2265 2266 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2267 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2268 2269 /* Invoke PMD device initialization function */ 2270 diag = dpaa_dev_init(eth_dev); 2271 if (diag == 0) { 2272 if (!dpaa_tx_sg_pool) { 2273 dpaa_tx_sg_pool = 2274 rte_pktmbuf_pool_create("dpaa_mbuf_tx_sg_pool", 2275 DPAA_POOL_SIZE, 2276 DPAA_POOL_CACHE_SIZE, 0, 2277 DPAA_MAX_SGS * sizeof(struct qm_sg_entry), 2278 rte_socket_id()); 2279 if (dpaa_tx_sg_pool == NULL) { 2280 DPAA_PMD_ERR("SG pool creation failed"); 2281 return -ENOMEM; 2282 } 2283 } 2284 rte_eth_dev_probing_finish(eth_dev); 2285 dpaa_valid_dev++; 2286 return 0; 2287 } 2288 2289 rte_eth_dev_release_port(eth_dev); 2290 return diag; 2291 } 2292 2293 static int 2294 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2295 { 2296 struct rte_eth_dev *eth_dev; 2297 int ret; 2298 2299 PMD_INIT_FUNC_TRACE(); 2300 2301 eth_dev = dpaa_dev->eth_dev; 2302 dpaa_eth_dev_close(eth_dev); 2303 dpaa_valid_dev--; 2304 if (!dpaa_valid_dev) 2305 rte_mempool_free(dpaa_tx_sg_pool); 2306 ret = rte_eth_dev_release_port(eth_dev); 2307 2308 return ret; 2309 } 2310 2311 static void __attribute__((destructor(102))) dpaa_finish(void) 2312 { 2313 /* For secondary, primary will do all the cleanup */ 2314 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2315 return; 2316 2317 if (!(default_q || fmc_q)) { 2318 unsigned int i; 2319 2320 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2321 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2322 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2323 struct dpaa_if *dpaa_intf = 2324 dev->data->dev_private; 2325 struct fman_if *fif = 2326 dev->process_private; 2327 if (dpaa_intf->port_handle) 2328 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2329 DPAA_PMD_WARN("DPAA FM " 2330 "deconfig failed"); 2331 if (fif->num_profiles) { 2332 if (dpaa_port_vsp_cleanup(dpaa_intf, 2333 fif)) 2334 DPAA_PMD_WARN("DPAA FM vsp cleanup failed"); 2335 } 2336 } 2337 } 2338 if (is_global_init) 2339 if (dpaa_fm_term()) 2340 DPAA_PMD_WARN("DPAA FM term failed"); 2341 2342 is_global_init = 0; 2343 2344 DPAA_PMD_INFO("DPAA fman cleaned up"); 2345 } 2346 } 2347 2348 static struct rte_dpaa_driver rte_dpaa_pmd = { 2349 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2350 .drv_type = FSL_DPAA_ETH, 2351 .probe = rte_dpaa_probe, 2352 .remove = rte_dpaa_remove, 2353 }; 2354 2355 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2356 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2357