1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020,2022-2024 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 #include <sys/ioctl.h> 18 19 #include <rte_string_fns.h> 20 #include <rte_byteorder.h> 21 #include <rte_common.h> 22 #include <rte_interrupts.h> 23 #include <rte_log.h> 24 #include <rte_debug.h> 25 #include <rte_pci.h> 26 #include <rte_atomic.h> 27 #include <rte_branch_prediction.h> 28 #include <rte_memory.h> 29 #include <rte_tailq.h> 30 #include <rte_eal.h> 31 #include <rte_alarm.h> 32 #include <rte_ether.h> 33 #include <rte_kvargs.h> 34 #include <ethdev_driver.h> 35 #include <rte_malloc.h> 36 #include <rte_ring.h> 37 38 #include <bus_dpaa_driver.h> 39 #include <rte_dpaa_logs.h> 40 #include <dpaa_mempool.h> 41 42 #include <dpaa_ethdev.h> 43 #include <dpaa_rxtx.h> 44 #include <dpaa_flow.h> 45 #include <rte_pmd_dpaa.h> 46 47 #include <fsl_usd.h> 48 #include <fsl_qman.h> 49 #include <fsl_bman.h> 50 #include <fsl_fman.h> 51 #include <process.h> 52 #include <fmlib/fm_ext.h> 53 54 #define DRIVER_IEEE1588 "drv_ieee1588" 55 #define CHECK_INTERVAL 100 /* 100ms */ 56 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 57 58 /* Supported Rx offloads */ 59 static uint64_t dev_rx_offloads_sup = 60 RTE_ETH_RX_OFFLOAD_SCATTER; 61 62 /* Rx offloads which cannot be disabled */ 63 static uint64_t dev_rx_offloads_nodis = 64 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 65 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 66 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 67 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 68 RTE_ETH_RX_OFFLOAD_RSS_HASH; 69 70 /* Supported Tx offloads */ 71 static uint64_t dev_tx_offloads_sup = 72 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 73 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 74 75 /* Tx offloads which cannot be disabled */ 76 static uint64_t dev_tx_offloads_nodis = 77 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 78 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 79 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 80 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 81 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 82 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 83 84 /* Keep track of whether QMAN and BMAN have been globally initialized */ 85 static int is_global_init; 86 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 87 static int default_q; /* use default queue - FMC is not executed*/ 88 int dpaa_ieee_1588; /* use to indicate if IEEE 1588 is enabled for the driver */ 89 /* At present we only allow up to 4 push mode queues as default - as each of 90 * this queue need dedicated portal and we are short of portals. 91 */ 92 #define DPAA_MAX_PUSH_MODE_QUEUE 8 93 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 94 95 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 96 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 97 98 99 /* Per RX FQ Taildrop in frame count */ 100 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 101 102 /* Per TX FQ Taildrop in frame count, disabled by default */ 103 static unsigned int td_tx_threshold; 104 105 struct rte_dpaa_xstats_name_off { 106 char name[RTE_ETH_XSTATS_NAME_SIZE]; 107 uint32_t offset; 108 }; 109 110 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 111 {"rx_align_err", 112 offsetof(struct dpaa_if_stats, raln)}, 113 {"rx_valid_pause", 114 offsetof(struct dpaa_if_stats, rxpf)}, 115 {"rx_fcs_err", 116 offsetof(struct dpaa_if_stats, rfcs)}, 117 {"rx_vlan_frame", 118 offsetof(struct dpaa_if_stats, rvlan)}, 119 {"rx_frame_err", 120 offsetof(struct dpaa_if_stats, rerr)}, 121 {"rx_drop_err", 122 offsetof(struct dpaa_if_stats, rdrp)}, 123 {"rx_undersized", 124 offsetof(struct dpaa_if_stats, rund)}, 125 {"rx_oversize_err", 126 offsetof(struct dpaa_if_stats, rovr)}, 127 {"rx_fragment_pkt", 128 offsetof(struct dpaa_if_stats, rfrg)}, 129 {"tx_valid_pause", 130 offsetof(struct dpaa_if_stats, txpf)}, 131 {"tx_fcs_err", 132 offsetof(struct dpaa_if_stats, terr)}, 133 {"tx_vlan_frame", 134 offsetof(struct dpaa_if_stats, tvlan)}, 135 {"rx_undersized", 136 offsetof(struct dpaa_if_stats, tund)}, 137 {"rx_frame_counter", 138 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rfrc)}, 139 {"rx_bad_frames_count", 140 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rfbc)}, 141 {"rx_large_frames_count", 142 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rlfc)}, 143 {"rx_filter_frames_count", 144 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rffc)}, 145 {"rx_frame_discrad_count", 146 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rfdc)}, 147 {"rx_frame_list_dma_err_count", 148 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rfldec)}, 149 {"rx_out_of_buffer_discard ", 150 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rodc)}, 151 {"rx_buf_diallocate", 152 offsetof(struct dpaa_if_rx_bmi_stats, fmbm_rbdc)}, 153 }; 154 155 static struct rte_dpaa_driver rte_dpaa_pmd; 156 int dpaa_valid_dev; 157 struct rte_mempool *dpaa_tx_sg_pool; 158 159 static int 160 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 161 162 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 163 int wait_to_complete __rte_unused); 164 165 static void dpaa_interrupt_handler(void *param); 166 167 static inline void 168 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 169 { 170 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 171 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 172 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 173 QM_FQCTRL_PREFERINCACHE; 174 opts->fqd.context_a.stashing.exclusive = 0; 175 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 176 opts->fqd.context_a.stashing.annotation_cl = 177 DPAA_IF_RX_ANNOTATION_STASH; 178 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 179 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 180 } 181 182 static int 183 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 184 { 185 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 186 + VLAN_TAG_SIZE; 187 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 188 struct fman_if *fif = dev->process_private; 189 190 PMD_INIT_FUNC_TRACE(); 191 192 if (fif->is_shared_mac) { 193 DPAA_PMD_ERR("Cannot configure mtu from DPDK in VSP mode."); 194 return -ENOTSUP; 195 } 196 197 /* 198 * Refuse mtu that requires the support of scattered packets 199 * when this feature has not been enabled before. 200 */ 201 if (dev->data->min_rx_buf_size && 202 !dev->data->scattered_rx && frame_size > buffsz) { 203 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 204 return -EINVAL; 205 } 206 207 /* check <seg size> * <max_seg> >= max_frame */ 208 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 209 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 210 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 211 buffsz * DPAA_SGT_MAX_ENTRIES); 212 return -EINVAL; 213 } 214 215 fman_if_set_maxfrm(dev->process_private, frame_size); 216 217 return 0; 218 } 219 220 static int 221 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 222 { 223 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 224 uint64_t rx_offloads = eth_conf->rxmode.offloads; 225 uint64_t tx_offloads = eth_conf->txmode.offloads; 226 struct dpaa_if *dpaa_intf = dev->data->dev_private; 227 struct rte_device *rdev = dev->device; 228 struct rte_eth_link *link = &dev->data->dev_link; 229 struct rte_dpaa_device *dpaa_dev; 230 struct fman_if *fif = dev->process_private; 231 struct __fman_if *__fif; 232 struct rte_intr_handle *intr_handle; 233 uint32_t max_rx_pktlen; 234 int speed, duplex; 235 int ret, rx_status, socket_fd; 236 struct ifreq ifr; 237 238 PMD_INIT_FUNC_TRACE(); 239 240 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 241 intr_handle = dpaa_dev->intr_handle; 242 __fif = container_of(fif, struct __fman_if, __if); 243 244 /* Check if interface is enabled in case of shared MAC */ 245 if (fif->is_shared_mac) { 246 rx_status = fman_if_get_rx_status(fif); 247 if (!rx_status) { 248 DPAA_PMD_ERR("%s Interface not enabled in kernel!", 249 dpaa_intf->name); 250 return -EHOSTDOWN; 251 } 252 253 socket_fd = socket(AF_INET, SOCK_DGRAM, IPPROTO_IP); 254 if (socket_fd == -1) { 255 DPAA_PMD_ERR("Cannot open IF socket"); 256 return -errno; 257 } 258 strncpy(ifr.ifr_name, dpaa_intf->name, IFNAMSIZ - 1); 259 260 if (ioctl(socket_fd, SIOCGIFMTU, &ifr) < 0) { 261 DPAA_PMD_ERR("Cannot get interface mtu"); 262 close(socket_fd); 263 return -errno; 264 } 265 266 close(socket_fd); 267 DPAA_PMD_INFO("Using kernel configured mtu size(%u)", 268 ifr.ifr_mtu); 269 270 eth_conf->rxmode.mtu = ifr.ifr_mtu; 271 } 272 273 /* Rx offloads which are enabled by default */ 274 if (dev_rx_offloads_nodis & ~rx_offloads) { 275 DPAA_PMD_INFO( 276 "Some of rx offloads enabled by default - requested 0x%" PRIx64 277 " fixed are 0x%" PRIx64, 278 rx_offloads, dev_rx_offloads_nodis); 279 } 280 281 /* Tx offloads which are enabled by default */ 282 if (dev_tx_offloads_nodis & ~tx_offloads) { 283 DPAA_PMD_INFO( 284 "Some of tx offloads enabled by default - requested 0x%" PRIx64 285 " fixed are 0x%" PRIx64, 286 tx_offloads, dev_tx_offloads_nodis); 287 } 288 289 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 290 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 291 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 292 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 293 "supported is %d", 294 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 295 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 296 } 297 298 if (!fif->is_shared_mac && fif->mac_type != fman_offline_internal && 299 fif->mac_type != fman_onic) 300 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 301 302 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 303 DPAA_PMD_DEBUG("enabling scatter mode"); 304 fman_if_set_sg(dev->process_private, 1); 305 dev->data->scattered_rx = 1; 306 } 307 308 if (!(default_q || fmc_q)) { 309 if (dpaa_fm_config(dev, 310 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 311 dpaa_write_fm_config_to_file(); 312 DPAA_PMD_ERR("FM port configuration: Failed"); 313 return -1; 314 } 315 dpaa_write_fm_config_to_file(); 316 } 317 318 /* Disable interrupt support on offline port*/ 319 if (fif->mac_type == fman_offline_internal || 320 fif->mac_type == fman_onic) 321 return 0; 322 323 /* if the interrupts were configured on this devices*/ 324 if (intr_handle && rte_intr_fd_get(intr_handle)) { 325 if (dev->data->dev_conf.intr_conf.lsc != 0) 326 rte_intr_callback_register(intr_handle, 327 dpaa_interrupt_handler, 328 (void *)dev); 329 330 ret = dpaa_intr_enable(__fif->node_name, 331 rte_intr_fd_get(intr_handle)); 332 if (ret) { 333 if (dev->data->dev_conf.intr_conf.lsc != 0) { 334 rte_intr_callback_unregister(intr_handle, 335 dpaa_interrupt_handler, 336 (void *)dev); 337 if (ret == EINVAL) 338 DPAA_PMD_ERR("Failed to enable interrupt: Not Supported"); 339 else 340 DPAA_PMD_ERR("Failed to enable interrupt"); 341 } 342 dev->data->dev_conf.intr_conf.lsc = 0; 343 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 344 } 345 } 346 347 /* Wait for link status to get updated */ 348 if (!link->link_status) 349 sleep(1); 350 351 /* Configure link only if link is UP*/ 352 if (link->link_status) { 353 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 354 /* Start autoneg only if link is not in autoneg mode */ 355 if (!link->link_autoneg) 356 dpaa_restart_link_autoneg(__fif->node_name); 357 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 358 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 359 case RTE_ETH_LINK_SPEED_10M_HD: 360 speed = RTE_ETH_SPEED_NUM_10M; 361 duplex = RTE_ETH_LINK_HALF_DUPLEX; 362 break; 363 case RTE_ETH_LINK_SPEED_10M: 364 speed = RTE_ETH_SPEED_NUM_10M; 365 duplex = RTE_ETH_LINK_FULL_DUPLEX; 366 break; 367 case RTE_ETH_LINK_SPEED_100M_HD: 368 speed = RTE_ETH_SPEED_NUM_100M; 369 duplex = RTE_ETH_LINK_HALF_DUPLEX; 370 break; 371 case RTE_ETH_LINK_SPEED_100M: 372 speed = RTE_ETH_SPEED_NUM_100M; 373 duplex = RTE_ETH_LINK_FULL_DUPLEX; 374 break; 375 case RTE_ETH_LINK_SPEED_1G: 376 speed = RTE_ETH_SPEED_NUM_1G; 377 duplex = RTE_ETH_LINK_FULL_DUPLEX; 378 break; 379 case RTE_ETH_LINK_SPEED_2_5G: 380 speed = RTE_ETH_SPEED_NUM_2_5G; 381 duplex = RTE_ETH_LINK_FULL_DUPLEX; 382 break; 383 case RTE_ETH_LINK_SPEED_10G: 384 speed = RTE_ETH_SPEED_NUM_10G; 385 duplex = RTE_ETH_LINK_FULL_DUPLEX; 386 break; 387 default: 388 speed = RTE_ETH_SPEED_NUM_NONE; 389 duplex = RTE_ETH_LINK_FULL_DUPLEX; 390 break; 391 } 392 /* Set link speed */ 393 dpaa_update_link_speed(__fif->node_name, speed, duplex); 394 } else { 395 /* Manual autoneg - custom advertisement speed. */ 396 DPAA_PMD_ERR("Custom Advertisement speeds not supported"); 397 } 398 } 399 400 return 0; 401 } 402 403 static const uint32_t * 404 dpaa_supported_ptypes_get(struct rte_eth_dev *dev, size_t *no_of_elements) 405 { 406 static const uint32_t ptypes[] = { 407 RTE_PTYPE_L2_ETHER, 408 RTE_PTYPE_L2_ETHER_VLAN, 409 RTE_PTYPE_L2_ETHER_ARP, 410 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 411 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 412 RTE_PTYPE_L4_ICMP, 413 RTE_PTYPE_L4_TCP, 414 RTE_PTYPE_L4_UDP, 415 RTE_PTYPE_L4_FRAG, 416 RTE_PTYPE_L4_TCP, 417 RTE_PTYPE_L4_UDP, 418 RTE_PTYPE_L4_SCTP, 419 RTE_PTYPE_TUNNEL_ESP, 420 RTE_PTYPE_TUNNEL_GRE, 421 }; 422 423 PMD_INIT_FUNC_TRACE(); 424 425 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) { 426 *no_of_elements = RTE_DIM(ptypes); 427 return ptypes; 428 } 429 return NULL; 430 } 431 432 static void dpaa_interrupt_handler(void *param) 433 { 434 struct rte_eth_dev *dev = param; 435 struct rte_device *rdev = dev->device; 436 struct rte_dpaa_device *dpaa_dev; 437 struct rte_intr_handle *intr_handle; 438 uint64_t buf; 439 int bytes_read; 440 441 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 442 intr_handle = dpaa_dev->intr_handle; 443 444 if (rte_intr_fd_get(intr_handle) < 0) 445 return; 446 447 bytes_read = read(rte_intr_fd_get(intr_handle), &buf, 448 sizeof(uint64_t)); 449 if (bytes_read < 0) 450 DPAA_PMD_ERR("Error reading eventfd"); 451 dpaa_eth_link_update(dev, 0); 452 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 453 } 454 455 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 456 { 457 struct dpaa_if *dpaa_intf = dev->data->dev_private; 458 struct fman_if *fif = dev->process_private; 459 uint16_t i; 460 461 PMD_INIT_FUNC_TRACE(); 462 463 if (!(default_q || fmc_q)) 464 dpaa_write_fm_config_to_file(); 465 466 /* Change tx callback to the real one */ 467 if (dpaa_intf->cgr_tx) 468 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 469 else 470 dev->tx_pkt_burst = dpaa_eth_queue_tx; 471 472 if (fif->mac_type != fman_onic) { 473 fman_if_bmi_stats_enable(fif); 474 fman_if_bmi_stats_reset(fif); 475 fman_if_enable_rx(fif); 476 } 477 for (i = 0; i < dev->data->nb_rx_queues; i++) 478 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 479 for (i = 0; i < dev->data->nb_tx_queues; i++) 480 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 481 482 return 0; 483 } 484 485 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 486 { 487 struct fman_if *fif = dev->process_private; 488 uint16_t i; 489 490 PMD_INIT_FUNC_TRACE(); 491 dev->data->dev_started = 0; 492 493 if (!fif->is_shared_mac) { 494 fman_if_bmi_stats_disable(fif); 495 fman_if_disable_rx(fif); 496 } 497 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 498 499 for (i = 0; i < dev->data->nb_rx_queues; i++) 500 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 501 for (i = 0; i < dev->data->nb_tx_queues; i++) 502 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 503 504 return 0; 505 } 506 507 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 508 { 509 struct fman_if *fif = dev->process_private; 510 struct __fman_if *__fif; 511 struct rte_device *rdev = dev->device; 512 struct rte_dpaa_device *dpaa_dev; 513 struct rte_intr_handle *intr_handle; 514 struct rte_eth_link *link = &dev->data->dev_link; 515 struct dpaa_if *dpaa_intf = dev->data->dev_private; 516 int loop; 517 int ret; 518 519 PMD_INIT_FUNC_TRACE(); 520 521 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 522 return 0; 523 524 if (!dpaa_intf) { 525 DPAA_PMD_WARN("Already closed or not started"); 526 return -1; 527 } 528 529 /* DPAA FM deconfig */ 530 if (!(default_q || fmc_q)) { 531 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 532 DPAA_PMD_WARN("DPAA FM deconfig failed"); 533 } 534 535 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 536 intr_handle = dpaa_dev->intr_handle; 537 __fif = container_of(fif, struct __fman_if, __if); 538 539 ret = dpaa_eth_dev_stop(dev); 540 541 if (fif->mac_type == fman_offline_internal || 542 fif->mac_type == fman_onic) 543 return 0; 544 545 /* Reset link to autoneg */ 546 if (link->link_status && !link->link_autoneg) 547 dpaa_restart_link_autoneg(__fif->node_name); 548 549 if (intr_handle && rte_intr_fd_get(intr_handle) && 550 dev->data->dev_conf.intr_conf.lsc != 0) { 551 dpaa_intr_disable(__fif->node_name); 552 rte_intr_callback_unregister(intr_handle, 553 dpaa_interrupt_handler, 554 (void *)dev); 555 } 556 557 /* release configuration memory */ 558 rte_free(dpaa_intf->fc_conf); 559 560 /* Release RX congestion Groups */ 561 if (dpaa_intf->cgr_rx) { 562 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 563 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 564 rte_free(dpaa_intf->cgr_rx); 565 dpaa_intf->cgr_rx = NULL; 566 } 567 568 /* Release TX congestion Groups */ 569 if (dpaa_intf->cgr_tx) { 570 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 571 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 572 rte_free(dpaa_intf->cgr_tx); 573 dpaa_intf->cgr_tx = NULL; 574 } 575 576 rte_free(dpaa_intf->rx_queues); 577 dpaa_intf->rx_queues = NULL; 578 579 rte_free(dpaa_intf->tx_queues); 580 dpaa_intf->tx_queues = NULL; 581 if (dpaa_intf->port_handle) { 582 if (dpaa_fm_deconfig(dpaa_intf, fif)) 583 DPAA_PMD_WARN("DPAA FM " 584 "deconfig failed"); 585 } 586 if (fif->num_profiles) { 587 if (dpaa_port_vsp_cleanup(dpaa_intf, fif)) 588 DPAA_PMD_WARN("DPAA FM vsp cleanup failed"); 589 } 590 591 return ret; 592 } 593 594 static int 595 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 596 char *fw_version, 597 size_t fw_size) 598 { 599 int ret; 600 FILE *svr_file = NULL; 601 unsigned int svr_ver = 0; 602 603 PMD_INIT_FUNC_TRACE(); 604 605 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 606 if (!svr_file) { 607 DPAA_PMD_ERR("Unable to open SoC device"); 608 return -ENOTSUP; /* Not supported on this infra */ 609 } 610 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 611 dpaa_svr_family = svr_ver & SVR_MASK; 612 else 613 DPAA_PMD_ERR("Unable to read SoC device"); 614 615 fclose(svr_file); 616 617 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 618 svr_ver, fman_ip_rev); 619 if (ret < 0) 620 return -EINVAL; 621 622 ret += 1; /* add the size of '\0' */ 623 if (fw_size < (size_t)ret) 624 return ret; 625 else 626 return 0; 627 } 628 629 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 630 struct rte_eth_dev_info *dev_info) 631 { 632 struct dpaa_if *dpaa_intf = dev->data->dev_private; 633 struct fman_if *fif = dev->process_private; 634 635 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 636 637 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 638 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 639 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 640 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 641 dev_info->max_hash_mac_addrs = 0; 642 dev_info->max_vfs = 0; 643 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 644 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 645 646 if (fif->mac_type == fman_mac_1g) { 647 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 648 | RTE_ETH_LINK_SPEED_10M 649 | RTE_ETH_LINK_SPEED_100M_HD 650 | RTE_ETH_LINK_SPEED_100M 651 | RTE_ETH_LINK_SPEED_1G; 652 } else if (fif->mac_type == fman_mac_2_5g) { 653 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 654 | RTE_ETH_LINK_SPEED_10M 655 | RTE_ETH_LINK_SPEED_100M_HD 656 | RTE_ETH_LINK_SPEED_100M 657 | RTE_ETH_LINK_SPEED_1G 658 | RTE_ETH_LINK_SPEED_2_5G; 659 } else if (fif->mac_type == fman_mac_10g) { 660 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 661 | RTE_ETH_LINK_SPEED_10M 662 | RTE_ETH_LINK_SPEED_100M_HD 663 | RTE_ETH_LINK_SPEED_100M 664 | RTE_ETH_LINK_SPEED_1G 665 | RTE_ETH_LINK_SPEED_2_5G 666 | RTE_ETH_LINK_SPEED_10G; 667 } else if (fif->mac_type == fman_offline_internal || 668 fif->mac_type == fman_onic) { 669 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 670 | RTE_ETH_LINK_SPEED_10M 671 | RTE_ETH_LINK_SPEED_100M_HD 672 | RTE_ETH_LINK_SPEED_100M 673 | RTE_ETH_LINK_SPEED_1G 674 | RTE_ETH_LINK_SPEED_2_5G; 675 } else { 676 DPAA_PMD_ERR("invalid link_speed: %s, %d", 677 dpaa_intf->name, fif->mac_type); 678 return -EINVAL; 679 } 680 681 dev_info->rx_offload_capa = dev_rx_offloads_sup | 682 dev_rx_offloads_nodis; 683 dev_info->tx_offload_capa = dev_tx_offloads_sup | 684 dev_tx_offloads_nodis; 685 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 686 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 687 dev_info->default_rxportconf.nb_queues = 1; 688 dev_info->default_txportconf.nb_queues = 1; 689 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 690 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 691 692 return 0; 693 } 694 695 static int 696 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 697 __rte_unused uint16_t queue_id, 698 struct rte_eth_burst_mode *mode) 699 { 700 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 701 int ret = -EINVAL; 702 unsigned int i; 703 const struct burst_info { 704 uint64_t flags; 705 const char *output; 706 } rx_offload_map[] = { 707 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 708 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 709 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 710 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 711 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 712 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 713 }; 714 715 /* Update Rx offload info */ 716 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 717 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 718 snprintf(mode->info, sizeof(mode->info), "%s", 719 rx_offload_map[i].output); 720 ret = 0; 721 break; 722 } 723 } 724 return ret; 725 } 726 727 static int 728 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 729 __rte_unused uint16_t queue_id, 730 struct rte_eth_burst_mode *mode) 731 { 732 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 733 int ret = -EINVAL; 734 unsigned int i; 735 const struct burst_info { 736 uint64_t flags; 737 const char *output; 738 } tx_offload_map[] = { 739 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 740 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 741 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 742 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 743 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 744 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 745 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 746 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 747 }; 748 749 /* Update Tx offload info */ 750 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 751 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 752 snprintf(mode->info, sizeof(mode->info), "%s", 753 tx_offload_map[i].output); 754 ret = 0; 755 break; 756 } 757 } 758 return ret; 759 } 760 761 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 762 int wait_to_complete) 763 { 764 struct dpaa_if *dpaa_intf = dev->data->dev_private; 765 struct rte_eth_link *link = &dev->data->dev_link; 766 struct fman_if *fif = dev->process_private; 767 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 768 int ret, ioctl_version; 769 uint8_t count; 770 771 PMD_INIT_FUNC_TRACE(); 772 773 ioctl_version = dpaa_get_ioctl_version_number(); 774 775 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC && 776 fif->mac_type != fman_offline_internal && 777 fif->mac_type != fman_onic) { 778 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 779 ret = dpaa_get_link_status(__fif->node_name, link); 780 if (ret) 781 return ret; 782 if (link->link_status == RTE_ETH_LINK_DOWN && 783 wait_to_complete) 784 rte_delay_ms(CHECK_INTERVAL); 785 else 786 break; 787 } 788 } else { 789 link->link_status = dpaa_intf->valid; 790 if (fif->mac_type == fman_offline_internal || 791 fif->mac_type == fman_onic) { 792 /*Max supported rate for O/H port is 3.75Mpps*/ 793 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 794 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 795 } 796 } 797 798 if (ioctl_version < 2) { 799 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 800 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 801 802 if (fif->mac_type == fman_mac_1g) 803 link->link_speed = RTE_ETH_SPEED_NUM_1G; 804 else if (fif->mac_type == fman_mac_2_5g) 805 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 806 else if (fif->mac_type == fman_mac_10g) 807 link->link_speed = RTE_ETH_SPEED_NUM_10G; 808 else 809 DPAA_PMD_ERR("invalid link_speed: %s, %d", 810 dpaa_intf->name, fif->mac_type); 811 } 812 813 DPAA_PMD_INFO("Port %d Link is %s", dev->data->port_id, 814 link->link_status ? "Up" : "Down"); 815 return 0; 816 } 817 818 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 819 struct rte_eth_stats *stats) 820 { 821 PMD_INIT_FUNC_TRACE(); 822 823 fman_if_stats_get(dev->process_private, stats); 824 return 0; 825 } 826 827 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 828 { 829 PMD_INIT_FUNC_TRACE(); 830 831 fman_if_stats_reset(dev->process_private); 832 fman_if_bmi_stats_reset(dev->process_private); 833 834 return 0; 835 } 836 837 static int 838 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 839 unsigned int n) 840 { 841 unsigned int i = 0, j, num = RTE_DIM(dpaa_xstats_strings); 842 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 843 unsigned int bmi_count = sizeof(struct dpaa_if_rx_bmi_stats) / 4; 844 845 if (n < num) 846 return num; 847 848 if (xstats == NULL) 849 return 0; 850 851 fman_if_stats_get_all(dev->process_private, values, 852 sizeof(struct dpaa_if_stats) / 8); 853 854 for (i = 0; i < num - (bmi_count - 1); i++) { 855 xstats[i].id = i; 856 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 857 } 858 fman_if_bmi_stats_get_all(dev->process_private, values); 859 for (j = 0; i < num; i++, j++) { 860 xstats[i].id = i; 861 xstats[i].value = values[j]; 862 } 863 864 return i; 865 } 866 867 static int 868 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 869 struct rte_eth_xstat_name *xstats_names, 870 unsigned int limit) 871 { 872 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 873 874 if (limit < stat_cnt) 875 return stat_cnt; 876 877 if (xstats_names != NULL) 878 for (i = 0; i < stat_cnt; i++) 879 strlcpy(xstats_names[i].name, 880 dpaa_xstats_strings[i].name, 881 sizeof(xstats_names[i].name)); 882 883 return stat_cnt; 884 } 885 886 static int 887 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 888 uint64_t *values, unsigned int n) 889 { 890 unsigned int i, j, stat_cnt = RTE_DIM(dpaa_xstats_strings); 891 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 892 unsigned int bmi_count = sizeof(struct dpaa_if_rx_bmi_stats) / 4; 893 894 if (!ids) { 895 if (n < stat_cnt) 896 return stat_cnt; 897 898 if (!values) 899 return 0; 900 901 fman_if_stats_get_all(dev->process_private, values_copy, 902 sizeof(struct dpaa_if_stats) / 8); 903 904 for (i = 0; i < stat_cnt - (bmi_count - 1); i++) 905 values[i] = 906 values_copy[dpaa_xstats_strings[i].offset / 8]; 907 908 fman_if_bmi_stats_get_all(dev->process_private, values); 909 for (j = 0; i < stat_cnt; i++, j++) 910 values[i] = values_copy[j]; 911 912 return stat_cnt; 913 } 914 915 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 916 917 for (i = 0; i < n; i++) { 918 if (ids[i] >= stat_cnt) { 919 DPAA_PMD_ERR("id value isn't valid"); 920 return -1; 921 } 922 values[i] = values_copy[ids[i]]; 923 } 924 return n; 925 } 926 927 static int 928 dpaa_xstats_get_names_by_id( 929 struct rte_eth_dev *dev, 930 const uint64_t *ids, 931 struct rte_eth_xstat_name *xstats_names, 932 unsigned int limit) 933 { 934 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 935 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 936 937 if (!ids) 938 return dpaa_xstats_get_names(dev, xstats_names, limit); 939 940 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 941 942 for (i = 0; i < limit; i++) { 943 if (ids[i] >= stat_cnt) { 944 DPAA_PMD_ERR("id value isn't valid"); 945 return -1; 946 } 947 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 948 } 949 return limit; 950 } 951 952 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 953 { 954 struct fman_if *fif = dev->process_private; 955 956 PMD_INIT_FUNC_TRACE(); 957 958 if (fif->mac_type == fman_onic) { 959 DPAA_PMD_INFO("Enable promiscuous mode not supported on ONIC " 960 "port"); 961 return 0; 962 } 963 964 fman_if_promiscuous_enable(dev->process_private); 965 966 return 0; 967 } 968 969 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 970 { 971 struct fman_if *fif = dev->process_private; 972 973 PMD_INIT_FUNC_TRACE(); 974 975 if (fif->mac_type == fman_onic) { 976 DPAA_PMD_INFO("Disable promiscuous mode not supported on ONIC " 977 "port"); 978 return 0; 979 } 980 981 fman_if_promiscuous_disable(dev->process_private); 982 983 return 0; 984 } 985 986 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 987 { 988 struct fman_if *fif = dev->process_private; 989 990 PMD_INIT_FUNC_TRACE(); 991 992 if (fif->mac_type == fman_onic) { 993 DPAA_PMD_INFO("Enable Multicast not supported on ONIC port"); 994 return 0; 995 } 996 997 fman_if_set_mcast_filter_table(dev->process_private); 998 999 return 0; 1000 } 1001 1002 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 1003 { 1004 struct fman_if *fif = dev->process_private; 1005 1006 PMD_INIT_FUNC_TRACE(); 1007 1008 if (fif->mac_type == fman_onic) { 1009 DPAA_PMD_INFO("Disable Multicast not supported on ONIC port"); 1010 return 0; 1011 } 1012 1013 fman_if_reset_mcast_filter_table(dev->process_private); 1014 1015 return 0; 1016 } 1017 1018 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 1019 { 1020 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1021 struct fman_if_ic_params icp; 1022 uint32_t fd_offset; 1023 uint32_t bp_size; 1024 1025 memset(&icp, 0, sizeof(icp)); 1026 /* set ICEOF for to the default value , which is 0*/ 1027 icp.iciof = DEFAULT_ICIOF; 1028 icp.iceof = DEFAULT_RX_ICEOF; 1029 icp.icsz = DEFAULT_ICSZ; 1030 fman_if_set_ic_params(dev->process_private, &icp); 1031 1032 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 1033 fman_if_set_fdoff(dev->process_private, fd_offset); 1034 1035 /* Buffer pool size should be equal to Dataroom Size*/ 1036 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 1037 1038 fman_if_set_bp(dev->process_private, 1039 dpaa_intf->bp_info->mp->size, 1040 dpaa_intf->bp_info->bpid, bp_size); 1041 } 1042 1043 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 1044 int8_t vsp_id, uint32_t bpid) 1045 { 1046 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1047 struct fman_if *fif = dev->process_private; 1048 1049 if (fif->num_profiles) { 1050 if (vsp_id < 0) 1051 vsp_id = fif->base_profile_id; 1052 } else { 1053 if (vsp_id < 0) 1054 vsp_id = 0; 1055 } 1056 1057 if (dpaa_intf->vsp_bpid[vsp_id] && 1058 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 1059 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 1060 1061 return -1; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static 1068 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1069 uint16_t nb_desc, 1070 unsigned int socket_id __rte_unused, 1071 const struct rte_eth_rxconf *rx_conf, 1072 struct rte_mempool *mp) 1073 { 1074 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1075 struct fman_if *fif = dev->process_private; 1076 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 1077 struct qm_mcc_initfq opts = {0}; 1078 u32 ch_id, flags = 0; 1079 int ret; 1080 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 1081 uint32_t max_rx_pktlen; 1082 1083 PMD_INIT_FUNC_TRACE(); 1084 1085 if (queue_idx >= dev->data->nb_rx_queues) { 1086 rte_errno = EOVERFLOW; 1087 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1088 (void *)dev, queue_idx, dev->data->nb_rx_queues); 1089 return -rte_errno; 1090 } 1091 1092 /* Rx deferred start is not supported */ 1093 if (rx_conf->rx_deferred_start) { 1094 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 1095 return -EINVAL; 1096 } 1097 rxq->nb_desc = UINT16_MAX; 1098 rxq->offloads = rx_conf->offloads; 1099 1100 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 1101 queue_idx, rxq->fqid); 1102 1103 if (!fif->num_profiles) { 1104 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 1105 dpaa_intf->bp_info->mp != mp) { 1106 DPAA_PMD_WARN("Multiple pools on same interface not" 1107 " supported"); 1108 return -EINVAL; 1109 } 1110 } else { 1111 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 1112 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 1113 return -EINVAL; 1114 } 1115 } 1116 1117 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 1118 dpaa_intf->bp_info->mp != mp) { 1119 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 1120 return -EINVAL; 1121 } 1122 1123 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 1124 VLAN_TAG_SIZE; 1125 /* Max packet can fit in single buffer */ 1126 if (max_rx_pktlen <= buffsz) { 1127 ; 1128 } else if (dev->data->dev_conf.rxmode.offloads & 1129 RTE_ETH_RX_OFFLOAD_SCATTER) { 1130 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 1131 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 1132 "MaxSGlist %d", 1133 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 1134 rte_errno = EOVERFLOW; 1135 return -rte_errno; 1136 } 1137 } else { 1138 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 1139 " larger than a single mbuf (%u) and scattered" 1140 " mode has not been requested", max_rx_pktlen, buffsz); 1141 } 1142 1143 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 1144 1145 /* For shared interface, it's done in kernel, skip.*/ 1146 if (!fif->is_shared_mac && fif->mac_type != fman_offline_internal && 1147 fif->mac_type != fman_onic) 1148 dpaa_fman_if_pool_setup(dev); 1149 1150 if (fif->num_profiles) { 1151 int8_t vsp_id = rxq->vsp_id; 1152 1153 if (vsp_id >= 0) { 1154 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 1155 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 1156 fif, buffsz + RTE_PKTMBUF_HEADROOM); 1157 if (ret) { 1158 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 1159 return ret; 1160 } 1161 } else { 1162 DPAA_PMD_INFO("Base profile is associated to" 1163 " RXQ fqid:%d", rxq->fqid); 1164 if (fif->is_shared_mac) { 1165 DPAA_PMD_ERR("Fatal: Base profile is associated" 1166 " to shared interface on DPDK."); 1167 return -EINVAL; 1168 } 1169 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1170 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1171 } 1172 } else { 1173 dpaa_intf->vsp_bpid[0] = 1174 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1175 } 1176 1177 dpaa_intf->valid = 1; 1178 if (fif->mac_type != fman_onic) 1179 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1180 fman_if_get_sg_enable(fif), max_rx_pktlen); 1181 /* checking if push mode only, no error check for now */ 1182 if (!rxq->is_static && 1183 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1184 struct qman_portal *qp; 1185 int q_fd; 1186 1187 dpaa_push_queue_idx++; 1188 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1189 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1190 QM_FQCTRL_CTXASTASHING | 1191 QM_FQCTRL_PREFERINCACHE; 1192 opts.fqd.context_a.stashing.exclusive = 0; 1193 /* In multicore scenario stashing becomes a bottleneck on LS1046. 1194 * So do not enable stashing in this case 1195 */ 1196 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1197 opts.fqd.context_a.stashing.annotation_cl = 1198 DPAA_IF_RX_ANNOTATION_STASH; 1199 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1200 opts.fqd.context_a.stashing.context_cl = 1201 DPAA_IF_RX_CONTEXT_STASH; 1202 1203 /*Create a channel and associate given queue with the channel*/ 1204 qman_alloc_pool_range(&ch_id, 1, 1, 0); 1205 rxq->ch_id = (u16)ch_id; 1206 1207 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1208 opts.fqd.dest.channel = rxq->ch_id; 1209 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1210 flags = QMAN_INITFQ_FLAG_SCHED; 1211 1212 /* Configure tail drop */ 1213 if (dpaa_intf->cgr_rx) { 1214 opts.we_mask |= QM_INITFQ_WE_CGID; 1215 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1216 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1217 } 1218 ret = qman_init_fq(rxq, flags, &opts); 1219 if (ret) { 1220 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1221 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1222 return ret; 1223 } 1224 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1225 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1226 } else { 1227 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1228 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1229 } 1230 1231 rxq->is_static = true; 1232 1233 /* Allocate qman specific portals */ 1234 qp = fsl_qman_fq_portal_create(&q_fd); 1235 if (!qp) { 1236 DPAA_PMD_ERR("Unable to alloc fq portal"); 1237 return -1; 1238 } 1239 rxq->qp = qp; 1240 1241 /* Set up the device interrupt handler */ 1242 if (dev->intr_handle == NULL) { 1243 struct rte_dpaa_device *dpaa_dev; 1244 struct rte_device *rdev = dev->device; 1245 1246 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1247 device); 1248 dev->intr_handle = dpaa_dev->intr_handle; 1249 if (rte_intr_vec_list_alloc(dev->intr_handle, 1250 NULL, dpaa_push_mode_max_queue)) { 1251 DPAA_PMD_ERR("intr_vec alloc failed"); 1252 return -ENOMEM; 1253 } 1254 if (rte_intr_nb_efd_set(dev->intr_handle, 1255 dpaa_push_mode_max_queue)) 1256 return -rte_errno; 1257 1258 if (rte_intr_max_intr_set(dev->intr_handle, 1259 dpaa_push_mode_max_queue)) 1260 return -rte_errno; 1261 } 1262 1263 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT)) 1264 return -rte_errno; 1265 1266 if (rte_intr_vec_list_index_set(dev->intr_handle, 1267 queue_idx, queue_idx + 1)) 1268 return -rte_errno; 1269 1270 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx, 1271 q_fd)) 1272 return -rte_errno; 1273 1274 rxq->q_fd = q_fd; 1275 } 1276 rxq->bp_array = rte_dpaa_bpid_info; 1277 dev->data->rx_queues[queue_idx] = rxq; 1278 1279 /* configure the CGR size as per the desc size */ 1280 if (dpaa_intf->cgr_rx) { 1281 struct qm_mcc_initcgr cgr_opts = {0}; 1282 1283 rxq->nb_desc = nb_desc; 1284 /* Enable tail drop with cgr on this queue */ 1285 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1286 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1287 if (ret) { 1288 DPAA_PMD_WARN( 1289 "rx taildrop modify fail on fqid %d (ret=%d)", 1290 rxq->fqid, ret); 1291 } 1292 } 1293 1294 /* Enable main queue to receive error packets also by default */ 1295 if (fif->mac_type != fman_offline_internal && 1296 fif->mac_type != fman_onic) 1297 fman_if_set_err_fqid(fif, rxq->fqid); 1298 1299 return 0; 1300 } 1301 1302 int 1303 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1304 int eth_rx_queue_id, 1305 u16 ch_id, 1306 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1307 { 1308 int ret; 1309 u32 flags = 0; 1310 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1311 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1312 struct qm_mcc_initfq opts = {0}; 1313 1314 if (dpaa_push_mode_max_queue) { 1315 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible"); 1316 DPAA_PMD_WARN("PUSH mode already enabled for first %d queues.", 1317 dpaa_push_mode_max_queue); 1318 DPAA_PMD_WARN("To disable set DPAA_PUSH_QUEUES_NUMBER to 0"); 1319 } 1320 1321 dpaa_poll_queue_default_config(&opts); 1322 1323 switch (queue_conf->ev.sched_type) { 1324 case RTE_SCHED_TYPE_ATOMIC: 1325 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1326 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1327 * configuration with HOLD_ACTIVE setting 1328 */ 1329 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1330 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1331 break; 1332 case RTE_SCHED_TYPE_ORDERED: 1333 DPAA_PMD_ERR("Ordered queue schedule type is not supported"); 1334 return -1; 1335 default: 1336 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1337 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1338 break; 1339 } 1340 1341 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1342 opts.fqd.dest.channel = ch_id; 1343 opts.fqd.dest.wq = queue_conf->ev.priority; 1344 1345 if (dpaa_intf->cgr_rx) { 1346 opts.we_mask |= QM_INITFQ_WE_CGID; 1347 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1348 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1349 } 1350 1351 flags = QMAN_INITFQ_FLAG_SCHED; 1352 1353 ret = qman_init_fq(rxq, flags, &opts); 1354 if (ret) { 1355 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1356 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1357 return ret; 1358 } 1359 1360 /* copy configuration which needs to be filled during dequeue */ 1361 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1362 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1363 1364 return ret; 1365 } 1366 1367 int 1368 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1369 int eth_rx_queue_id) 1370 { 1371 struct qm_mcc_initfq opts = {0}; 1372 int ret; 1373 u32 flags = 0; 1374 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1375 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1376 1377 qman_retire_fq(rxq, NULL); 1378 qman_oos_fq(rxq); 1379 ret = qman_init_fq(rxq, flags, &opts); 1380 if (ret) { 1381 DPAA_PMD_ERR("detach rx fqid %d failed with ret: %d", 1382 rxq->fqid, ret); 1383 } 1384 1385 rxq->cb.dqrr_dpdk_cb = NULL; 1386 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1387 1388 return 0; 1389 } 1390 1391 static 1392 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1393 uint16_t nb_desc __rte_unused, 1394 unsigned int socket_id __rte_unused, 1395 const struct rte_eth_txconf *tx_conf) 1396 { 1397 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1398 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1399 1400 PMD_INIT_FUNC_TRACE(); 1401 1402 /* Tx deferred start is not supported */ 1403 if (tx_conf->tx_deferred_start) { 1404 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1405 return -EINVAL; 1406 } 1407 txq->nb_desc = UINT16_MAX; 1408 txq->offloads = tx_conf->offloads; 1409 1410 if (queue_idx >= dev->data->nb_tx_queues) { 1411 rte_errno = EOVERFLOW; 1412 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1413 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1414 return -rte_errno; 1415 } 1416 1417 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1418 queue_idx, txq->fqid); 1419 dev->data->tx_queues[queue_idx] = txq; 1420 1421 return 0; 1422 } 1423 1424 static uint32_t 1425 dpaa_dev_rx_queue_count(void *rx_queue) 1426 { 1427 struct qman_fq *rxq = rx_queue; 1428 u32 frm_cnt = 0; 1429 1430 PMD_INIT_FUNC_TRACE(); 1431 1432 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1433 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1434 rx_queue, frm_cnt); 1435 } 1436 return frm_cnt; 1437 } 1438 1439 static int dpaa_link_down(struct rte_eth_dev *dev) 1440 { 1441 struct fman_if *fif = dev->process_private; 1442 struct __fman_if *__fif; 1443 1444 PMD_INIT_FUNC_TRACE(); 1445 1446 __fif = container_of(fif, struct __fman_if, __if); 1447 1448 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC && 1449 fif->mac_type != fman_offline_internal && 1450 fif->mac_type != fman_onic) 1451 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1452 else 1453 return dpaa_eth_dev_stop(dev); 1454 return 0; 1455 } 1456 1457 static int dpaa_link_up(struct rte_eth_dev *dev) 1458 { 1459 struct fman_if *fif = dev->process_private; 1460 struct __fman_if *__fif; 1461 1462 PMD_INIT_FUNC_TRACE(); 1463 1464 __fif = container_of(fif, struct __fman_if, __if); 1465 1466 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC && 1467 fif->mac_type != fman_offline_internal && 1468 fif->mac_type != fman_onic) 1469 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1470 else 1471 dpaa_eth_dev_start(dev); 1472 return 0; 1473 } 1474 1475 static int 1476 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1477 struct rte_eth_fc_conf *fc_conf) 1478 { 1479 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1480 struct rte_eth_fc_conf *net_fc; 1481 1482 PMD_INIT_FUNC_TRACE(); 1483 1484 if (!(dpaa_intf->fc_conf)) { 1485 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1486 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1487 if (!dpaa_intf->fc_conf) { 1488 DPAA_PMD_ERR("unable to save flow control info"); 1489 return -ENOMEM; 1490 } 1491 } 1492 net_fc = dpaa_intf->fc_conf; 1493 1494 if (fc_conf->high_water < fc_conf->low_water) { 1495 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1496 return -EINVAL; 1497 } 1498 1499 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1500 return 0; 1501 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1502 fc_conf->mode == RTE_ETH_FC_FULL) { 1503 fman_if_set_fc_threshold(dev->process_private, 1504 fc_conf->high_water, 1505 fc_conf->low_water, 1506 dpaa_intf->bp_info->bpid); 1507 if (fc_conf->pause_time) 1508 fman_if_set_fc_quanta(dev->process_private, 1509 fc_conf->pause_time); 1510 } 1511 1512 /* Save the information in dpaa device */ 1513 net_fc->pause_time = fc_conf->pause_time; 1514 net_fc->high_water = fc_conf->high_water; 1515 net_fc->low_water = fc_conf->low_water; 1516 net_fc->send_xon = fc_conf->send_xon; 1517 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1518 net_fc->mode = fc_conf->mode; 1519 net_fc->autoneg = fc_conf->autoneg; 1520 1521 return 0; 1522 } 1523 1524 static int 1525 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1526 struct rte_eth_fc_conf *fc_conf) 1527 { 1528 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1529 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1530 int ret; 1531 1532 PMD_INIT_FUNC_TRACE(); 1533 1534 if (net_fc) { 1535 fc_conf->pause_time = net_fc->pause_time; 1536 fc_conf->high_water = net_fc->high_water; 1537 fc_conf->low_water = net_fc->low_water; 1538 fc_conf->send_xon = net_fc->send_xon; 1539 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1540 fc_conf->mode = net_fc->mode; 1541 fc_conf->autoneg = net_fc->autoneg; 1542 return 0; 1543 } 1544 ret = fman_if_get_fc_threshold(dev->process_private); 1545 if (ret) { 1546 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1547 fc_conf->pause_time = 1548 fman_if_get_fc_quanta(dev->process_private); 1549 } else { 1550 fc_conf->mode = RTE_ETH_FC_NONE; 1551 } 1552 1553 return 0; 1554 } 1555 1556 static int 1557 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1558 struct rte_ether_addr *addr, 1559 uint32_t index, 1560 __rte_unused uint32_t pool) 1561 { 1562 int ret; 1563 struct fman_if *fif = dev->process_private; 1564 1565 PMD_INIT_FUNC_TRACE(); 1566 1567 if (fif->mac_type == fman_offline_internal) { 1568 DPAA_PMD_DEBUG("Add MAC Address not supported on O/H port"); 1569 return 0; 1570 } 1571 1572 if (fif->mac_type == fman_onic) { 1573 DPAA_PMD_INFO("Add MAC Address not supported on ONIC port"); 1574 return 0; 1575 } 1576 1577 ret = fman_if_add_mac_addr(dev->process_private, 1578 addr->addr_bytes, index); 1579 1580 if (ret) 1581 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1582 return 0; 1583 } 1584 1585 static void 1586 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1587 uint32_t index) 1588 { 1589 struct fman_if *fif = dev->process_private; 1590 1591 PMD_INIT_FUNC_TRACE(); 1592 1593 if (fif->mac_type == fman_offline_internal) { 1594 DPAA_PMD_DEBUG("Remove MAC Address not supported on O/H port"); 1595 return; 1596 } 1597 1598 if (fif->mac_type == fman_onic) { 1599 DPAA_PMD_INFO("Remove MAC Address not supported on ONIC port"); 1600 return; 1601 } 1602 1603 fman_if_clear_mac_addr(dev->process_private, index); 1604 } 1605 1606 static int 1607 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1608 struct rte_ether_addr *addr) 1609 { 1610 int ret; 1611 struct fman_if *fif = dev->process_private; 1612 1613 PMD_INIT_FUNC_TRACE(); 1614 1615 if (fif->mac_type == fman_offline_internal) { 1616 DPAA_PMD_DEBUG("Set MAC Address not supported on O/H port"); 1617 return 0; 1618 } 1619 1620 if (fif->mac_type == fman_onic) { 1621 DPAA_PMD_INFO("Set MAC Address not supported on ONIC port"); 1622 return 0; 1623 } 1624 1625 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1626 if (ret) 1627 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1628 1629 return ret; 1630 } 1631 1632 static int 1633 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1634 struct rte_eth_rss_conf *rss_conf) 1635 { 1636 struct rte_eth_dev_data *data = dev->data; 1637 struct rte_eth_conf *eth_conf = &data->dev_conf; 1638 1639 PMD_INIT_FUNC_TRACE(); 1640 1641 if (!(default_q || fmc_q)) { 1642 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1643 DPAA_PMD_ERR("FM port configuration: Failed"); 1644 return -1; 1645 } 1646 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1647 } else { 1648 DPAA_PMD_ERR("Function not supported"); 1649 return -ENOTSUP; 1650 } 1651 return 0; 1652 } 1653 1654 static int 1655 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1656 struct rte_eth_rss_conf *rss_conf) 1657 { 1658 struct rte_eth_dev_data *data = dev->data; 1659 struct rte_eth_conf *eth_conf = &data->dev_conf; 1660 1661 /* dpaa does not support rss_key, so length should be 0*/ 1662 rss_conf->rss_key_len = 0; 1663 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1664 return 0; 1665 } 1666 1667 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1668 uint16_t queue_id) 1669 { 1670 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1671 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1672 1673 if (!rxq->is_static) 1674 return -EINVAL; 1675 1676 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1677 } 1678 1679 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1680 uint16_t queue_id) 1681 { 1682 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1683 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1684 uint32_t temp; 1685 ssize_t temp1; 1686 1687 if (!rxq->is_static) 1688 return -EINVAL; 1689 1690 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1691 1692 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1693 if (temp1 != sizeof(temp)) 1694 DPAA_PMD_DEBUG("read did not return anything"); 1695 1696 qman_fq_portal_thread_irq(rxq->qp); 1697 1698 return 0; 1699 } 1700 1701 static void 1702 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1703 struct rte_eth_rxq_info *qinfo) 1704 { 1705 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1706 struct qman_fq *rxq; 1707 int ret; 1708 1709 rxq = dev->data->rx_queues[queue_id]; 1710 1711 qinfo->mp = dpaa_intf->bp_info->mp; 1712 qinfo->scattered_rx = dev->data->scattered_rx; 1713 qinfo->nb_desc = rxq->nb_desc; 1714 1715 /* Report the HW Rx buffer length to user */ 1716 ret = fman_if_get_maxfrm(dev->process_private); 1717 if (ret > 0) 1718 qinfo->rx_buf_size = ret; 1719 1720 qinfo->conf.rx_free_thresh = 1; 1721 qinfo->conf.rx_drop_en = 1; 1722 qinfo->conf.rx_deferred_start = 0; 1723 qinfo->conf.offloads = rxq->offloads; 1724 } 1725 1726 static void 1727 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1728 struct rte_eth_txq_info *qinfo) 1729 { 1730 struct qman_fq *txq; 1731 1732 txq = dev->data->tx_queues[queue_id]; 1733 1734 qinfo->nb_desc = txq->nb_desc; 1735 qinfo->conf.tx_thresh.pthresh = 0; 1736 qinfo->conf.tx_thresh.hthresh = 0; 1737 qinfo->conf.tx_thresh.wthresh = 0; 1738 1739 qinfo->conf.tx_free_thresh = 0; 1740 qinfo->conf.tx_rs_thresh = 0; 1741 qinfo->conf.offloads = txq->offloads; 1742 qinfo->conf.tx_deferred_start = 0; 1743 } 1744 1745 static struct eth_dev_ops dpaa_devops = { 1746 .dev_configure = dpaa_eth_dev_configure, 1747 .dev_start = dpaa_eth_dev_start, 1748 .dev_stop = dpaa_eth_dev_stop, 1749 .dev_close = dpaa_eth_dev_close, 1750 .dev_infos_get = dpaa_eth_dev_info, 1751 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1752 1753 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1754 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1755 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1756 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1757 .rxq_info_get = dpaa_rxq_info_get, 1758 .txq_info_get = dpaa_txq_info_get, 1759 1760 .flow_ctrl_get = dpaa_flow_ctrl_get, 1761 .flow_ctrl_set = dpaa_flow_ctrl_set, 1762 1763 .link_update = dpaa_eth_link_update, 1764 .stats_get = dpaa_eth_stats_get, 1765 .xstats_get = dpaa_dev_xstats_get, 1766 .xstats_get_by_id = dpaa_xstats_get_by_id, 1767 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1768 .xstats_get_names = dpaa_xstats_get_names, 1769 .xstats_reset = dpaa_eth_stats_reset, 1770 .stats_reset = dpaa_eth_stats_reset, 1771 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1772 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1773 .allmulticast_enable = dpaa_eth_multicast_enable, 1774 .allmulticast_disable = dpaa_eth_multicast_disable, 1775 .mtu_set = dpaa_mtu_set, 1776 .dev_set_link_down = dpaa_link_down, 1777 .dev_set_link_up = dpaa_link_up, 1778 .mac_addr_add = dpaa_dev_add_mac_addr, 1779 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1780 .mac_addr_set = dpaa_dev_set_mac_addr, 1781 1782 .fw_version_get = dpaa_fw_version_get, 1783 1784 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1785 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1786 .rss_hash_update = dpaa_dev_rss_hash_update, 1787 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1788 .timesync_enable = dpaa_timesync_enable, 1789 .timesync_disable = dpaa_timesync_disable, 1790 .timesync_read_time = dpaa_timesync_read_time, 1791 .timesync_write_time = dpaa_timesync_write_time, 1792 .timesync_adjust_time = dpaa_timesync_adjust_time, 1793 .timesync_read_rx_timestamp = dpaa_timesync_read_rx_timestamp, 1794 .timesync_read_tx_timestamp = dpaa_timesync_read_tx_timestamp, 1795 }; 1796 1797 static bool 1798 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1799 { 1800 if (strcmp(dev->device->driver->name, 1801 drv->driver.name)) 1802 return false; 1803 1804 return true; 1805 } 1806 1807 static bool 1808 is_dpaa_supported(struct rte_eth_dev *dev) 1809 { 1810 return is_device_supported(dev, &rte_dpaa_pmd); 1811 } 1812 1813 int 1814 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1815 { 1816 struct rte_eth_dev *dev; 1817 1818 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1819 1820 dev = &rte_eth_devices[port]; 1821 1822 if (!is_dpaa_supported(dev)) 1823 return -ENOTSUP; 1824 1825 if (on) 1826 fman_if_loopback_enable(dev->process_private); 1827 else 1828 fman_if_loopback_disable(dev->process_private); 1829 1830 return 0; 1831 } 1832 1833 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1834 struct fman_if *fman_intf) 1835 { 1836 struct rte_eth_fc_conf *fc_conf; 1837 int ret; 1838 1839 PMD_INIT_FUNC_TRACE(); 1840 1841 if (!(dpaa_intf->fc_conf)) { 1842 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1843 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1844 if (!dpaa_intf->fc_conf) { 1845 DPAA_PMD_ERR("unable to save flow control info"); 1846 return -ENOMEM; 1847 } 1848 } 1849 fc_conf = dpaa_intf->fc_conf; 1850 ret = fman_if_get_fc_threshold(fman_intf); 1851 if (ret) { 1852 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1853 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1854 } else { 1855 fc_conf->mode = RTE_ETH_FC_NONE; 1856 } 1857 1858 return 0; 1859 } 1860 1861 /* Initialise an Rx FQ */ 1862 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1863 uint32_t fqid) 1864 { 1865 struct qm_mcc_initfq opts = {0}; 1866 int ret; 1867 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1868 struct qm_mcc_initcgr cgr_opts = { 1869 .we_mask = QM_CGR_WE_CS_THRES | 1870 QM_CGR_WE_CSTD_EN | 1871 QM_CGR_WE_MODE, 1872 .cgr = { 1873 .cstd_en = QM_CGR_EN, 1874 .mode = QMAN_CGR_MODE_FRAME 1875 } 1876 }; 1877 1878 if (fmc_q || default_q) { 1879 ret = qman_reserve_fqid(fqid); 1880 if (ret) { 1881 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1882 fqid, ret); 1883 return -EINVAL; 1884 } 1885 } 1886 1887 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1888 ret = qman_create_fq(fqid, flags, fq); 1889 if (ret) { 1890 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1891 fqid, ret); 1892 return ret; 1893 } 1894 fq->is_static = false; 1895 1896 dpaa_poll_queue_default_config(&opts); 1897 1898 if (cgr_rx) { 1899 /* Enable tail drop with cgr on this queue */ 1900 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1901 cgr_rx->cb = NULL; 1902 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1903 &cgr_opts); 1904 if (ret) { 1905 DPAA_PMD_WARN( 1906 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1907 fq->fqid, ret); 1908 goto without_cgr; 1909 } 1910 opts.we_mask |= QM_INITFQ_WE_CGID; 1911 opts.fqd.cgid = cgr_rx->cgrid; 1912 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1913 } 1914 without_cgr: 1915 ret = qman_init_fq(fq, 0, &opts); 1916 if (ret) 1917 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1918 return ret; 1919 } 1920 1921 uint8_t fm_default_vsp_id(struct fman_if *fif) 1922 { 1923 /* Avoid being same as base profile which could be used 1924 * for kernel interface of shared mac. 1925 */ 1926 if (fif->base_profile_id) 1927 return 0; 1928 else 1929 return DPAA_DEFAULT_RXQ_VSP_ID; 1930 } 1931 1932 /* Initialise a Tx FQ */ 1933 static int dpaa_tx_queue_init(struct qman_fq *fq, 1934 struct fman_if *fman_intf, 1935 struct qman_cgr *cgr_tx) 1936 { 1937 struct qm_mcc_initfq opts = {0}; 1938 struct qm_mcc_initcgr cgr_opts = { 1939 .we_mask = QM_CGR_WE_CS_THRES | 1940 QM_CGR_WE_CSTD_EN | 1941 QM_CGR_WE_MODE, 1942 .cgr = { 1943 .cstd_en = QM_CGR_EN, 1944 .mode = QMAN_CGR_MODE_FRAME 1945 } 1946 }; 1947 int ret; 1948 1949 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1950 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1951 if (ret) { 1952 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1953 return ret; 1954 } 1955 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1956 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1957 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1958 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1959 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1960 opts.fqd.context_b = 0; 1961 if (dpaa_ieee_1588) { 1962 opts.fqd.context_a.lo = 0; 1963 opts.fqd.context_a.hi = fman_dealloc_bufs_mask_hi; 1964 } else { 1965 /* no tx-confirmation */ 1966 opts.fqd.context_a.lo = fman_dealloc_bufs_mask_lo; 1967 opts.fqd.context_a.hi = DPAA_FQD_CTX_A_OVERRIDE_FQ | 1968 fman_dealloc_bufs_mask_hi; 1969 } 1970 1971 if (fman_ip_rev >= FMAN_V3) 1972 /* Set B0V bit in contextA to set ASPID to 0 */ 1973 opts.fqd.context_a.hi |= DPAA_FQD_CTX_A_B0_FIELD_VALID; 1974 1975 if (fman_intf->mac_type == fman_offline_internal || 1976 fman_intf->mac_type == fman_onic) { 1977 opts.fqd.context_a.lo |= DPAA_FQD_CTX_A2_VSPE_BIT; 1978 opts.fqd.context_b = fm_default_vsp_id(fman_intf) << 1979 DPAA_FQD_CTX_B_SHIFT_BITS; 1980 } 1981 1982 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1983 1984 if (cgr_tx) { 1985 /* Enable tail drop with cgr on this queue */ 1986 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1987 td_tx_threshold, 0); 1988 cgr_tx->cb = NULL; 1989 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1990 &cgr_opts); 1991 if (ret) { 1992 DPAA_PMD_WARN( 1993 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1994 fq->fqid, ret); 1995 goto without_cgr; 1996 } 1997 opts.we_mask |= QM_INITFQ_WE_CGID; 1998 opts.fqd.cgid = cgr_tx->cgrid; 1999 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 2000 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d", 2001 td_tx_threshold); 2002 } 2003 without_cgr: 2004 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 2005 if (ret) 2006 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 2007 return ret; 2008 } 2009 2010 static int 2011 dpaa_tx_conf_queue_init(struct qman_fq *fq) 2012 { 2013 struct qm_mcc_initfq opts = {0}; 2014 int ret; 2015 2016 PMD_INIT_FUNC_TRACE(); 2017 2018 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID, fq); 2019 if (ret) { 2020 DPAA_PMD_ERR("create Tx_conf failed with ret: %d", ret); 2021 return ret; 2022 } 2023 2024 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 2025 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 2026 ret = qman_init_fq(fq, 0, &opts); 2027 if (ret) 2028 DPAA_PMD_ERR("init Tx_conf fqid %d failed with ret: %d", 2029 fq->fqid, ret); 2030 return ret; 2031 } 2032 2033 #if defined(RTE_LIBRTE_DPAA_DEBUG_DRIVER) 2034 /* Initialise a DEBUG FQ ([rt]x_error, rx_default) */ 2035 static int dpaa_def_queue_init(struct qman_fq *fq, uint32_t fqid) 2036 { 2037 struct qm_mcc_initfq opts = {0}; 2038 int ret; 2039 2040 PMD_INIT_FUNC_TRACE(); 2041 2042 ret = qman_reserve_fqid(fqid); 2043 if (ret) { 2044 DPAA_PMD_ERR("Reserve fqid %d failed with ret: %d", 2045 fqid, ret); 2046 return -EINVAL; 2047 } 2048 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 2049 DPAA_PMD_DEBUG("Creating fq %p, fqid %d", fq, fqid); 2050 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 2051 if (ret) { 2052 DPAA_PMD_ERR("create fqid %d failed with ret: %d", 2053 fqid, ret); 2054 return ret; 2055 } 2056 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 2057 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 2058 ret = qman_init_fq(fq, 0, &opts); 2059 if (ret) 2060 DPAA_PMD_ERR("init fqid %d failed with ret: %d", 2061 fqid, ret); 2062 return ret; 2063 } 2064 #endif 2065 2066 /* Initialise a network interface */ 2067 static int 2068 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 2069 { 2070 struct rte_dpaa_device *dpaa_device; 2071 struct fm_eth_port_cfg *cfg; 2072 struct dpaa_if *dpaa_intf; 2073 struct fman_if *fman_intf; 2074 int dev_id; 2075 2076 PMD_INIT_FUNC_TRACE(); 2077 2078 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 2079 dev_id = dpaa_device->id.dev_id; 2080 cfg = dpaa_get_eth_port_cfg(dev_id); 2081 fman_intf = cfg->fman_if; 2082 eth_dev->process_private = fman_intf; 2083 2084 /* Plugging of UCODE burst API not supported in Secondary */ 2085 dpaa_intf = eth_dev->data->dev_private; 2086 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2087 if (dpaa_intf->cgr_tx) 2088 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 2089 else 2090 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 2091 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 2092 qman_set_fq_lookup_table( 2093 dpaa_intf->rx_queues->qman_fq_lookup_table); 2094 #endif 2095 2096 return 0; 2097 } 2098 2099 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2100 static int 2101 dpaa_error_queue_init(struct dpaa_if *dpaa_intf, 2102 struct fman_if *fman_intf) 2103 { 2104 int i, ret; 2105 struct qman_fq *err_queues = dpaa_intf->debug_queues; 2106 uint32_t err_fqid = 0; 2107 2108 if (fman_intf->is_shared_mac) { 2109 DPAA_PMD_DEBUG("Shared MAC's err queues are handled in kernel"); 2110 return 0; 2111 } 2112 2113 for (i = 0; i < DPAA_DEBUG_FQ_MAX_NUM; i++) { 2114 if (i == DPAA_DEBUG_FQ_RX_ERROR) 2115 err_fqid = fman_intf->fqid_rx_err; 2116 else if (i == DPAA_DEBUG_FQ_TX_ERROR) 2117 err_fqid = fman_intf->fqid_tx_err; 2118 else 2119 continue; 2120 ret = dpaa_def_queue_init(&err_queues[i], err_fqid); 2121 if (ret) { 2122 DPAA_PMD_ERR("DPAA %s ERROR queue init failed!", 2123 i == DPAA_DEBUG_FQ_RX_ERROR ? 2124 "RX" : "TX"); 2125 return ret; 2126 } 2127 err_queues[i].dpaa_intf = dpaa_intf; 2128 } 2129 2130 return 0; 2131 } 2132 #endif 2133 2134 static int 2135 check_devargs_handler(__rte_unused const char *key, const char *value, 2136 __rte_unused void *opaque) 2137 { 2138 if (strcmp(value, "1")) 2139 return -1; 2140 2141 return 0; 2142 } 2143 2144 static int 2145 dpaa_get_devargs(struct rte_devargs *devargs, const char *key) 2146 { 2147 struct rte_kvargs *kvlist; 2148 2149 if (!devargs) 2150 return 0; 2151 2152 kvlist = rte_kvargs_parse(devargs->args, NULL); 2153 if (!kvlist) 2154 return 0; 2155 2156 if (!rte_kvargs_count(kvlist, key)) { 2157 rte_kvargs_free(kvlist); 2158 return 0; 2159 } 2160 2161 if (rte_kvargs_process(kvlist, key, 2162 check_devargs_handler, NULL) < 0) { 2163 rte_kvargs_free(kvlist); 2164 return 0; 2165 } 2166 rte_kvargs_free(kvlist); 2167 2168 return 1; 2169 } 2170 2171 /* Initialise a network interface */ 2172 static int 2173 dpaa_dev_init(struct rte_eth_dev *eth_dev) 2174 { 2175 int num_rx_fqs, fqid; 2176 int loop, ret = 0; 2177 int dev_id; 2178 struct rte_dpaa_device *dpaa_device; 2179 struct dpaa_if *dpaa_intf; 2180 struct fm_eth_port_cfg *cfg; 2181 struct fman_if *fman_intf; 2182 struct fman_if_bpool *bp, *tmp_bp; 2183 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 2184 uint32_t cgrid_tx[MAX_DPAA_CORES]; 2185 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 2186 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 2187 int8_t vsp_id = -1; 2188 struct rte_device *dev = eth_dev->device; 2189 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2190 char *penv; 2191 #endif 2192 2193 PMD_INIT_FUNC_TRACE(); 2194 2195 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 2196 dev_id = dpaa_device->id.dev_id; 2197 dpaa_intf = eth_dev->data->dev_private; 2198 cfg = dpaa_get_eth_port_cfg(dev_id); 2199 fman_intf = cfg->fman_if; 2200 2201 dpaa_intf->name = dpaa_device->name; 2202 2203 /* save fman_if & cfg in the interface structure */ 2204 eth_dev->process_private = fman_intf; 2205 dpaa_intf->ifid = dev_id; 2206 dpaa_intf->cfg = cfg; 2207 2208 if (dpaa_get_devargs(dev->devargs, DRIVER_IEEE1588)) 2209 dpaa_ieee_1588 = 1; 2210 2211 memset((char *)dev_rx_fqids, 0, 2212 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 2213 2214 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 2215 2216 /* Initialize Rx FQ's */ 2217 if (default_q) { 2218 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 2219 } else if (fmc_q) { 2220 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 2221 dev_vspids, 2222 DPAA_MAX_NUM_PCD_QUEUES); 2223 if (num_rx_fqs < 0) { 2224 DPAA_PMD_ERR("%s FMC initializes failed!", 2225 dpaa_intf->name); 2226 goto free_rx; 2227 } 2228 if (!num_rx_fqs) { 2229 if (fman_intf->mac_type == fman_offline_internal || 2230 fman_intf->mac_type == fman_onic) { 2231 ret = -ENODEV; 2232 goto free_rx; 2233 } 2234 DPAA_PMD_WARN("%s is not configured by FMC.", 2235 dpaa_intf->name); 2236 } 2237 } else { 2238 /* FMCLESS mode, load balance to multiple cores.*/ 2239 num_rx_fqs = rte_lcore_count(); 2240 } 2241 2242 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 2243 * queues. 2244 */ 2245 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 2246 DPAA_PMD_ERR("Invalid number of RX queues"); 2247 return -EINVAL; 2248 } 2249 2250 if (num_rx_fqs > 0) { 2251 dpaa_intf->rx_queues = rte_zmalloc(NULL, 2252 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 2253 if (!dpaa_intf->rx_queues) { 2254 DPAA_PMD_ERR("Failed to alloc mem for RX queues"); 2255 return -ENOMEM; 2256 } 2257 } else { 2258 dpaa_intf->rx_queues = NULL; 2259 } 2260 2261 memset(cgrid, 0, sizeof(cgrid)); 2262 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 2263 2264 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 2265 * Tx tail drop is disabled. 2266 */ 2267 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 2268 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 2269 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 2270 td_tx_threshold); 2271 /* if a very large value is being configured */ 2272 if (td_tx_threshold > UINT16_MAX) 2273 td_tx_threshold = CGR_RX_PERFQ_THRESH; 2274 } 2275 2276 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2277 penv = getenv("DPAA_DISPLAY_FRAME_AND_PARSER_RESULT"); 2278 if (penv) 2279 dpaa_force_display_frame_set(atoi(penv)); 2280 #endif 2281 2282 /* If congestion control is enabled globally*/ 2283 if (num_rx_fqs > 0 && td_threshold) { 2284 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 2285 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 2286 if (!dpaa_intf->cgr_rx) { 2287 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx"); 2288 ret = -ENOMEM; 2289 goto free_rx; 2290 } 2291 2292 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 2293 if (ret != num_rx_fqs) { 2294 DPAA_PMD_WARN("insufficient CGRIDs available"); 2295 ret = -EINVAL; 2296 goto free_rx; 2297 } 2298 } else { 2299 dpaa_intf->cgr_rx = NULL; 2300 } 2301 2302 if (!fmc_q && !default_q) { 2303 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 2304 num_rx_fqs, 0); 2305 if (ret < 0) { 2306 DPAA_PMD_ERR("Failed to alloc rx fqid's"); 2307 goto free_rx; 2308 } 2309 } 2310 2311 for (loop = 0; loop < num_rx_fqs; loop++) { 2312 if (default_q) 2313 fqid = cfg->rx_def; 2314 else 2315 fqid = dev_rx_fqids[loop]; 2316 2317 vsp_id = dev_vspids[loop]; 2318 2319 if (dpaa_intf->cgr_rx) 2320 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 2321 2322 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 2323 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 2324 fqid); 2325 if (ret) 2326 goto free_rx; 2327 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 2328 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 2329 } 2330 dpaa_intf->nb_rx_queues = num_rx_fqs; 2331 2332 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 2333 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 2334 MAX_DPAA_CORES, MAX_CACHELINE); 2335 if (!dpaa_intf->tx_queues) { 2336 DPAA_PMD_ERR("Failed to alloc mem for TX queues"); 2337 ret = -ENOMEM; 2338 goto free_rx; 2339 } 2340 2341 dpaa_intf->tx_conf_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 2342 MAX_DPAA_CORES, MAX_CACHELINE); 2343 if (!dpaa_intf->tx_conf_queues) { 2344 DPAA_PMD_ERR("Failed to alloc mem for TX conf queues"); 2345 ret = -ENOMEM; 2346 goto free_rx; 2347 } 2348 2349 /* If congestion control is enabled globally*/ 2350 if (td_tx_threshold) { 2351 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 2352 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 2353 MAX_CACHELINE); 2354 if (!dpaa_intf->cgr_tx) { 2355 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx"); 2356 ret = -ENOMEM; 2357 goto free_rx; 2358 } 2359 2360 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 2361 1, 0); 2362 if (ret != MAX_DPAA_CORES) { 2363 DPAA_PMD_WARN("insufficient CGRIDs available"); 2364 ret = -EINVAL; 2365 goto free_rx; 2366 } 2367 } else { 2368 dpaa_intf->cgr_tx = NULL; 2369 } 2370 2371 2372 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2373 if (dpaa_intf->cgr_tx) 2374 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2375 2376 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2377 fman_intf, 2378 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2379 if (ret) 2380 goto free_tx; 2381 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2382 2383 if (dpaa_ieee_1588) { 2384 ret = dpaa_tx_conf_queue_init(&dpaa_intf->tx_conf_queues[loop]); 2385 if (ret) 2386 goto free_tx; 2387 2388 dpaa_intf->tx_conf_queues[loop].dpaa_intf = dpaa_intf; 2389 dpaa_intf->tx_queues[loop].tx_conf_queue = &dpaa_intf->tx_conf_queues[loop]; 2390 } 2391 } 2392 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2393 #if defined(RTE_LIBRTE_DPAA_DEBUG_DRIVER) 2394 ret = dpaa_error_queue_init(dpaa_intf, fman_intf); 2395 if (ret) 2396 goto free_tx; 2397 #endif 2398 DPAA_PMD_DEBUG("All frame queues created"); 2399 2400 /* Get the initial configuration for flow control */ 2401 if (fman_intf->mac_type != fman_offline_internal && 2402 fman_intf->mac_type != fman_onic) 2403 dpaa_fc_set_default(dpaa_intf, fman_intf); 2404 2405 /* reset bpool list, initialize bpool dynamically */ 2406 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2407 list_del(&bp->node); 2408 rte_free(bp); 2409 } 2410 2411 /* Populate ethdev structure */ 2412 eth_dev->dev_ops = &dpaa_devops; 2413 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2414 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2415 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2416 2417 /* Allocate memory for storing MAC addresses */ 2418 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2419 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2420 if (eth_dev->data->mac_addrs == NULL) { 2421 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2422 "store MAC addresses", 2423 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2424 ret = -ENOMEM; 2425 goto free_tx; 2426 } 2427 2428 /* copy the primary mac address */ 2429 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2430 2431 DPAA_PMD_INFO("net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT, 2432 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2433 2434 if (!fman_intf->is_shared_mac && 2435 fman_intf->mac_type != fman_offline_internal && 2436 fman_intf->mac_type != fman_onic) { 2437 /* Configure error packet handling */ 2438 fman_if_receive_rx_errors(fman_intf, 2439 FM_FD_RX_STATUS_ERR_MASK); 2440 /* Disable RX mode */ 2441 fman_if_disable_rx(fman_intf); 2442 /* Disable promiscuous mode */ 2443 fman_if_promiscuous_disable(fman_intf); 2444 /* Disable multicast */ 2445 fman_if_reset_mcast_filter_table(fman_intf); 2446 /* Reset interface statistics */ 2447 fman_if_stats_reset(fman_intf); 2448 /* Disable SG by default */ 2449 fman_if_set_sg(fman_intf, 0); 2450 fman_if_set_maxfrm(fman_intf, 2451 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2452 } 2453 2454 return 0; 2455 2456 free_tx: 2457 rte_free(dpaa_intf->tx_queues); 2458 dpaa_intf->tx_queues = NULL; 2459 dpaa_intf->nb_tx_queues = 0; 2460 2461 free_rx: 2462 rte_free(dpaa_intf->cgr_rx); 2463 rte_free(dpaa_intf->cgr_tx); 2464 rte_free(dpaa_intf->rx_queues); 2465 dpaa_intf->rx_queues = NULL; 2466 dpaa_intf->nb_rx_queues = 0; 2467 return ret; 2468 } 2469 2470 static int 2471 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2472 struct rte_dpaa_device *dpaa_dev) 2473 { 2474 int diag; 2475 int ret; 2476 struct rte_eth_dev *eth_dev; 2477 2478 PMD_INIT_FUNC_TRACE(); 2479 2480 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2481 RTE_PKTMBUF_HEADROOM) { 2482 DPAA_PMD_ERR( 2483 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2484 RTE_PKTMBUF_HEADROOM, 2485 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2486 2487 return -1; 2488 } 2489 2490 /* In case of secondary process, the device is already configured 2491 * and no further action is required, except portal initialization 2492 * and verifying secondary attachment to port name. 2493 */ 2494 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2495 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2496 if (!eth_dev) 2497 return -ENOMEM; 2498 eth_dev->device = &dpaa_dev->device; 2499 eth_dev->dev_ops = &dpaa_devops; 2500 2501 ret = dpaa_dev_init_secondary(eth_dev); 2502 if (ret != 0) { 2503 DPAA_PMD_ERR("secondary dev init failed"); 2504 return ret; 2505 } 2506 2507 rte_eth_dev_probing_finish(eth_dev); 2508 return 0; 2509 } 2510 2511 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2512 if (access("/tmp/fmc.bin", F_OK) == -1) { 2513 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2514 default_q = 1; 2515 } 2516 2517 if (!(default_q || fmc_q)) { 2518 if (dpaa_fm_init()) { 2519 DPAA_PMD_ERR("FM init failed"); 2520 return -1; 2521 } 2522 } 2523 2524 /* disabling the default push mode for LS1043 */ 2525 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2526 dpaa_push_mode_max_queue = 0; 2527 2528 /* if push mode queues to be enabled. Currently we are allowing 2529 * only one queue per thread. 2530 */ 2531 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2532 dpaa_push_mode_max_queue = 2533 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2534 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2535 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2536 } 2537 2538 is_global_init = 1; 2539 } 2540 2541 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2542 ret = rte_dpaa_portal_init((void *)1); 2543 if (ret) { 2544 DPAA_PMD_ERR("Unable to initialize portal"); 2545 return ret; 2546 } 2547 } 2548 2549 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2550 if (!eth_dev) 2551 return -ENOMEM; 2552 2553 eth_dev->data->dev_private = 2554 rte_zmalloc("ethdev private structure", 2555 sizeof(struct dpaa_if), 2556 RTE_CACHE_LINE_SIZE); 2557 if (!eth_dev->data->dev_private) { 2558 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2559 rte_eth_dev_release_port(eth_dev); 2560 return -ENOMEM; 2561 } 2562 2563 eth_dev->device = &dpaa_dev->device; 2564 dpaa_dev->eth_dev = eth_dev; 2565 2566 qman_ern_register_cb(dpaa_free_mbuf); 2567 2568 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2569 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2570 2571 /* Invoke PMD device initialization function */ 2572 diag = dpaa_dev_init(eth_dev); 2573 if (diag == 0) { 2574 if (!dpaa_tx_sg_pool) { 2575 dpaa_tx_sg_pool = 2576 rte_pktmbuf_pool_create("dpaa_mbuf_tx_sg_pool", 2577 DPAA_POOL_SIZE, 2578 DPAA_POOL_CACHE_SIZE, 0, 2579 DPAA_MAX_SGS * sizeof(struct qm_sg_entry), 2580 rte_socket_id()); 2581 if (dpaa_tx_sg_pool == NULL) { 2582 DPAA_PMD_ERR("SG pool creation failed"); 2583 return -ENOMEM; 2584 } 2585 } 2586 rte_eth_dev_probing_finish(eth_dev); 2587 dpaa_valid_dev++; 2588 return 0; 2589 } 2590 2591 rte_eth_dev_release_port(eth_dev); 2592 return diag; 2593 } 2594 2595 static int 2596 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2597 { 2598 struct rte_eth_dev *eth_dev; 2599 int ret; 2600 2601 PMD_INIT_FUNC_TRACE(); 2602 2603 eth_dev = dpaa_dev->eth_dev; 2604 dpaa_eth_dev_close(eth_dev); 2605 dpaa_valid_dev--; 2606 if (!dpaa_valid_dev) 2607 rte_mempool_free(dpaa_tx_sg_pool); 2608 ret = rte_eth_dev_release_port(eth_dev); 2609 2610 return ret; 2611 } 2612 2613 static void __attribute__((destructor(102))) dpaa_finish(void) 2614 { 2615 /* For secondary, primary will do all the cleanup */ 2616 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2617 return; 2618 2619 if (!(default_q || fmc_q)) { 2620 if (is_global_init) 2621 if (dpaa_fm_term()) 2622 DPAA_PMD_WARN("DPAA FM term failed"); 2623 2624 is_global_init = 0; 2625 2626 DPAA_PMD_INFO("DPAA fman cleaned up"); 2627 } 2628 } 2629 2630 static struct rte_dpaa_driver rte_dpaa_pmd = { 2631 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2632 .drv_type = FSL_DPAA_ETH, 2633 .probe = rte_dpaa_probe, 2634 .remove = rte_dpaa_remove, 2635 }; 2636 2637 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2638 RTE_PMD_REGISTER_PARAM_STRING(net_dpaa, 2639 DRIVER_IEEE1588 "=<int>"); 2640 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2641