1 /* SPDX-License-Identifier: BSD-3-Clause 2 * 3 * Copyright 2016 Freescale Semiconductor, Inc. All rights reserved. 4 * Copyright 2017-2020 NXP 5 * 6 */ 7 /* System headers */ 8 #include <stdio.h> 9 #include <inttypes.h> 10 #include <unistd.h> 11 #include <limits.h> 12 #include <sched.h> 13 #include <signal.h> 14 #include <pthread.h> 15 #include <sys/types.h> 16 #include <sys/syscall.h> 17 18 #include <rte_string_fns.h> 19 #include <rte_byteorder.h> 20 #include <rte_common.h> 21 #include <rte_interrupts.h> 22 #include <rte_log.h> 23 #include <rte_debug.h> 24 #include <rte_pci.h> 25 #include <rte_atomic.h> 26 #include <rte_branch_prediction.h> 27 #include <rte_memory.h> 28 #include <rte_tailq.h> 29 #include <rte_eal.h> 30 #include <rte_alarm.h> 31 #include <rte_ether.h> 32 #include <ethdev_driver.h> 33 #include <rte_malloc.h> 34 #include <rte_ring.h> 35 36 #include <bus_dpaa_driver.h> 37 #include <rte_dpaa_logs.h> 38 #include <dpaa_mempool.h> 39 40 #include <dpaa_ethdev.h> 41 #include <dpaa_rxtx.h> 42 #include <dpaa_flow.h> 43 #include <rte_pmd_dpaa.h> 44 45 #include <fsl_usd.h> 46 #include <fsl_qman.h> 47 #include <fsl_bman.h> 48 #include <fsl_fman.h> 49 #include <process.h> 50 #include <fmlib/fm_ext.h> 51 52 #define CHECK_INTERVAL 100 /* 100ms */ 53 #define MAX_REPEAT_TIME 90 /* 9s (90 * 100ms) in total */ 54 55 /* Supported Rx offloads */ 56 static uint64_t dev_rx_offloads_sup = 57 RTE_ETH_RX_OFFLOAD_SCATTER; 58 59 /* Rx offloads which cannot be disabled */ 60 static uint64_t dev_rx_offloads_nodis = 61 RTE_ETH_RX_OFFLOAD_IPV4_CKSUM | 62 RTE_ETH_RX_OFFLOAD_UDP_CKSUM | 63 RTE_ETH_RX_OFFLOAD_TCP_CKSUM | 64 RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM | 65 RTE_ETH_RX_OFFLOAD_RSS_HASH; 66 67 /* Supported Tx offloads */ 68 static uint64_t dev_tx_offloads_sup = 69 RTE_ETH_TX_OFFLOAD_MT_LOCKFREE | 70 RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE; 71 72 /* Tx offloads which cannot be disabled */ 73 static uint64_t dev_tx_offloads_nodis = 74 RTE_ETH_TX_OFFLOAD_IPV4_CKSUM | 75 RTE_ETH_TX_OFFLOAD_UDP_CKSUM | 76 RTE_ETH_TX_OFFLOAD_TCP_CKSUM | 77 RTE_ETH_TX_OFFLOAD_SCTP_CKSUM | 78 RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM | 79 RTE_ETH_TX_OFFLOAD_MULTI_SEGS; 80 81 /* Keep track of whether QMAN and BMAN have been globally initialized */ 82 static int is_global_init; 83 static int fmc_q = 1; /* Indicates the use of static fmc for distribution */ 84 static int default_q; /* use default queue - FMC is not executed*/ 85 /* At present we only allow up to 4 push mode queues as default - as each of 86 * this queue need dedicated portal and we are short of portals. 87 */ 88 #define DPAA_MAX_PUSH_MODE_QUEUE 8 89 #define DPAA_DEFAULT_PUSH_MODE_QUEUE 4 90 91 static int dpaa_push_mode_max_queue = DPAA_DEFAULT_PUSH_MODE_QUEUE; 92 static int dpaa_push_queue_idx; /* Queue index which are in push mode*/ 93 94 95 /* Per RX FQ Taildrop in frame count */ 96 static unsigned int td_threshold = CGR_RX_PERFQ_THRESH; 97 98 /* Per TX FQ Taildrop in frame count, disabled by default */ 99 static unsigned int td_tx_threshold; 100 101 struct rte_dpaa_xstats_name_off { 102 char name[RTE_ETH_XSTATS_NAME_SIZE]; 103 uint32_t offset; 104 }; 105 106 static const struct rte_dpaa_xstats_name_off dpaa_xstats_strings[] = { 107 {"rx_align_err", 108 offsetof(struct dpaa_if_stats, raln)}, 109 {"rx_valid_pause", 110 offsetof(struct dpaa_if_stats, rxpf)}, 111 {"rx_fcs_err", 112 offsetof(struct dpaa_if_stats, rfcs)}, 113 {"rx_vlan_frame", 114 offsetof(struct dpaa_if_stats, rvlan)}, 115 {"rx_frame_err", 116 offsetof(struct dpaa_if_stats, rerr)}, 117 {"rx_drop_err", 118 offsetof(struct dpaa_if_stats, rdrp)}, 119 {"rx_undersized", 120 offsetof(struct dpaa_if_stats, rund)}, 121 {"rx_oversize_err", 122 offsetof(struct dpaa_if_stats, rovr)}, 123 {"rx_fragment_pkt", 124 offsetof(struct dpaa_if_stats, rfrg)}, 125 {"tx_valid_pause", 126 offsetof(struct dpaa_if_stats, txpf)}, 127 {"tx_fcs_err", 128 offsetof(struct dpaa_if_stats, terr)}, 129 {"tx_vlan_frame", 130 offsetof(struct dpaa_if_stats, tvlan)}, 131 {"rx_undersized", 132 offsetof(struct dpaa_if_stats, tund)}, 133 }; 134 135 static struct rte_dpaa_driver rte_dpaa_pmd; 136 int dpaa_valid_dev; 137 struct rte_mempool *dpaa_tx_sg_pool; 138 139 static int 140 dpaa_eth_dev_info(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info); 141 142 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 143 int wait_to_complete __rte_unused); 144 145 static void dpaa_interrupt_handler(void *param); 146 147 static inline void 148 dpaa_poll_queue_default_config(struct qm_mcc_initfq *opts) 149 { 150 memset(opts, 0, sizeof(struct qm_mcc_initfq)); 151 opts->we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 152 opts->fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | QM_FQCTRL_CTXASTASHING | 153 QM_FQCTRL_PREFERINCACHE; 154 opts->fqd.context_a.stashing.exclusive = 0; 155 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 156 opts->fqd.context_a.stashing.annotation_cl = 157 DPAA_IF_RX_ANNOTATION_STASH; 158 opts->fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 159 opts->fqd.context_a.stashing.context_cl = DPAA_IF_RX_CONTEXT_STASH; 160 } 161 162 static int 163 dpaa_mtu_set(struct rte_eth_dev *dev, uint16_t mtu) 164 { 165 uint32_t frame_size = mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN 166 + VLAN_TAG_SIZE; 167 uint32_t buffsz = dev->data->min_rx_buf_size - RTE_PKTMBUF_HEADROOM; 168 169 PMD_INIT_FUNC_TRACE(); 170 171 /* 172 * Refuse mtu that requires the support of scattered packets 173 * when this feature has not been enabled before. 174 */ 175 if (dev->data->min_rx_buf_size && 176 !dev->data->scattered_rx && frame_size > buffsz) { 177 DPAA_PMD_ERR("SG not enabled, will not fit in one buffer"); 178 return -EINVAL; 179 } 180 181 /* check <seg size> * <max_seg> >= max_frame */ 182 if (dev->data->min_rx_buf_size && dev->data->scattered_rx && 183 (frame_size > buffsz * DPAA_SGT_MAX_ENTRIES)) { 184 DPAA_PMD_ERR("Too big to fit for Max SG list %d", 185 buffsz * DPAA_SGT_MAX_ENTRIES); 186 return -EINVAL; 187 } 188 189 fman_if_set_maxfrm(dev->process_private, frame_size); 190 191 return 0; 192 } 193 194 static int 195 dpaa_eth_dev_configure(struct rte_eth_dev *dev) 196 { 197 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 198 uint64_t rx_offloads = eth_conf->rxmode.offloads; 199 uint64_t tx_offloads = eth_conf->txmode.offloads; 200 struct dpaa_if *dpaa_intf = dev->data->dev_private; 201 struct rte_device *rdev = dev->device; 202 struct rte_eth_link *link = &dev->data->dev_link; 203 struct rte_dpaa_device *dpaa_dev; 204 struct fman_if *fif = dev->process_private; 205 struct __fman_if *__fif; 206 struct rte_intr_handle *intr_handle; 207 uint32_t max_rx_pktlen; 208 int speed, duplex; 209 int ret, rx_status; 210 211 PMD_INIT_FUNC_TRACE(); 212 213 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 214 intr_handle = dpaa_dev->intr_handle; 215 __fif = container_of(fif, struct __fman_if, __if); 216 217 /* Check if interface is enabled in case of shared MAC */ 218 if (fif->is_shared_mac) { 219 rx_status = fman_if_get_rx_status(fif); 220 if (!rx_status) { 221 DPAA_PMD_ERR("%s Interface not enabled in kernel!", 222 dpaa_intf->name); 223 return -EHOSTDOWN; 224 } 225 } 226 227 /* Rx offloads which are enabled by default */ 228 if (dev_rx_offloads_nodis & ~rx_offloads) { 229 DPAA_PMD_INFO( 230 "Some of rx offloads enabled by default - requested 0x%" PRIx64 231 " fixed are 0x%" PRIx64, 232 rx_offloads, dev_rx_offloads_nodis); 233 } 234 235 /* Tx offloads which are enabled by default */ 236 if (dev_tx_offloads_nodis & ~tx_offloads) { 237 DPAA_PMD_INFO( 238 "Some of tx offloads enabled by default - requested 0x%" PRIx64 239 " fixed are 0x%" PRIx64, 240 tx_offloads, dev_tx_offloads_nodis); 241 } 242 243 max_rx_pktlen = eth_conf->rxmode.mtu + RTE_ETHER_HDR_LEN + 244 RTE_ETHER_CRC_LEN + VLAN_TAG_SIZE; 245 if (max_rx_pktlen > DPAA_MAX_RX_PKT_LEN) { 246 DPAA_PMD_INFO("enabling jumbo override conf max len=%d " 247 "supported is %d", 248 max_rx_pktlen, DPAA_MAX_RX_PKT_LEN); 249 max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 250 } 251 252 fman_if_set_maxfrm(dev->process_private, max_rx_pktlen); 253 254 if (rx_offloads & RTE_ETH_RX_OFFLOAD_SCATTER) { 255 DPAA_PMD_DEBUG("enabling scatter mode"); 256 fman_if_set_sg(dev->process_private, 1); 257 dev->data->scattered_rx = 1; 258 } 259 260 if (!(default_q || fmc_q)) { 261 if (dpaa_fm_config(dev, 262 eth_conf->rx_adv_conf.rss_conf.rss_hf)) { 263 dpaa_write_fm_config_to_file(); 264 DPAA_PMD_ERR("FM port configuration: Failed\n"); 265 return -1; 266 } 267 dpaa_write_fm_config_to_file(); 268 } 269 270 /* if the interrupts were configured on this devices*/ 271 if (intr_handle && rte_intr_fd_get(intr_handle)) { 272 if (dev->data->dev_conf.intr_conf.lsc != 0) 273 rte_intr_callback_register(intr_handle, 274 dpaa_interrupt_handler, 275 (void *)dev); 276 277 ret = dpaa_intr_enable(__fif->node_name, 278 rte_intr_fd_get(intr_handle)); 279 if (ret) { 280 if (dev->data->dev_conf.intr_conf.lsc != 0) { 281 rte_intr_callback_unregister(intr_handle, 282 dpaa_interrupt_handler, 283 (void *)dev); 284 if (ret == EINVAL) 285 printf("Failed to enable interrupt: Not Supported\n"); 286 else 287 printf("Failed to enable interrupt\n"); 288 } 289 dev->data->dev_conf.intr_conf.lsc = 0; 290 dev->data->dev_flags &= ~RTE_ETH_DEV_INTR_LSC; 291 } 292 } 293 294 /* Wait for link status to get updated */ 295 if (!link->link_status) 296 sleep(1); 297 298 /* Configure link only if link is UP*/ 299 if (link->link_status) { 300 if (eth_conf->link_speeds == RTE_ETH_LINK_SPEED_AUTONEG) { 301 /* Start autoneg only if link is not in autoneg mode */ 302 if (!link->link_autoneg) 303 dpaa_restart_link_autoneg(__fif->node_name); 304 } else if (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 305 switch (eth_conf->link_speeds & RTE_ETH_LINK_SPEED_FIXED) { 306 case RTE_ETH_LINK_SPEED_10M_HD: 307 speed = RTE_ETH_SPEED_NUM_10M; 308 duplex = RTE_ETH_LINK_HALF_DUPLEX; 309 break; 310 case RTE_ETH_LINK_SPEED_10M: 311 speed = RTE_ETH_SPEED_NUM_10M; 312 duplex = RTE_ETH_LINK_FULL_DUPLEX; 313 break; 314 case RTE_ETH_LINK_SPEED_100M_HD: 315 speed = RTE_ETH_SPEED_NUM_100M; 316 duplex = RTE_ETH_LINK_HALF_DUPLEX; 317 break; 318 case RTE_ETH_LINK_SPEED_100M: 319 speed = RTE_ETH_SPEED_NUM_100M; 320 duplex = RTE_ETH_LINK_FULL_DUPLEX; 321 break; 322 case RTE_ETH_LINK_SPEED_1G: 323 speed = RTE_ETH_SPEED_NUM_1G; 324 duplex = RTE_ETH_LINK_FULL_DUPLEX; 325 break; 326 case RTE_ETH_LINK_SPEED_2_5G: 327 speed = RTE_ETH_SPEED_NUM_2_5G; 328 duplex = RTE_ETH_LINK_FULL_DUPLEX; 329 break; 330 case RTE_ETH_LINK_SPEED_10G: 331 speed = RTE_ETH_SPEED_NUM_10G; 332 duplex = RTE_ETH_LINK_FULL_DUPLEX; 333 break; 334 default: 335 speed = RTE_ETH_SPEED_NUM_NONE; 336 duplex = RTE_ETH_LINK_FULL_DUPLEX; 337 break; 338 } 339 /* Set link speed */ 340 dpaa_update_link_speed(__fif->node_name, speed, duplex); 341 } else { 342 /* Manual autoneg - custom advertisement speed. */ 343 printf("Custom Advertisement speeds not supported\n"); 344 } 345 } 346 347 return 0; 348 } 349 350 static const uint32_t * 351 dpaa_supported_ptypes_get(struct rte_eth_dev *dev) 352 { 353 static const uint32_t ptypes[] = { 354 RTE_PTYPE_L2_ETHER, 355 RTE_PTYPE_L2_ETHER_VLAN, 356 RTE_PTYPE_L2_ETHER_ARP, 357 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN, 358 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN, 359 RTE_PTYPE_L4_ICMP, 360 RTE_PTYPE_L4_TCP, 361 RTE_PTYPE_L4_UDP, 362 RTE_PTYPE_L4_FRAG, 363 RTE_PTYPE_L4_TCP, 364 RTE_PTYPE_L4_UDP, 365 RTE_PTYPE_L4_SCTP, 366 RTE_PTYPE_TUNNEL_ESP 367 }; 368 369 PMD_INIT_FUNC_TRACE(); 370 371 if (dev->rx_pkt_burst == dpaa_eth_queue_rx) 372 return ptypes; 373 return NULL; 374 } 375 376 static void dpaa_interrupt_handler(void *param) 377 { 378 struct rte_eth_dev *dev = param; 379 struct rte_device *rdev = dev->device; 380 struct rte_dpaa_device *dpaa_dev; 381 struct rte_intr_handle *intr_handle; 382 uint64_t buf; 383 int bytes_read; 384 385 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 386 intr_handle = dpaa_dev->intr_handle; 387 388 if (rte_intr_fd_get(intr_handle) < 0) 389 return; 390 391 bytes_read = read(rte_intr_fd_get(intr_handle), &buf, 392 sizeof(uint64_t)); 393 if (bytes_read < 0) 394 DPAA_PMD_ERR("Error reading eventfd\n"); 395 dpaa_eth_link_update(dev, 0); 396 rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC, NULL); 397 } 398 399 static int dpaa_eth_dev_start(struct rte_eth_dev *dev) 400 { 401 struct dpaa_if *dpaa_intf = dev->data->dev_private; 402 uint16_t i; 403 404 PMD_INIT_FUNC_TRACE(); 405 406 if (!(default_q || fmc_q)) 407 dpaa_write_fm_config_to_file(); 408 409 /* Change tx callback to the real one */ 410 if (dpaa_intf->cgr_tx) 411 dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 412 else 413 dev->tx_pkt_burst = dpaa_eth_queue_tx; 414 415 fman_if_enable_rx(dev->process_private); 416 417 for (i = 0; i < dev->data->nb_rx_queues; i++) 418 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 419 for (i = 0; i < dev->data->nb_tx_queues; i++) 420 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STARTED; 421 422 return 0; 423 } 424 425 static int dpaa_eth_dev_stop(struct rte_eth_dev *dev) 426 { 427 struct fman_if *fif = dev->process_private; 428 uint16_t i; 429 430 PMD_INIT_FUNC_TRACE(); 431 dev->data->dev_started = 0; 432 433 if (!fif->is_shared_mac) 434 fman_if_disable_rx(fif); 435 dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 436 437 for (i = 0; i < dev->data->nb_rx_queues; i++) 438 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 439 for (i = 0; i < dev->data->nb_tx_queues; i++) 440 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED; 441 442 return 0; 443 } 444 445 static int dpaa_eth_dev_close(struct rte_eth_dev *dev) 446 { 447 struct fman_if *fif = dev->process_private; 448 struct __fman_if *__fif; 449 struct rte_device *rdev = dev->device; 450 struct rte_dpaa_device *dpaa_dev; 451 struct rte_intr_handle *intr_handle; 452 struct rte_eth_link *link = &dev->data->dev_link; 453 struct dpaa_if *dpaa_intf = dev->data->dev_private; 454 int loop; 455 int ret; 456 457 PMD_INIT_FUNC_TRACE(); 458 459 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 460 return 0; 461 462 if (!dpaa_intf) { 463 DPAA_PMD_WARN("Already closed or not started"); 464 return -1; 465 } 466 467 /* DPAA FM deconfig */ 468 if (!(default_q || fmc_q)) { 469 if (dpaa_fm_deconfig(dpaa_intf, dev->process_private)) 470 DPAA_PMD_WARN("DPAA FM deconfig failed\n"); 471 } 472 473 dpaa_dev = container_of(rdev, struct rte_dpaa_device, device); 474 intr_handle = dpaa_dev->intr_handle; 475 __fif = container_of(fif, struct __fman_if, __if); 476 477 ret = dpaa_eth_dev_stop(dev); 478 479 /* Reset link to autoneg */ 480 if (link->link_status && !link->link_autoneg) 481 dpaa_restart_link_autoneg(__fif->node_name); 482 483 if (intr_handle && rte_intr_fd_get(intr_handle) && 484 dev->data->dev_conf.intr_conf.lsc != 0) { 485 dpaa_intr_disable(__fif->node_name); 486 rte_intr_callback_unregister(intr_handle, 487 dpaa_interrupt_handler, 488 (void *)dev); 489 } 490 491 /* release configuration memory */ 492 rte_free(dpaa_intf->fc_conf); 493 494 /* Release RX congestion Groups */ 495 if (dpaa_intf->cgr_rx) { 496 for (loop = 0; loop < dpaa_intf->nb_rx_queues; loop++) 497 qman_delete_cgr(&dpaa_intf->cgr_rx[loop]); 498 } 499 500 rte_free(dpaa_intf->cgr_rx); 501 dpaa_intf->cgr_rx = NULL; 502 /* Release TX congestion Groups */ 503 if (dpaa_intf->cgr_tx) { 504 for (loop = 0; loop < MAX_DPAA_CORES; loop++) 505 qman_delete_cgr(&dpaa_intf->cgr_tx[loop]); 506 rte_free(dpaa_intf->cgr_tx); 507 dpaa_intf->cgr_tx = NULL; 508 } 509 510 rte_free(dpaa_intf->rx_queues); 511 dpaa_intf->rx_queues = NULL; 512 513 rte_free(dpaa_intf->tx_queues); 514 dpaa_intf->tx_queues = NULL; 515 516 return ret; 517 } 518 519 static int 520 dpaa_fw_version_get(struct rte_eth_dev *dev __rte_unused, 521 char *fw_version, 522 size_t fw_size) 523 { 524 int ret; 525 FILE *svr_file = NULL; 526 unsigned int svr_ver = 0; 527 528 PMD_INIT_FUNC_TRACE(); 529 530 svr_file = fopen(DPAA_SOC_ID_FILE, "r"); 531 if (!svr_file) { 532 DPAA_PMD_ERR("Unable to open SoC device"); 533 return -ENOTSUP; /* Not supported on this infra */ 534 } 535 if (fscanf(svr_file, "svr:%x", &svr_ver) > 0) 536 dpaa_svr_family = svr_ver & SVR_MASK; 537 else 538 DPAA_PMD_ERR("Unable to read SoC device"); 539 540 fclose(svr_file); 541 542 ret = snprintf(fw_version, fw_size, "SVR:%x-fman-v%x", 543 svr_ver, fman_ip_rev); 544 if (ret < 0) 545 return -EINVAL; 546 547 ret += 1; /* add the size of '\0' */ 548 if (fw_size < (size_t)ret) 549 return ret; 550 else 551 return 0; 552 } 553 554 static int dpaa_eth_dev_info(struct rte_eth_dev *dev, 555 struct rte_eth_dev_info *dev_info) 556 { 557 struct dpaa_if *dpaa_intf = dev->data->dev_private; 558 struct fman_if *fif = dev->process_private; 559 560 DPAA_PMD_DEBUG(": %s", dpaa_intf->name); 561 562 dev_info->max_rx_queues = dpaa_intf->nb_rx_queues; 563 dev_info->max_tx_queues = dpaa_intf->nb_tx_queues; 564 dev_info->max_rx_pktlen = DPAA_MAX_RX_PKT_LEN; 565 dev_info->max_mac_addrs = DPAA_MAX_MAC_FILTER; 566 dev_info->max_hash_mac_addrs = 0; 567 dev_info->max_vfs = 0; 568 dev_info->max_vmdq_pools = RTE_ETH_16_POOLS; 569 dev_info->flow_type_rss_offloads = DPAA_RSS_OFFLOAD_ALL; 570 571 if (fif->mac_type == fman_mac_1g) { 572 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 573 | RTE_ETH_LINK_SPEED_10M 574 | RTE_ETH_LINK_SPEED_100M_HD 575 | RTE_ETH_LINK_SPEED_100M 576 | RTE_ETH_LINK_SPEED_1G; 577 } else if (fif->mac_type == fman_mac_2_5g) { 578 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 579 | RTE_ETH_LINK_SPEED_10M 580 | RTE_ETH_LINK_SPEED_100M_HD 581 | RTE_ETH_LINK_SPEED_100M 582 | RTE_ETH_LINK_SPEED_1G 583 | RTE_ETH_LINK_SPEED_2_5G; 584 } else if (fif->mac_type == fman_mac_10g) { 585 dev_info->speed_capa = RTE_ETH_LINK_SPEED_10M_HD 586 | RTE_ETH_LINK_SPEED_10M 587 | RTE_ETH_LINK_SPEED_100M_HD 588 | RTE_ETH_LINK_SPEED_100M 589 | RTE_ETH_LINK_SPEED_1G 590 | RTE_ETH_LINK_SPEED_2_5G 591 | RTE_ETH_LINK_SPEED_10G; 592 } else { 593 DPAA_PMD_ERR("invalid link_speed: %s, %d", 594 dpaa_intf->name, fif->mac_type); 595 return -EINVAL; 596 } 597 598 dev_info->rx_offload_capa = dev_rx_offloads_sup | 599 dev_rx_offloads_nodis; 600 dev_info->tx_offload_capa = dev_tx_offloads_sup | 601 dev_tx_offloads_nodis; 602 dev_info->default_rxportconf.burst_size = DPAA_DEF_RX_BURST_SIZE; 603 dev_info->default_txportconf.burst_size = DPAA_DEF_TX_BURST_SIZE; 604 dev_info->default_rxportconf.nb_queues = 1; 605 dev_info->default_txportconf.nb_queues = 1; 606 dev_info->default_txportconf.ring_size = CGR_TX_CGR_THRESH; 607 dev_info->default_rxportconf.ring_size = CGR_RX_PERFQ_THRESH; 608 609 return 0; 610 } 611 612 static int 613 dpaa_dev_rx_burst_mode_get(struct rte_eth_dev *dev, 614 __rte_unused uint16_t queue_id, 615 struct rte_eth_burst_mode *mode) 616 { 617 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 618 int ret = -EINVAL; 619 unsigned int i; 620 const struct burst_info { 621 uint64_t flags; 622 const char *output; 623 } rx_offload_map[] = { 624 {RTE_ETH_RX_OFFLOAD_SCATTER, " Scattered,"}, 625 {RTE_ETH_RX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 626 {RTE_ETH_RX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 627 {RTE_ETH_RX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 628 {RTE_ETH_RX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 629 {RTE_ETH_RX_OFFLOAD_RSS_HASH, " RSS,"} 630 }; 631 632 /* Update Rx offload info */ 633 for (i = 0; i < RTE_DIM(rx_offload_map); i++) { 634 if (eth_conf->rxmode.offloads & rx_offload_map[i].flags) { 635 snprintf(mode->info, sizeof(mode->info), "%s", 636 rx_offload_map[i].output); 637 ret = 0; 638 break; 639 } 640 } 641 return ret; 642 } 643 644 static int 645 dpaa_dev_tx_burst_mode_get(struct rte_eth_dev *dev, 646 __rte_unused uint16_t queue_id, 647 struct rte_eth_burst_mode *mode) 648 { 649 struct rte_eth_conf *eth_conf = &dev->data->dev_conf; 650 int ret = -EINVAL; 651 unsigned int i; 652 const struct burst_info { 653 uint64_t flags; 654 const char *output; 655 } tx_offload_map[] = { 656 {RTE_ETH_TX_OFFLOAD_MT_LOCKFREE, " MT lockfree,"}, 657 {RTE_ETH_TX_OFFLOAD_MBUF_FAST_FREE, " MBUF free disable,"}, 658 {RTE_ETH_TX_OFFLOAD_IPV4_CKSUM, " IPV4 csum,"}, 659 {RTE_ETH_TX_OFFLOAD_UDP_CKSUM, " UDP csum,"}, 660 {RTE_ETH_TX_OFFLOAD_TCP_CKSUM, " TCP csum,"}, 661 {RTE_ETH_TX_OFFLOAD_SCTP_CKSUM, " SCTP csum,"}, 662 {RTE_ETH_TX_OFFLOAD_OUTER_IPV4_CKSUM, " Outer IPV4 csum,"}, 663 {RTE_ETH_TX_OFFLOAD_MULTI_SEGS, " Scattered,"} 664 }; 665 666 /* Update Tx offload info */ 667 for (i = 0; i < RTE_DIM(tx_offload_map); i++) { 668 if (eth_conf->txmode.offloads & tx_offload_map[i].flags) { 669 snprintf(mode->info, sizeof(mode->info), "%s", 670 tx_offload_map[i].output); 671 ret = 0; 672 break; 673 } 674 } 675 return ret; 676 } 677 678 static int dpaa_eth_link_update(struct rte_eth_dev *dev, 679 int wait_to_complete) 680 { 681 struct dpaa_if *dpaa_intf = dev->data->dev_private; 682 struct rte_eth_link *link = &dev->data->dev_link; 683 struct fman_if *fif = dev->process_private; 684 struct __fman_if *__fif = container_of(fif, struct __fman_if, __if); 685 int ret, ioctl_version; 686 uint8_t count; 687 688 PMD_INIT_FUNC_TRACE(); 689 690 ioctl_version = dpaa_get_ioctl_version_number(); 691 692 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) { 693 for (count = 0; count <= MAX_REPEAT_TIME; count++) { 694 ret = dpaa_get_link_status(__fif->node_name, link); 695 if (ret) 696 return ret; 697 if (link->link_status == RTE_ETH_LINK_DOWN && 698 wait_to_complete) 699 rte_delay_ms(CHECK_INTERVAL); 700 else 701 break; 702 } 703 } else { 704 link->link_status = dpaa_intf->valid; 705 } 706 707 if (ioctl_version < 2) { 708 link->link_duplex = RTE_ETH_LINK_FULL_DUPLEX; 709 link->link_autoneg = RTE_ETH_LINK_AUTONEG; 710 711 if (fif->mac_type == fman_mac_1g) 712 link->link_speed = RTE_ETH_SPEED_NUM_1G; 713 else if (fif->mac_type == fman_mac_2_5g) 714 link->link_speed = RTE_ETH_SPEED_NUM_2_5G; 715 else if (fif->mac_type == fman_mac_10g) 716 link->link_speed = RTE_ETH_SPEED_NUM_10G; 717 else 718 DPAA_PMD_ERR("invalid link_speed: %s, %d", 719 dpaa_intf->name, fif->mac_type); 720 } 721 722 DPAA_PMD_INFO("Port %d Link is %s\n", dev->data->port_id, 723 link->link_status ? "Up" : "Down"); 724 return 0; 725 } 726 727 static int dpaa_eth_stats_get(struct rte_eth_dev *dev, 728 struct rte_eth_stats *stats) 729 { 730 PMD_INIT_FUNC_TRACE(); 731 732 fman_if_stats_get(dev->process_private, stats); 733 return 0; 734 } 735 736 static int dpaa_eth_stats_reset(struct rte_eth_dev *dev) 737 { 738 PMD_INIT_FUNC_TRACE(); 739 740 fman_if_stats_reset(dev->process_private); 741 742 return 0; 743 } 744 745 static int 746 dpaa_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats, 747 unsigned int n) 748 { 749 unsigned int i = 0, num = RTE_DIM(dpaa_xstats_strings); 750 uint64_t values[sizeof(struct dpaa_if_stats) / 8]; 751 752 if (n < num) 753 return num; 754 755 if (xstats == NULL) 756 return 0; 757 758 fman_if_stats_get_all(dev->process_private, values, 759 sizeof(struct dpaa_if_stats) / 8); 760 761 for (i = 0; i < num; i++) { 762 xstats[i].id = i; 763 xstats[i].value = values[dpaa_xstats_strings[i].offset / 8]; 764 } 765 return i; 766 } 767 768 static int 769 dpaa_xstats_get_names(__rte_unused struct rte_eth_dev *dev, 770 struct rte_eth_xstat_name *xstats_names, 771 unsigned int limit) 772 { 773 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 774 775 if (limit < stat_cnt) 776 return stat_cnt; 777 778 if (xstats_names != NULL) 779 for (i = 0; i < stat_cnt; i++) 780 strlcpy(xstats_names[i].name, 781 dpaa_xstats_strings[i].name, 782 sizeof(xstats_names[i].name)); 783 784 return stat_cnt; 785 } 786 787 static int 788 dpaa_xstats_get_by_id(struct rte_eth_dev *dev, const uint64_t *ids, 789 uint64_t *values, unsigned int n) 790 { 791 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 792 uint64_t values_copy[sizeof(struct dpaa_if_stats) / 8]; 793 794 if (!ids) { 795 if (n < stat_cnt) 796 return stat_cnt; 797 798 if (!values) 799 return 0; 800 801 fman_if_stats_get_all(dev->process_private, values_copy, 802 sizeof(struct dpaa_if_stats) / 8); 803 804 for (i = 0; i < stat_cnt; i++) 805 values[i] = 806 values_copy[dpaa_xstats_strings[i].offset / 8]; 807 808 return stat_cnt; 809 } 810 811 dpaa_xstats_get_by_id(dev, NULL, values_copy, stat_cnt); 812 813 for (i = 0; i < n; i++) { 814 if (ids[i] >= stat_cnt) { 815 DPAA_PMD_ERR("id value isn't valid"); 816 return -1; 817 } 818 values[i] = values_copy[ids[i]]; 819 } 820 return n; 821 } 822 823 static int 824 dpaa_xstats_get_names_by_id( 825 struct rte_eth_dev *dev, 826 const uint64_t *ids, 827 struct rte_eth_xstat_name *xstats_names, 828 unsigned int limit) 829 { 830 unsigned int i, stat_cnt = RTE_DIM(dpaa_xstats_strings); 831 struct rte_eth_xstat_name xstats_names_copy[stat_cnt]; 832 833 if (!ids) 834 return dpaa_xstats_get_names(dev, xstats_names, limit); 835 836 dpaa_xstats_get_names(dev, xstats_names_copy, limit); 837 838 for (i = 0; i < limit; i++) { 839 if (ids[i] >= stat_cnt) { 840 DPAA_PMD_ERR("id value isn't valid"); 841 return -1; 842 } 843 strcpy(xstats_names[i].name, xstats_names_copy[ids[i]].name); 844 } 845 return limit; 846 } 847 848 static int dpaa_eth_promiscuous_enable(struct rte_eth_dev *dev) 849 { 850 PMD_INIT_FUNC_TRACE(); 851 852 fman_if_promiscuous_enable(dev->process_private); 853 854 return 0; 855 } 856 857 static int dpaa_eth_promiscuous_disable(struct rte_eth_dev *dev) 858 { 859 PMD_INIT_FUNC_TRACE(); 860 861 fman_if_promiscuous_disable(dev->process_private); 862 863 return 0; 864 } 865 866 static int dpaa_eth_multicast_enable(struct rte_eth_dev *dev) 867 { 868 PMD_INIT_FUNC_TRACE(); 869 870 fman_if_set_mcast_filter_table(dev->process_private); 871 872 return 0; 873 } 874 875 static int dpaa_eth_multicast_disable(struct rte_eth_dev *dev) 876 { 877 PMD_INIT_FUNC_TRACE(); 878 879 fman_if_reset_mcast_filter_table(dev->process_private); 880 881 return 0; 882 } 883 884 static void dpaa_fman_if_pool_setup(struct rte_eth_dev *dev) 885 { 886 struct dpaa_if *dpaa_intf = dev->data->dev_private; 887 struct fman_if_ic_params icp; 888 uint32_t fd_offset; 889 uint32_t bp_size; 890 891 memset(&icp, 0, sizeof(icp)); 892 /* set ICEOF for to the default value , which is 0*/ 893 icp.iciof = DEFAULT_ICIOF; 894 icp.iceof = DEFAULT_RX_ICEOF; 895 icp.icsz = DEFAULT_ICSZ; 896 fman_if_set_ic_params(dev->process_private, &icp); 897 898 fd_offset = RTE_PKTMBUF_HEADROOM + DPAA_HW_BUF_RESERVE; 899 fman_if_set_fdoff(dev->process_private, fd_offset); 900 901 /* Buffer pool size should be equal to Dataroom Size*/ 902 bp_size = rte_pktmbuf_data_room_size(dpaa_intf->bp_info->mp); 903 904 fman_if_set_bp(dev->process_private, 905 dpaa_intf->bp_info->mp->size, 906 dpaa_intf->bp_info->bpid, bp_size); 907 } 908 909 static inline int dpaa_eth_rx_queue_bp_check(struct rte_eth_dev *dev, 910 int8_t vsp_id, uint32_t bpid) 911 { 912 struct dpaa_if *dpaa_intf = dev->data->dev_private; 913 struct fman_if *fif = dev->process_private; 914 915 if (fif->num_profiles) { 916 if (vsp_id < 0) 917 vsp_id = fif->base_profile_id; 918 } else { 919 if (vsp_id < 0) 920 vsp_id = 0; 921 } 922 923 if (dpaa_intf->vsp_bpid[vsp_id] && 924 bpid != dpaa_intf->vsp_bpid[vsp_id]) { 925 DPAA_PMD_ERR("Various MPs are assigned to RXQs with same VSP"); 926 927 return -1; 928 } 929 930 return 0; 931 } 932 933 static 934 int dpaa_eth_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 935 uint16_t nb_desc, 936 unsigned int socket_id __rte_unused, 937 const struct rte_eth_rxconf *rx_conf, 938 struct rte_mempool *mp) 939 { 940 struct dpaa_if *dpaa_intf = dev->data->dev_private; 941 struct fman_if *fif = dev->process_private; 942 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_idx]; 943 struct qm_mcc_initfq opts = {0}; 944 u32 flags = 0; 945 int ret; 946 u32 buffsz = rte_pktmbuf_data_room_size(mp) - RTE_PKTMBUF_HEADROOM; 947 uint32_t max_rx_pktlen; 948 949 PMD_INIT_FUNC_TRACE(); 950 951 if (queue_idx >= dev->data->nb_rx_queues) { 952 rte_errno = EOVERFLOW; 953 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 954 (void *)dev, queue_idx, dev->data->nb_rx_queues); 955 return -rte_errno; 956 } 957 958 /* Rx deferred start is not supported */ 959 if (rx_conf->rx_deferred_start) { 960 DPAA_PMD_ERR("%p:Rx deferred start not supported", (void *)dev); 961 return -EINVAL; 962 } 963 rxq->nb_desc = UINT16_MAX; 964 rxq->offloads = rx_conf->offloads; 965 966 DPAA_PMD_INFO("Rx queue setup for queue index: %d fq_id (0x%x)", 967 queue_idx, rxq->fqid); 968 969 if (!fif->num_profiles) { 970 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 971 dpaa_intf->bp_info->mp != mp) { 972 DPAA_PMD_WARN("Multiple pools on same interface not" 973 " supported"); 974 return -EINVAL; 975 } 976 } else { 977 if (dpaa_eth_rx_queue_bp_check(dev, rxq->vsp_id, 978 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid)) { 979 return -EINVAL; 980 } 981 } 982 983 if (dpaa_intf->bp_info && dpaa_intf->bp_info->bp && 984 dpaa_intf->bp_info->mp != mp) { 985 DPAA_PMD_WARN("Multiple pools on same interface not supported"); 986 return -EINVAL; 987 } 988 989 max_rx_pktlen = dev->data->mtu + RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + 990 VLAN_TAG_SIZE; 991 /* Max packet can fit in single buffer */ 992 if (max_rx_pktlen <= buffsz) { 993 ; 994 } else if (dev->data->dev_conf.rxmode.offloads & 995 RTE_ETH_RX_OFFLOAD_SCATTER) { 996 if (max_rx_pktlen > buffsz * DPAA_SGT_MAX_ENTRIES) { 997 DPAA_PMD_ERR("Maximum Rx packet size %d too big to fit " 998 "MaxSGlist %d", 999 max_rx_pktlen, buffsz * DPAA_SGT_MAX_ENTRIES); 1000 rte_errno = EOVERFLOW; 1001 return -rte_errno; 1002 } 1003 } else { 1004 DPAA_PMD_WARN("The requested maximum Rx packet size (%u) is" 1005 " larger than a single mbuf (%u) and scattered" 1006 " mode has not been requested", max_rx_pktlen, buffsz); 1007 } 1008 1009 dpaa_intf->bp_info = DPAA_MEMPOOL_TO_POOL_INFO(mp); 1010 1011 /* For shared interface, it's done in kernel, skip.*/ 1012 if (!fif->is_shared_mac) 1013 dpaa_fman_if_pool_setup(dev); 1014 1015 if (fif->num_profiles) { 1016 int8_t vsp_id = rxq->vsp_id; 1017 1018 if (vsp_id >= 0) { 1019 ret = dpaa_port_vsp_update(dpaa_intf, fmc_q, vsp_id, 1020 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid, 1021 fif, buffsz + RTE_PKTMBUF_HEADROOM); 1022 if (ret) { 1023 DPAA_PMD_ERR("dpaa_port_vsp_update failed"); 1024 return ret; 1025 } 1026 } else { 1027 DPAA_PMD_INFO("Base profile is associated to" 1028 " RXQ fqid:%d\r\n", rxq->fqid); 1029 if (fif->is_shared_mac) { 1030 DPAA_PMD_ERR("Fatal: Base profile is associated" 1031 " to shared interface on DPDK."); 1032 return -EINVAL; 1033 } 1034 dpaa_intf->vsp_bpid[fif->base_profile_id] = 1035 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1036 } 1037 } else { 1038 dpaa_intf->vsp_bpid[0] = 1039 DPAA_MEMPOOL_TO_POOL_INFO(mp)->bpid; 1040 } 1041 1042 dpaa_intf->valid = 1; 1043 DPAA_PMD_DEBUG("if:%s sg_on = %d, max_frm =%d", dpaa_intf->name, 1044 fman_if_get_sg_enable(fif), max_rx_pktlen); 1045 /* checking if push mode only, no error check for now */ 1046 if (!rxq->is_static && 1047 dpaa_push_mode_max_queue > dpaa_push_queue_idx) { 1048 struct qman_portal *qp; 1049 int q_fd; 1050 1051 dpaa_push_queue_idx++; 1052 opts.we_mask = QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA; 1053 opts.fqd.fq_ctrl = QM_FQCTRL_AVOIDBLOCK | 1054 QM_FQCTRL_CTXASTASHING | 1055 QM_FQCTRL_PREFERINCACHE; 1056 opts.fqd.context_a.stashing.exclusive = 0; 1057 /* In multicore scenario stashing becomes a bottleneck on LS1046. 1058 * So do not enable stashing in this case 1059 */ 1060 if (dpaa_svr_family != SVR_LS1046A_FAMILY) 1061 opts.fqd.context_a.stashing.annotation_cl = 1062 DPAA_IF_RX_ANNOTATION_STASH; 1063 opts.fqd.context_a.stashing.data_cl = DPAA_IF_RX_DATA_STASH; 1064 opts.fqd.context_a.stashing.context_cl = 1065 DPAA_IF_RX_CONTEXT_STASH; 1066 1067 /*Create a channel and associate given queue with the channel*/ 1068 qman_alloc_pool_range((u32 *)&rxq->ch_id, 1, 1, 0); 1069 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1070 opts.fqd.dest.channel = rxq->ch_id; 1071 opts.fqd.dest.wq = DPAA_IF_RX_PRIORITY; 1072 flags = QMAN_INITFQ_FLAG_SCHED; 1073 1074 /* Configure tail drop */ 1075 if (dpaa_intf->cgr_rx) { 1076 opts.we_mask |= QM_INITFQ_WE_CGID; 1077 opts.fqd.cgid = dpaa_intf->cgr_rx[queue_idx].cgrid; 1078 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1079 } 1080 ret = qman_init_fq(rxq, flags, &opts); 1081 if (ret) { 1082 DPAA_PMD_ERR("Channel/Q association failed. fqid 0x%x " 1083 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1084 return ret; 1085 } 1086 if (dpaa_svr_family == SVR_LS1043A_FAMILY) { 1087 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb_no_prefetch; 1088 } else { 1089 rxq->cb.dqrr_dpdk_pull_cb = dpaa_rx_cb; 1090 rxq->cb.dqrr_prepare = dpaa_rx_cb_prepare; 1091 } 1092 1093 rxq->is_static = true; 1094 1095 /* Allocate qman specific portals */ 1096 qp = fsl_qman_fq_portal_create(&q_fd); 1097 if (!qp) { 1098 DPAA_PMD_ERR("Unable to alloc fq portal"); 1099 return -1; 1100 } 1101 rxq->qp = qp; 1102 1103 /* Set up the device interrupt handler */ 1104 if (dev->intr_handle == NULL) { 1105 struct rte_dpaa_device *dpaa_dev; 1106 struct rte_device *rdev = dev->device; 1107 1108 dpaa_dev = container_of(rdev, struct rte_dpaa_device, 1109 device); 1110 dev->intr_handle = dpaa_dev->intr_handle; 1111 if (rte_intr_vec_list_alloc(dev->intr_handle, 1112 NULL, dpaa_push_mode_max_queue)) { 1113 DPAA_PMD_ERR("intr_vec alloc failed"); 1114 return -ENOMEM; 1115 } 1116 if (rte_intr_nb_efd_set(dev->intr_handle, 1117 dpaa_push_mode_max_queue)) 1118 return -rte_errno; 1119 1120 if (rte_intr_max_intr_set(dev->intr_handle, 1121 dpaa_push_mode_max_queue)) 1122 return -rte_errno; 1123 } 1124 1125 if (rte_intr_type_set(dev->intr_handle, RTE_INTR_HANDLE_EXT)) 1126 return -rte_errno; 1127 1128 if (rte_intr_vec_list_index_set(dev->intr_handle, 1129 queue_idx, queue_idx + 1)) 1130 return -rte_errno; 1131 1132 if (rte_intr_efds_index_set(dev->intr_handle, queue_idx, 1133 q_fd)) 1134 return -rte_errno; 1135 1136 rxq->q_fd = q_fd; 1137 } 1138 rxq->bp_array = rte_dpaa_bpid_info; 1139 dev->data->rx_queues[queue_idx] = rxq; 1140 1141 /* configure the CGR size as per the desc size */ 1142 if (dpaa_intf->cgr_rx) { 1143 struct qm_mcc_initcgr cgr_opts = {0}; 1144 1145 rxq->nb_desc = nb_desc; 1146 /* Enable tail drop with cgr on this queue */ 1147 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, nb_desc, 0); 1148 ret = qman_modify_cgr(dpaa_intf->cgr_rx, 0, &cgr_opts); 1149 if (ret) { 1150 DPAA_PMD_WARN( 1151 "rx taildrop modify fail on fqid %d (ret=%d)", 1152 rxq->fqid, ret); 1153 } 1154 } 1155 /* Enable main queue to receive error packets also by default */ 1156 fman_if_set_err_fqid(fif, rxq->fqid); 1157 return 0; 1158 } 1159 1160 int 1161 dpaa_eth_eventq_attach(const struct rte_eth_dev *dev, 1162 int eth_rx_queue_id, 1163 u16 ch_id, 1164 const struct rte_event_eth_rx_adapter_queue_conf *queue_conf) 1165 { 1166 int ret; 1167 u32 flags = 0; 1168 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1169 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1170 struct qm_mcc_initfq opts = {0}; 1171 1172 if (dpaa_push_mode_max_queue) 1173 DPAA_PMD_WARN("PUSH mode q and EVENTDEV are not compatible\n" 1174 "PUSH mode already enabled for first %d queues.\n" 1175 "To disable set DPAA_PUSH_QUEUES_NUMBER to 0\n", 1176 dpaa_push_mode_max_queue); 1177 1178 dpaa_poll_queue_default_config(&opts); 1179 1180 switch (queue_conf->ev.sched_type) { 1181 case RTE_SCHED_TYPE_ATOMIC: 1182 opts.fqd.fq_ctrl |= QM_FQCTRL_HOLDACTIVE; 1183 /* Reset FQCTRL_AVOIDBLOCK bit as it is unnecessary 1184 * configuration with HOLD_ACTIVE setting 1185 */ 1186 opts.fqd.fq_ctrl &= (~QM_FQCTRL_AVOIDBLOCK); 1187 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_atomic; 1188 break; 1189 case RTE_SCHED_TYPE_ORDERED: 1190 DPAA_PMD_ERR("Ordered queue schedule type is not supported\n"); 1191 return -1; 1192 default: 1193 opts.fqd.fq_ctrl |= QM_FQCTRL_AVOIDBLOCK; 1194 rxq->cb.dqrr_dpdk_cb = dpaa_rx_cb_parallel; 1195 break; 1196 } 1197 1198 opts.we_mask = opts.we_mask | QM_INITFQ_WE_DESTWQ; 1199 opts.fqd.dest.channel = ch_id; 1200 opts.fqd.dest.wq = queue_conf->ev.priority; 1201 1202 if (dpaa_intf->cgr_rx) { 1203 opts.we_mask |= QM_INITFQ_WE_CGID; 1204 opts.fqd.cgid = dpaa_intf->cgr_rx[eth_rx_queue_id].cgrid; 1205 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1206 } 1207 1208 flags = QMAN_INITFQ_FLAG_SCHED; 1209 1210 ret = qman_init_fq(rxq, flags, &opts); 1211 if (ret) { 1212 DPAA_PMD_ERR("Ev-Channel/Q association failed. fqid 0x%x " 1213 "ret:%d(%s)", rxq->fqid, ret, strerror(ret)); 1214 return ret; 1215 } 1216 1217 /* copy configuration which needs to be filled during dequeue */ 1218 memcpy(&rxq->ev, &queue_conf->ev, sizeof(struct rte_event)); 1219 dev->data->rx_queues[eth_rx_queue_id] = rxq; 1220 1221 return ret; 1222 } 1223 1224 int 1225 dpaa_eth_eventq_detach(const struct rte_eth_dev *dev, 1226 int eth_rx_queue_id) 1227 { 1228 struct qm_mcc_initfq opts = {0}; 1229 int ret; 1230 u32 flags = 0; 1231 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1232 struct qman_fq *rxq = &dpaa_intf->rx_queues[eth_rx_queue_id]; 1233 1234 qman_retire_fq(rxq, NULL); 1235 qman_oos_fq(rxq); 1236 ret = qman_init_fq(rxq, flags, &opts); 1237 if (ret) { 1238 DPAA_PMD_ERR("detach rx fqid %d failed with ret: %d", 1239 rxq->fqid, ret); 1240 } 1241 1242 rxq->cb.dqrr_dpdk_cb = NULL; 1243 dev->data->rx_queues[eth_rx_queue_id] = NULL; 1244 1245 return 0; 1246 } 1247 1248 static 1249 int dpaa_eth_tx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx, 1250 uint16_t nb_desc __rte_unused, 1251 unsigned int socket_id __rte_unused, 1252 const struct rte_eth_txconf *tx_conf) 1253 { 1254 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1255 struct qman_fq *txq = &dpaa_intf->tx_queues[queue_idx]; 1256 1257 PMD_INIT_FUNC_TRACE(); 1258 1259 /* Tx deferred start is not supported */ 1260 if (tx_conf->tx_deferred_start) { 1261 DPAA_PMD_ERR("%p:Tx deferred start not supported", (void *)dev); 1262 return -EINVAL; 1263 } 1264 txq->nb_desc = UINT16_MAX; 1265 txq->offloads = tx_conf->offloads; 1266 1267 if (queue_idx >= dev->data->nb_tx_queues) { 1268 rte_errno = EOVERFLOW; 1269 DPAA_PMD_ERR("%p: queue index out of range (%u >= %u)", 1270 (void *)dev, queue_idx, dev->data->nb_tx_queues); 1271 return -rte_errno; 1272 } 1273 1274 DPAA_PMD_INFO("Tx queue setup for queue index: %d fq_id (0x%x)", 1275 queue_idx, txq->fqid); 1276 dev->data->tx_queues[queue_idx] = txq; 1277 1278 return 0; 1279 } 1280 1281 static uint32_t 1282 dpaa_dev_rx_queue_count(void *rx_queue) 1283 { 1284 struct qman_fq *rxq = rx_queue; 1285 u32 frm_cnt = 0; 1286 1287 PMD_INIT_FUNC_TRACE(); 1288 1289 if (qman_query_fq_frm_cnt(rxq, &frm_cnt) == 0) { 1290 DPAA_PMD_DEBUG("RX frame count for q(%p) is %u", 1291 rx_queue, frm_cnt); 1292 } 1293 return frm_cnt; 1294 } 1295 1296 static int dpaa_link_down(struct rte_eth_dev *dev) 1297 { 1298 struct fman_if *fif = dev->process_private; 1299 struct __fman_if *__fif; 1300 1301 PMD_INIT_FUNC_TRACE(); 1302 1303 __fif = container_of(fif, struct __fman_if, __if); 1304 1305 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1306 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_DOWN); 1307 else 1308 return dpaa_eth_dev_stop(dev); 1309 return 0; 1310 } 1311 1312 static int dpaa_link_up(struct rte_eth_dev *dev) 1313 { 1314 struct fman_if *fif = dev->process_private; 1315 struct __fman_if *__fif; 1316 1317 PMD_INIT_FUNC_TRACE(); 1318 1319 __fif = container_of(fif, struct __fman_if, __if); 1320 1321 if (dev->data->dev_flags & RTE_ETH_DEV_INTR_LSC) 1322 dpaa_update_link_status(__fif->node_name, RTE_ETH_LINK_UP); 1323 else 1324 dpaa_eth_dev_start(dev); 1325 return 0; 1326 } 1327 1328 static int 1329 dpaa_flow_ctrl_set(struct rte_eth_dev *dev, 1330 struct rte_eth_fc_conf *fc_conf) 1331 { 1332 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1333 struct rte_eth_fc_conf *net_fc; 1334 1335 PMD_INIT_FUNC_TRACE(); 1336 1337 if (!(dpaa_intf->fc_conf)) { 1338 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1339 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1340 if (!dpaa_intf->fc_conf) { 1341 DPAA_PMD_ERR("unable to save flow control info"); 1342 return -ENOMEM; 1343 } 1344 } 1345 net_fc = dpaa_intf->fc_conf; 1346 1347 if (fc_conf->high_water < fc_conf->low_water) { 1348 DPAA_PMD_ERR("Incorrect Flow Control Configuration"); 1349 return -EINVAL; 1350 } 1351 1352 if (fc_conf->mode == RTE_ETH_FC_NONE) { 1353 return 0; 1354 } else if (fc_conf->mode == RTE_ETH_FC_TX_PAUSE || 1355 fc_conf->mode == RTE_ETH_FC_FULL) { 1356 fman_if_set_fc_threshold(dev->process_private, 1357 fc_conf->high_water, 1358 fc_conf->low_water, 1359 dpaa_intf->bp_info->bpid); 1360 if (fc_conf->pause_time) 1361 fman_if_set_fc_quanta(dev->process_private, 1362 fc_conf->pause_time); 1363 } 1364 1365 /* Save the information in dpaa device */ 1366 net_fc->pause_time = fc_conf->pause_time; 1367 net_fc->high_water = fc_conf->high_water; 1368 net_fc->low_water = fc_conf->low_water; 1369 net_fc->send_xon = fc_conf->send_xon; 1370 net_fc->mac_ctrl_frame_fwd = fc_conf->mac_ctrl_frame_fwd; 1371 net_fc->mode = fc_conf->mode; 1372 net_fc->autoneg = fc_conf->autoneg; 1373 1374 return 0; 1375 } 1376 1377 static int 1378 dpaa_flow_ctrl_get(struct rte_eth_dev *dev, 1379 struct rte_eth_fc_conf *fc_conf) 1380 { 1381 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1382 struct rte_eth_fc_conf *net_fc = dpaa_intf->fc_conf; 1383 int ret; 1384 1385 PMD_INIT_FUNC_TRACE(); 1386 1387 if (net_fc) { 1388 fc_conf->pause_time = net_fc->pause_time; 1389 fc_conf->high_water = net_fc->high_water; 1390 fc_conf->low_water = net_fc->low_water; 1391 fc_conf->send_xon = net_fc->send_xon; 1392 fc_conf->mac_ctrl_frame_fwd = net_fc->mac_ctrl_frame_fwd; 1393 fc_conf->mode = net_fc->mode; 1394 fc_conf->autoneg = net_fc->autoneg; 1395 return 0; 1396 } 1397 ret = fman_if_get_fc_threshold(dev->process_private); 1398 if (ret) { 1399 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1400 fc_conf->pause_time = 1401 fman_if_get_fc_quanta(dev->process_private); 1402 } else { 1403 fc_conf->mode = RTE_ETH_FC_NONE; 1404 } 1405 1406 return 0; 1407 } 1408 1409 static int 1410 dpaa_dev_add_mac_addr(struct rte_eth_dev *dev, 1411 struct rte_ether_addr *addr, 1412 uint32_t index, 1413 __rte_unused uint32_t pool) 1414 { 1415 int ret; 1416 1417 PMD_INIT_FUNC_TRACE(); 1418 1419 ret = fman_if_add_mac_addr(dev->process_private, 1420 addr->addr_bytes, index); 1421 1422 if (ret) 1423 DPAA_PMD_ERR("Adding the MAC ADDR failed: err = %d", ret); 1424 return 0; 1425 } 1426 1427 static void 1428 dpaa_dev_remove_mac_addr(struct rte_eth_dev *dev, 1429 uint32_t index) 1430 { 1431 PMD_INIT_FUNC_TRACE(); 1432 1433 fman_if_clear_mac_addr(dev->process_private, index); 1434 } 1435 1436 static int 1437 dpaa_dev_set_mac_addr(struct rte_eth_dev *dev, 1438 struct rte_ether_addr *addr) 1439 { 1440 int ret; 1441 1442 PMD_INIT_FUNC_TRACE(); 1443 1444 ret = fman_if_add_mac_addr(dev->process_private, addr->addr_bytes, 0); 1445 if (ret) 1446 DPAA_PMD_ERR("Setting the MAC ADDR failed %d", ret); 1447 1448 return ret; 1449 } 1450 1451 static int 1452 dpaa_dev_rss_hash_update(struct rte_eth_dev *dev, 1453 struct rte_eth_rss_conf *rss_conf) 1454 { 1455 struct rte_eth_dev_data *data = dev->data; 1456 struct rte_eth_conf *eth_conf = &data->dev_conf; 1457 1458 PMD_INIT_FUNC_TRACE(); 1459 1460 if (!(default_q || fmc_q)) { 1461 if (dpaa_fm_config(dev, rss_conf->rss_hf)) { 1462 DPAA_PMD_ERR("FM port configuration: Failed\n"); 1463 return -1; 1464 } 1465 eth_conf->rx_adv_conf.rss_conf.rss_hf = rss_conf->rss_hf; 1466 } else { 1467 DPAA_PMD_ERR("Function not supported\n"); 1468 return -ENOTSUP; 1469 } 1470 return 0; 1471 } 1472 1473 static int 1474 dpaa_dev_rss_hash_conf_get(struct rte_eth_dev *dev, 1475 struct rte_eth_rss_conf *rss_conf) 1476 { 1477 struct rte_eth_dev_data *data = dev->data; 1478 struct rte_eth_conf *eth_conf = &data->dev_conf; 1479 1480 /* dpaa does not support rss_key, so length should be 0*/ 1481 rss_conf->rss_key_len = 0; 1482 rss_conf->rss_hf = eth_conf->rx_adv_conf.rss_conf.rss_hf; 1483 return 0; 1484 } 1485 1486 static int dpaa_dev_queue_intr_enable(struct rte_eth_dev *dev, 1487 uint16_t queue_id) 1488 { 1489 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1490 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1491 1492 if (!rxq->is_static) 1493 return -EINVAL; 1494 1495 return qman_fq_portal_irqsource_add(rxq->qp, QM_PIRQ_DQRI); 1496 } 1497 1498 static int dpaa_dev_queue_intr_disable(struct rte_eth_dev *dev, 1499 uint16_t queue_id) 1500 { 1501 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1502 struct qman_fq *rxq = &dpaa_intf->rx_queues[queue_id]; 1503 uint32_t temp; 1504 ssize_t temp1; 1505 1506 if (!rxq->is_static) 1507 return -EINVAL; 1508 1509 qman_fq_portal_irqsource_remove(rxq->qp, ~0); 1510 1511 temp1 = read(rxq->q_fd, &temp, sizeof(temp)); 1512 if (temp1 != sizeof(temp)) 1513 DPAA_PMD_DEBUG("read did not return anything"); 1514 1515 qman_fq_portal_thread_irq(rxq->qp); 1516 1517 return 0; 1518 } 1519 1520 static void 1521 dpaa_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1522 struct rte_eth_rxq_info *qinfo) 1523 { 1524 struct dpaa_if *dpaa_intf = dev->data->dev_private; 1525 struct qman_fq *rxq; 1526 int ret; 1527 1528 rxq = dev->data->rx_queues[queue_id]; 1529 1530 qinfo->mp = dpaa_intf->bp_info->mp; 1531 qinfo->scattered_rx = dev->data->scattered_rx; 1532 qinfo->nb_desc = rxq->nb_desc; 1533 1534 /* Report the HW Rx buffer length to user */ 1535 ret = fman_if_get_maxfrm(dev->process_private); 1536 if (ret > 0) 1537 qinfo->rx_buf_size = ret; 1538 1539 qinfo->conf.rx_free_thresh = 1; 1540 qinfo->conf.rx_drop_en = 1; 1541 qinfo->conf.rx_deferred_start = 0; 1542 qinfo->conf.offloads = rxq->offloads; 1543 } 1544 1545 static void 1546 dpaa_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id, 1547 struct rte_eth_txq_info *qinfo) 1548 { 1549 struct qman_fq *txq; 1550 1551 txq = dev->data->tx_queues[queue_id]; 1552 1553 qinfo->nb_desc = txq->nb_desc; 1554 qinfo->conf.tx_thresh.pthresh = 0; 1555 qinfo->conf.tx_thresh.hthresh = 0; 1556 qinfo->conf.tx_thresh.wthresh = 0; 1557 1558 qinfo->conf.tx_free_thresh = 0; 1559 qinfo->conf.tx_rs_thresh = 0; 1560 qinfo->conf.offloads = txq->offloads; 1561 qinfo->conf.tx_deferred_start = 0; 1562 } 1563 1564 static struct eth_dev_ops dpaa_devops = { 1565 .dev_configure = dpaa_eth_dev_configure, 1566 .dev_start = dpaa_eth_dev_start, 1567 .dev_stop = dpaa_eth_dev_stop, 1568 .dev_close = dpaa_eth_dev_close, 1569 .dev_infos_get = dpaa_eth_dev_info, 1570 .dev_supported_ptypes_get = dpaa_supported_ptypes_get, 1571 1572 .rx_queue_setup = dpaa_eth_rx_queue_setup, 1573 .tx_queue_setup = dpaa_eth_tx_queue_setup, 1574 .rx_burst_mode_get = dpaa_dev_rx_burst_mode_get, 1575 .tx_burst_mode_get = dpaa_dev_tx_burst_mode_get, 1576 .rxq_info_get = dpaa_rxq_info_get, 1577 .txq_info_get = dpaa_txq_info_get, 1578 1579 .flow_ctrl_get = dpaa_flow_ctrl_get, 1580 .flow_ctrl_set = dpaa_flow_ctrl_set, 1581 1582 .link_update = dpaa_eth_link_update, 1583 .stats_get = dpaa_eth_stats_get, 1584 .xstats_get = dpaa_dev_xstats_get, 1585 .xstats_get_by_id = dpaa_xstats_get_by_id, 1586 .xstats_get_names_by_id = dpaa_xstats_get_names_by_id, 1587 .xstats_get_names = dpaa_xstats_get_names, 1588 .xstats_reset = dpaa_eth_stats_reset, 1589 .stats_reset = dpaa_eth_stats_reset, 1590 .promiscuous_enable = dpaa_eth_promiscuous_enable, 1591 .promiscuous_disable = dpaa_eth_promiscuous_disable, 1592 .allmulticast_enable = dpaa_eth_multicast_enable, 1593 .allmulticast_disable = dpaa_eth_multicast_disable, 1594 .mtu_set = dpaa_mtu_set, 1595 .dev_set_link_down = dpaa_link_down, 1596 .dev_set_link_up = dpaa_link_up, 1597 .mac_addr_add = dpaa_dev_add_mac_addr, 1598 .mac_addr_remove = dpaa_dev_remove_mac_addr, 1599 .mac_addr_set = dpaa_dev_set_mac_addr, 1600 1601 .fw_version_get = dpaa_fw_version_get, 1602 1603 .rx_queue_intr_enable = dpaa_dev_queue_intr_enable, 1604 .rx_queue_intr_disable = dpaa_dev_queue_intr_disable, 1605 .rss_hash_update = dpaa_dev_rss_hash_update, 1606 .rss_hash_conf_get = dpaa_dev_rss_hash_conf_get, 1607 }; 1608 1609 static bool 1610 is_device_supported(struct rte_eth_dev *dev, struct rte_dpaa_driver *drv) 1611 { 1612 if (strcmp(dev->device->driver->name, 1613 drv->driver.name)) 1614 return false; 1615 1616 return true; 1617 } 1618 1619 static bool 1620 is_dpaa_supported(struct rte_eth_dev *dev) 1621 { 1622 return is_device_supported(dev, &rte_dpaa_pmd); 1623 } 1624 1625 int 1626 rte_pmd_dpaa_set_tx_loopback(uint16_t port, uint8_t on) 1627 { 1628 struct rte_eth_dev *dev; 1629 1630 RTE_ETH_VALID_PORTID_OR_ERR_RET(port, -ENODEV); 1631 1632 dev = &rte_eth_devices[port]; 1633 1634 if (!is_dpaa_supported(dev)) 1635 return -ENOTSUP; 1636 1637 if (on) 1638 fman_if_loopback_enable(dev->process_private); 1639 else 1640 fman_if_loopback_disable(dev->process_private); 1641 1642 return 0; 1643 } 1644 1645 static int dpaa_fc_set_default(struct dpaa_if *dpaa_intf, 1646 struct fman_if *fman_intf) 1647 { 1648 struct rte_eth_fc_conf *fc_conf; 1649 int ret; 1650 1651 PMD_INIT_FUNC_TRACE(); 1652 1653 if (!(dpaa_intf->fc_conf)) { 1654 dpaa_intf->fc_conf = rte_zmalloc(NULL, 1655 sizeof(struct rte_eth_fc_conf), MAX_CACHELINE); 1656 if (!dpaa_intf->fc_conf) { 1657 DPAA_PMD_ERR("unable to save flow control info"); 1658 return -ENOMEM; 1659 } 1660 } 1661 fc_conf = dpaa_intf->fc_conf; 1662 ret = fman_if_get_fc_threshold(fman_intf); 1663 if (ret) { 1664 fc_conf->mode = RTE_ETH_FC_TX_PAUSE; 1665 fc_conf->pause_time = fman_if_get_fc_quanta(fman_intf); 1666 } else { 1667 fc_conf->mode = RTE_ETH_FC_NONE; 1668 } 1669 1670 return 0; 1671 } 1672 1673 /* Initialise an Rx FQ */ 1674 static int dpaa_rx_queue_init(struct qman_fq *fq, struct qman_cgr *cgr_rx, 1675 uint32_t fqid) 1676 { 1677 struct qm_mcc_initfq opts = {0}; 1678 int ret; 1679 u32 flags = QMAN_FQ_FLAG_NO_ENQUEUE; 1680 struct qm_mcc_initcgr cgr_opts = { 1681 .we_mask = QM_CGR_WE_CS_THRES | 1682 QM_CGR_WE_CSTD_EN | 1683 QM_CGR_WE_MODE, 1684 .cgr = { 1685 .cstd_en = QM_CGR_EN, 1686 .mode = QMAN_CGR_MODE_FRAME 1687 } 1688 }; 1689 1690 if (fmc_q || default_q) { 1691 ret = qman_reserve_fqid(fqid); 1692 if (ret) { 1693 DPAA_PMD_ERR("reserve rx fqid 0x%x failed, ret: %d", 1694 fqid, ret); 1695 return -EINVAL; 1696 } 1697 } 1698 1699 DPAA_PMD_DEBUG("creating rx fq %p, fqid 0x%x", fq, fqid); 1700 ret = qman_create_fq(fqid, flags, fq); 1701 if (ret) { 1702 DPAA_PMD_ERR("create rx fqid 0x%x failed with ret: %d", 1703 fqid, ret); 1704 return ret; 1705 } 1706 fq->is_static = false; 1707 1708 dpaa_poll_queue_default_config(&opts); 1709 1710 if (cgr_rx) { 1711 /* Enable tail drop with cgr on this queue */ 1712 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, td_threshold, 0); 1713 cgr_rx->cb = NULL; 1714 ret = qman_create_cgr(cgr_rx, QMAN_CGR_FLAG_USE_INIT, 1715 &cgr_opts); 1716 if (ret) { 1717 DPAA_PMD_WARN( 1718 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1719 fq->fqid, ret); 1720 goto without_cgr; 1721 } 1722 opts.we_mask |= QM_INITFQ_WE_CGID; 1723 opts.fqd.cgid = cgr_rx->cgrid; 1724 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1725 } 1726 without_cgr: 1727 ret = qman_init_fq(fq, 0, &opts); 1728 if (ret) 1729 DPAA_PMD_ERR("init rx fqid 0x%x failed with ret:%d", fqid, ret); 1730 return ret; 1731 } 1732 1733 /* Initialise a Tx FQ */ 1734 static int dpaa_tx_queue_init(struct qman_fq *fq, 1735 struct fman_if *fman_intf, 1736 struct qman_cgr *cgr_tx) 1737 { 1738 struct qm_mcc_initfq opts = {0}; 1739 struct qm_mcc_initcgr cgr_opts = { 1740 .we_mask = QM_CGR_WE_CS_THRES | 1741 QM_CGR_WE_CSTD_EN | 1742 QM_CGR_WE_MODE, 1743 .cgr = { 1744 .cstd_en = QM_CGR_EN, 1745 .mode = QMAN_CGR_MODE_FRAME 1746 } 1747 }; 1748 int ret; 1749 1750 ret = qman_create_fq(0, QMAN_FQ_FLAG_DYNAMIC_FQID | 1751 QMAN_FQ_FLAG_TO_DCPORTAL, fq); 1752 if (ret) { 1753 DPAA_PMD_ERR("create tx fq failed with ret: %d", ret); 1754 return ret; 1755 } 1756 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL | 1757 QM_INITFQ_WE_CONTEXTB | QM_INITFQ_WE_CONTEXTA; 1758 opts.fqd.dest.channel = fman_intf->tx_channel_id; 1759 opts.fqd.dest.wq = DPAA_IF_TX_PRIORITY; 1760 opts.fqd.fq_ctrl = QM_FQCTRL_PREFERINCACHE; 1761 opts.fqd.context_b = 0; 1762 /* no tx-confirmation */ 1763 opts.fqd.context_a.hi = 0x80000000 | fman_dealloc_bufs_mask_hi; 1764 opts.fqd.context_a.lo = 0 | fman_dealloc_bufs_mask_lo; 1765 if (fman_ip_rev >= FMAN_V3) { 1766 /* Set B0V bit in contextA to set ASPID to 0 */ 1767 opts.fqd.context_a.hi |= 0x04000000; 1768 } 1769 DPAA_PMD_DEBUG("init tx fq %p, fqid 0x%x", fq, fq->fqid); 1770 1771 if (cgr_tx) { 1772 /* Enable tail drop with cgr on this queue */ 1773 qm_cgr_cs_thres_set64(&cgr_opts.cgr.cs_thres, 1774 td_tx_threshold, 0); 1775 cgr_tx->cb = NULL; 1776 ret = qman_create_cgr(cgr_tx, QMAN_CGR_FLAG_USE_INIT, 1777 &cgr_opts); 1778 if (ret) { 1779 DPAA_PMD_WARN( 1780 "rx taildrop init fail on rx fqid 0x%x(ret=%d)", 1781 fq->fqid, ret); 1782 goto without_cgr; 1783 } 1784 opts.we_mask |= QM_INITFQ_WE_CGID; 1785 opts.fqd.cgid = cgr_tx->cgrid; 1786 opts.fqd.fq_ctrl |= QM_FQCTRL_CGE; 1787 DPAA_PMD_DEBUG("Tx FQ tail drop enabled, threshold = %d\n", 1788 td_tx_threshold); 1789 } 1790 without_cgr: 1791 ret = qman_init_fq(fq, QMAN_INITFQ_FLAG_SCHED, &opts); 1792 if (ret) 1793 DPAA_PMD_ERR("init tx fqid 0x%x failed %d", fq->fqid, ret); 1794 return ret; 1795 } 1796 1797 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 1798 /* Initialise a DEBUG FQ ([rt]x_error, rx_default). */ 1799 static int dpaa_debug_queue_init(struct qman_fq *fq, uint32_t fqid) 1800 { 1801 struct qm_mcc_initfq opts = {0}; 1802 int ret; 1803 1804 PMD_INIT_FUNC_TRACE(); 1805 1806 ret = qman_reserve_fqid(fqid); 1807 if (ret) { 1808 DPAA_PMD_ERR("Reserve debug fqid %d failed with ret: %d", 1809 fqid, ret); 1810 return -EINVAL; 1811 } 1812 /* "map" this Rx FQ to one of the interfaces Tx FQID */ 1813 DPAA_PMD_DEBUG("Creating debug fq %p, fqid %d", fq, fqid); 1814 ret = qman_create_fq(fqid, QMAN_FQ_FLAG_NO_ENQUEUE, fq); 1815 if (ret) { 1816 DPAA_PMD_ERR("create debug fqid %d failed with ret: %d", 1817 fqid, ret); 1818 return ret; 1819 } 1820 opts.we_mask = QM_INITFQ_WE_DESTWQ | QM_INITFQ_WE_FQCTRL; 1821 opts.fqd.dest.wq = DPAA_IF_DEBUG_PRIORITY; 1822 ret = qman_init_fq(fq, 0, &opts); 1823 if (ret) 1824 DPAA_PMD_ERR("init debug fqid %d failed with ret: %d", 1825 fqid, ret); 1826 return ret; 1827 } 1828 #endif 1829 1830 /* Initialise a network interface */ 1831 static int 1832 dpaa_dev_init_secondary(struct rte_eth_dev *eth_dev) 1833 { 1834 struct rte_dpaa_device *dpaa_device; 1835 struct fm_eth_port_cfg *cfg; 1836 struct dpaa_if *dpaa_intf; 1837 struct fman_if *fman_intf; 1838 int dev_id; 1839 1840 PMD_INIT_FUNC_TRACE(); 1841 1842 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1843 dev_id = dpaa_device->id.dev_id; 1844 cfg = dpaa_get_eth_port_cfg(dev_id); 1845 fman_intf = cfg->fman_if; 1846 eth_dev->process_private = fman_intf; 1847 1848 /* Plugging of UCODE burst API not supported in Secondary */ 1849 dpaa_intf = eth_dev->data->dev_private; 1850 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 1851 if (dpaa_intf->cgr_tx) 1852 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx_slow; 1853 else 1854 eth_dev->tx_pkt_burst = dpaa_eth_queue_tx; 1855 #ifdef CONFIG_FSL_QMAN_FQ_LOOKUP 1856 qman_set_fq_lookup_table( 1857 dpaa_intf->rx_queues->qman_fq_lookup_table); 1858 #endif 1859 1860 return 0; 1861 } 1862 1863 /* Initialise a network interface */ 1864 static int 1865 dpaa_dev_init(struct rte_eth_dev *eth_dev) 1866 { 1867 int num_rx_fqs, fqid; 1868 int loop, ret = 0; 1869 int dev_id; 1870 struct rte_dpaa_device *dpaa_device; 1871 struct dpaa_if *dpaa_intf; 1872 struct fm_eth_port_cfg *cfg; 1873 struct fman_if *fman_intf; 1874 struct fman_if_bpool *bp, *tmp_bp; 1875 uint32_t cgrid[DPAA_MAX_NUM_PCD_QUEUES]; 1876 uint32_t cgrid_tx[MAX_DPAA_CORES]; 1877 uint32_t dev_rx_fqids[DPAA_MAX_NUM_PCD_QUEUES]; 1878 int8_t dev_vspids[DPAA_MAX_NUM_PCD_QUEUES]; 1879 int8_t vsp_id = -1; 1880 1881 PMD_INIT_FUNC_TRACE(); 1882 1883 dpaa_device = DEV_TO_DPAA_DEVICE(eth_dev->device); 1884 dev_id = dpaa_device->id.dev_id; 1885 dpaa_intf = eth_dev->data->dev_private; 1886 cfg = dpaa_get_eth_port_cfg(dev_id); 1887 fman_intf = cfg->fman_if; 1888 1889 dpaa_intf->name = dpaa_device->name; 1890 1891 /* save fman_if & cfg in the interface structure */ 1892 eth_dev->process_private = fman_intf; 1893 dpaa_intf->ifid = dev_id; 1894 dpaa_intf->cfg = cfg; 1895 1896 memset((char *)dev_rx_fqids, 0, 1897 sizeof(uint32_t) * DPAA_MAX_NUM_PCD_QUEUES); 1898 1899 memset(dev_vspids, -1, DPAA_MAX_NUM_PCD_QUEUES); 1900 1901 /* Initialize Rx FQ's */ 1902 if (default_q) { 1903 num_rx_fqs = DPAA_DEFAULT_NUM_PCD_QUEUES; 1904 } else if (fmc_q) { 1905 num_rx_fqs = dpaa_port_fmc_init(fman_intf, dev_rx_fqids, 1906 dev_vspids, 1907 DPAA_MAX_NUM_PCD_QUEUES); 1908 if (num_rx_fqs < 0) { 1909 DPAA_PMD_ERR("%s FMC initializes failed!", 1910 dpaa_intf->name); 1911 goto free_rx; 1912 } 1913 if (!num_rx_fqs) { 1914 DPAA_PMD_WARN("%s is not configured by FMC.", 1915 dpaa_intf->name); 1916 } 1917 } else { 1918 /* FMCLESS mode, load balance to multiple cores.*/ 1919 num_rx_fqs = rte_lcore_count(); 1920 } 1921 1922 /* Each device can not have more than DPAA_MAX_NUM_PCD_QUEUES RX 1923 * queues. 1924 */ 1925 if (num_rx_fqs < 0 || num_rx_fqs > DPAA_MAX_NUM_PCD_QUEUES) { 1926 DPAA_PMD_ERR("Invalid number of RX queues\n"); 1927 return -EINVAL; 1928 } 1929 1930 if (num_rx_fqs > 0) { 1931 dpaa_intf->rx_queues = rte_zmalloc(NULL, 1932 sizeof(struct qman_fq) * num_rx_fqs, MAX_CACHELINE); 1933 if (!dpaa_intf->rx_queues) { 1934 DPAA_PMD_ERR("Failed to alloc mem for RX queues\n"); 1935 return -ENOMEM; 1936 } 1937 } else { 1938 dpaa_intf->rx_queues = NULL; 1939 } 1940 1941 memset(cgrid, 0, sizeof(cgrid)); 1942 memset(cgrid_tx, 0, sizeof(cgrid_tx)); 1943 1944 /* if DPAA_TX_TAILDROP_THRESHOLD is set, use that value; if 0, it means 1945 * Tx tail drop is disabled. 1946 */ 1947 if (getenv("DPAA_TX_TAILDROP_THRESHOLD")) { 1948 td_tx_threshold = atoi(getenv("DPAA_TX_TAILDROP_THRESHOLD")); 1949 DPAA_PMD_DEBUG("Tail drop threshold env configured: %u", 1950 td_tx_threshold); 1951 /* if a very large value is being configured */ 1952 if (td_tx_threshold > UINT16_MAX) 1953 td_tx_threshold = CGR_RX_PERFQ_THRESH; 1954 } 1955 1956 /* If congestion control is enabled globally*/ 1957 if (num_rx_fqs > 0 && td_threshold) { 1958 dpaa_intf->cgr_rx = rte_zmalloc(NULL, 1959 sizeof(struct qman_cgr) * num_rx_fqs, MAX_CACHELINE); 1960 if (!dpaa_intf->cgr_rx) { 1961 DPAA_PMD_ERR("Failed to alloc mem for cgr_rx\n"); 1962 ret = -ENOMEM; 1963 goto free_rx; 1964 } 1965 1966 ret = qman_alloc_cgrid_range(&cgrid[0], num_rx_fqs, 1, 0); 1967 if (ret != num_rx_fqs) { 1968 DPAA_PMD_WARN("insufficient CGRIDs available"); 1969 ret = -EINVAL; 1970 goto free_rx; 1971 } 1972 } else { 1973 dpaa_intf->cgr_rx = NULL; 1974 } 1975 1976 if (!fmc_q && !default_q) { 1977 ret = qman_alloc_fqid_range(dev_rx_fqids, num_rx_fqs, 1978 num_rx_fqs, 0); 1979 if (ret < 0) { 1980 DPAA_PMD_ERR("Failed to alloc rx fqid's\n"); 1981 goto free_rx; 1982 } 1983 } 1984 1985 for (loop = 0; loop < num_rx_fqs; loop++) { 1986 if (default_q) 1987 fqid = cfg->rx_def; 1988 else 1989 fqid = dev_rx_fqids[loop]; 1990 1991 vsp_id = dev_vspids[loop]; 1992 1993 if (dpaa_intf->cgr_rx) 1994 dpaa_intf->cgr_rx[loop].cgrid = cgrid[loop]; 1995 1996 ret = dpaa_rx_queue_init(&dpaa_intf->rx_queues[loop], 1997 dpaa_intf->cgr_rx ? &dpaa_intf->cgr_rx[loop] : NULL, 1998 fqid); 1999 if (ret) 2000 goto free_rx; 2001 dpaa_intf->rx_queues[loop].vsp_id = vsp_id; 2002 dpaa_intf->rx_queues[loop].dpaa_intf = dpaa_intf; 2003 } 2004 dpaa_intf->nb_rx_queues = num_rx_fqs; 2005 2006 /* Initialise Tx FQs.free_rx Have as many Tx FQ's as number of cores */ 2007 dpaa_intf->tx_queues = rte_zmalloc(NULL, sizeof(struct qman_fq) * 2008 MAX_DPAA_CORES, MAX_CACHELINE); 2009 if (!dpaa_intf->tx_queues) { 2010 DPAA_PMD_ERR("Failed to alloc mem for TX queues\n"); 2011 ret = -ENOMEM; 2012 goto free_rx; 2013 } 2014 2015 /* If congestion control is enabled globally*/ 2016 if (td_tx_threshold) { 2017 dpaa_intf->cgr_tx = rte_zmalloc(NULL, 2018 sizeof(struct qman_cgr) * MAX_DPAA_CORES, 2019 MAX_CACHELINE); 2020 if (!dpaa_intf->cgr_tx) { 2021 DPAA_PMD_ERR("Failed to alloc mem for cgr_tx\n"); 2022 ret = -ENOMEM; 2023 goto free_rx; 2024 } 2025 2026 ret = qman_alloc_cgrid_range(&cgrid_tx[0], MAX_DPAA_CORES, 2027 1, 0); 2028 if (ret != MAX_DPAA_CORES) { 2029 DPAA_PMD_WARN("insufficient CGRIDs available"); 2030 ret = -EINVAL; 2031 goto free_rx; 2032 } 2033 } else { 2034 dpaa_intf->cgr_tx = NULL; 2035 } 2036 2037 2038 for (loop = 0; loop < MAX_DPAA_CORES; loop++) { 2039 if (dpaa_intf->cgr_tx) 2040 dpaa_intf->cgr_tx[loop].cgrid = cgrid_tx[loop]; 2041 2042 ret = dpaa_tx_queue_init(&dpaa_intf->tx_queues[loop], 2043 fman_intf, 2044 dpaa_intf->cgr_tx ? &dpaa_intf->cgr_tx[loop] : NULL); 2045 if (ret) 2046 goto free_tx; 2047 dpaa_intf->tx_queues[loop].dpaa_intf = dpaa_intf; 2048 } 2049 dpaa_intf->nb_tx_queues = MAX_DPAA_CORES; 2050 2051 #ifdef RTE_LIBRTE_DPAA_DEBUG_DRIVER 2052 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2053 [DPAA_DEBUG_FQ_RX_ERROR], fman_intf->fqid_rx_err); 2054 if (ret) { 2055 DPAA_PMD_ERR("DPAA RX ERROR queue init failed!"); 2056 goto free_tx; 2057 } 2058 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_RX_ERROR].dpaa_intf = dpaa_intf; 2059 ret = dpaa_debug_queue_init(&dpaa_intf->debug_queues 2060 [DPAA_DEBUG_FQ_TX_ERROR], fman_intf->fqid_tx_err); 2061 if (ret) { 2062 DPAA_PMD_ERR("DPAA TX ERROR queue init failed!"); 2063 goto free_tx; 2064 } 2065 dpaa_intf->debug_queues[DPAA_DEBUG_FQ_TX_ERROR].dpaa_intf = dpaa_intf; 2066 #endif 2067 2068 DPAA_PMD_DEBUG("All frame queues created"); 2069 2070 /* Get the initial configuration for flow control */ 2071 dpaa_fc_set_default(dpaa_intf, fman_intf); 2072 2073 /* reset bpool list, initialize bpool dynamically */ 2074 list_for_each_entry_safe(bp, tmp_bp, &cfg->fman_if->bpool_list, node) { 2075 list_del(&bp->node); 2076 rte_free(bp); 2077 } 2078 2079 /* Populate ethdev structure */ 2080 eth_dev->dev_ops = &dpaa_devops; 2081 eth_dev->rx_queue_count = dpaa_dev_rx_queue_count; 2082 eth_dev->rx_pkt_burst = dpaa_eth_queue_rx; 2083 eth_dev->tx_pkt_burst = dpaa_eth_tx_drop_all; 2084 2085 /* Allocate memory for storing MAC addresses */ 2086 eth_dev->data->mac_addrs = rte_zmalloc("mac_addr", 2087 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER, 0); 2088 if (eth_dev->data->mac_addrs == NULL) { 2089 DPAA_PMD_ERR("Failed to allocate %d bytes needed to " 2090 "store MAC addresses", 2091 RTE_ETHER_ADDR_LEN * DPAA_MAX_MAC_FILTER); 2092 ret = -ENOMEM; 2093 goto free_tx; 2094 } 2095 2096 /* copy the primary mac address */ 2097 rte_ether_addr_copy(&fman_intf->mac_addr, ð_dev->data->mac_addrs[0]); 2098 2099 DPAA_PMD_INFO("net: dpaa: %s: " RTE_ETHER_ADDR_PRT_FMT, 2100 dpaa_device->name, RTE_ETHER_ADDR_BYTES(&fman_intf->mac_addr)); 2101 2102 if (!fman_intf->is_shared_mac) { 2103 /* Configure error packet handling */ 2104 fman_if_receive_rx_errors(fman_intf, 2105 FM_FD_RX_STATUS_ERR_MASK); 2106 /* Disable RX mode */ 2107 fman_if_disable_rx(fman_intf); 2108 /* Disable promiscuous mode */ 2109 fman_if_promiscuous_disable(fman_intf); 2110 /* Disable multicast */ 2111 fman_if_reset_mcast_filter_table(fman_intf); 2112 /* Reset interface statistics */ 2113 fman_if_stats_reset(fman_intf); 2114 /* Disable SG by default */ 2115 fman_if_set_sg(fman_intf, 0); 2116 fman_if_set_maxfrm(fman_intf, 2117 RTE_ETHER_MAX_LEN + VLAN_TAG_SIZE); 2118 } 2119 2120 return 0; 2121 2122 free_tx: 2123 rte_free(dpaa_intf->tx_queues); 2124 dpaa_intf->tx_queues = NULL; 2125 dpaa_intf->nb_tx_queues = 0; 2126 2127 free_rx: 2128 rte_free(dpaa_intf->cgr_rx); 2129 rte_free(dpaa_intf->cgr_tx); 2130 rte_free(dpaa_intf->rx_queues); 2131 dpaa_intf->rx_queues = NULL; 2132 dpaa_intf->nb_rx_queues = 0; 2133 return ret; 2134 } 2135 2136 static int 2137 rte_dpaa_probe(struct rte_dpaa_driver *dpaa_drv, 2138 struct rte_dpaa_device *dpaa_dev) 2139 { 2140 int diag; 2141 int ret; 2142 struct rte_eth_dev *eth_dev; 2143 2144 PMD_INIT_FUNC_TRACE(); 2145 2146 if ((DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE) > 2147 RTE_PKTMBUF_HEADROOM) { 2148 DPAA_PMD_ERR( 2149 "RTE_PKTMBUF_HEADROOM(%d) shall be > DPAA Annotation req(%d)", 2150 RTE_PKTMBUF_HEADROOM, 2151 DPAA_MBUF_HW_ANNOTATION + DPAA_FD_PTA_SIZE); 2152 2153 return -1; 2154 } 2155 2156 /* In case of secondary process, the device is already configured 2157 * and no further action is required, except portal initialization 2158 * and verifying secondary attachment to port name. 2159 */ 2160 if (rte_eal_process_type() != RTE_PROC_PRIMARY) { 2161 eth_dev = rte_eth_dev_attach_secondary(dpaa_dev->name); 2162 if (!eth_dev) 2163 return -ENOMEM; 2164 eth_dev->device = &dpaa_dev->device; 2165 eth_dev->dev_ops = &dpaa_devops; 2166 2167 ret = dpaa_dev_init_secondary(eth_dev); 2168 if (ret != 0) { 2169 DPAA_PMD_ERR("secondary dev init failed"); 2170 return ret; 2171 } 2172 2173 rte_eth_dev_probing_finish(eth_dev); 2174 return 0; 2175 } 2176 2177 if (!is_global_init && (rte_eal_process_type() == RTE_PROC_PRIMARY)) { 2178 if (access("/tmp/fmc.bin", F_OK) == -1) { 2179 DPAA_PMD_INFO("* FMC not configured.Enabling default mode"); 2180 default_q = 1; 2181 } 2182 2183 if (!(default_q || fmc_q)) { 2184 if (dpaa_fm_init()) { 2185 DPAA_PMD_ERR("FM init failed\n"); 2186 return -1; 2187 } 2188 } 2189 2190 /* disabling the default push mode for LS1043 */ 2191 if (dpaa_svr_family == SVR_LS1043A_FAMILY) 2192 dpaa_push_mode_max_queue = 0; 2193 2194 /* if push mode queues to be enabled. Currently we are allowing 2195 * only one queue per thread. 2196 */ 2197 if (getenv("DPAA_PUSH_QUEUES_NUMBER")) { 2198 dpaa_push_mode_max_queue = 2199 atoi(getenv("DPAA_PUSH_QUEUES_NUMBER")); 2200 if (dpaa_push_mode_max_queue > DPAA_MAX_PUSH_MODE_QUEUE) 2201 dpaa_push_mode_max_queue = DPAA_MAX_PUSH_MODE_QUEUE; 2202 } 2203 2204 is_global_init = 1; 2205 } 2206 2207 if (unlikely(!DPAA_PER_LCORE_PORTAL)) { 2208 ret = rte_dpaa_portal_init((void *)1); 2209 if (ret) { 2210 DPAA_PMD_ERR("Unable to initialize portal"); 2211 return ret; 2212 } 2213 } 2214 2215 eth_dev = rte_eth_dev_allocate(dpaa_dev->name); 2216 if (!eth_dev) 2217 return -ENOMEM; 2218 2219 eth_dev->data->dev_private = 2220 rte_zmalloc("ethdev private structure", 2221 sizeof(struct dpaa_if), 2222 RTE_CACHE_LINE_SIZE); 2223 if (!eth_dev->data->dev_private) { 2224 DPAA_PMD_ERR("Cannot allocate memzone for port data"); 2225 rte_eth_dev_release_port(eth_dev); 2226 return -ENOMEM; 2227 } 2228 2229 eth_dev->device = &dpaa_dev->device; 2230 dpaa_dev->eth_dev = eth_dev; 2231 2232 qman_ern_register_cb(dpaa_free_mbuf); 2233 2234 if (dpaa_drv->drv_flags & RTE_DPAA_DRV_INTR_LSC) 2235 eth_dev->data->dev_flags |= RTE_ETH_DEV_INTR_LSC; 2236 2237 /* Invoke PMD device initialization function */ 2238 diag = dpaa_dev_init(eth_dev); 2239 if (diag == 0) { 2240 if (!dpaa_tx_sg_pool) { 2241 dpaa_tx_sg_pool = 2242 rte_pktmbuf_pool_create("dpaa_mbuf_tx_sg_pool", 2243 DPAA_POOL_SIZE, 2244 DPAA_POOL_CACHE_SIZE, 0, 2245 DPAA_MAX_SGS * sizeof(struct qm_sg_entry), 2246 rte_socket_id()); 2247 if (dpaa_tx_sg_pool == NULL) { 2248 DPAA_PMD_ERR("SG pool creation failed\n"); 2249 return -ENOMEM; 2250 } 2251 } 2252 rte_eth_dev_probing_finish(eth_dev); 2253 dpaa_valid_dev++; 2254 return 0; 2255 } 2256 2257 rte_eth_dev_release_port(eth_dev); 2258 return diag; 2259 } 2260 2261 static int 2262 rte_dpaa_remove(struct rte_dpaa_device *dpaa_dev) 2263 { 2264 struct rte_eth_dev *eth_dev; 2265 int ret; 2266 2267 PMD_INIT_FUNC_TRACE(); 2268 2269 eth_dev = dpaa_dev->eth_dev; 2270 dpaa_eth_dev_close(eth_dev); 2271 dpaa_valid_dev--; 2272 if (!dpaa_valid_dev) 2273 rte_mempool_free(dpaa_tx_sg_pool); 2274 ret = rte_eth_dev_release_port(eth_dev); 2275 2276 return ret; 2277 } 2278 2279 static void __attribute__((destructor(102))) dpaa_finish(void) 2280 { 2281 /* For secondary, primary will do all the cleanup */ 2282 if (rte_eal_process_type() != RTE_PROC_PRIMARY) 2283 return; 2284 2285 if (!(default_q || fmc_q)) { 2286 unsigned int i; 2287 2288 for (i = 0; i < RTE_MAX_ETHPORTS; i++) { 2289 if (rte_eth_devices[i].dev_ops == &dpaa_devops) { 2290 struct rte_eth_dev *dev = &rte_eth_devices[i]; 2291 struct dpaa_if *dpaa_intf = 2292 dev->data->dev_private; 2293 struct fman_if *fif = 2294 dev->process_private; 2295 if (dpaa_intf->port_handle) 2296 if (dpaa_fm_deconfig(dpaa_intf, fif)) 2297 DPAA_PMD_WARN("DPAA FM " 2298 "deconfig failed\n"); 2299 if (fif->num_profiles) { 2300 if (dpaa_port_vsp_cleanup(dpaa_intf, 2301 fif)) 2302 DPAA_PMD_WARN("DPAA FM vsp cleanup failed\n"); 2303 } 2304 } 2305 } 2306 if (is_global_init) 2307 if (dpaa_fm_term()) 2308 DPAA_PMD_WARN("DPAA FM term failed\n"); 2309 2310 is_global_init = 0; 2311 2312 DPAA_PMD_INFO("DPAA fman cleaned up"); 2313 } 2314 } 2315 2316 static struct rte_dpaa_driver rte_dpaa_pmd = { 2317 .drv_flags = RTE_DPAA_DRV_INTR_LSC, 2318 .drv_type = FSL_DPAA_ETH, 2319 .probe = rte_dpaa_probe, 2320 .remove = rte_dpaa_remove, 2321 }; 2322 2323 RTE_PMD_REGISTER_DPAA(net_dpaa, rte_dpaa_pmd); 2324 RTE_LOG_REGISTER_DEFAULT(dpaa_logtype_pmd, NOTICE); 2325