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Searched defs:ResultReg (Results 1 – 19 of 19) sorted by relevance

/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp362 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); fastMaterializeAlloca() local
385 Register ResultReg = createResultReg(RC); materializeInt() local
421 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); materializeFP() local
439 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); materializeFP() local
463 unsigned ResultReg; materializeGV() local
1065 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); simplifyAddress() local
1076 unsigned ResultReg = 0; simplifyAddress() local
1110 unsigned ResultReg; simplifyAddress() local
1216 unsigned ResultReg = 0; emitAddSub() local
1321 unsigned ResultReg; emitAddSub_rr() local
1366 unsigned ResultReg; emitAddSub_ri() local
1407 unsigned ResultReg; emitAddSub_rs() local
1451 unsigned ResultReg; emitAddSub_rx() local
1545 unsigned ResultReg; emitAdd_ri_() local
1603 unsigned ResultReg = 0; emitLogicalOp() local
1695 Register ResultReg = emitLogicalOp_ri() local
1737 Register ResultReg = emitLogicalOp_rs() local
1863 Register ResultReg = createResultReg(RC); emitLoad() local
1897 unsigned ResultReg; selectAddSub() local
1923 unsigned ResultReg; selectLogicalOp() local
1992 unsigned ResultReg = selectLoad() local
2540 unsigned ResultReg = 0; selectCmp() local
2663 Register ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg, optimizeSelect() local
2784 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC); selectSelect() local
2798 Register ResultReg = createResultReg(&AArch64::FPR64RegClass); selectFPExt() local
2814 Register ResultReg = createResultReg(&AArch64::FPR32RegClass); selectFPTrunc() local
2847 Register ResultReg = createResultReg( selectFPToInt() local
2893 Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg); selectIntToFP() local
3001 Register ResultReg = createResultReg(RC); fastLowerArguments() local
3113 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); finishCall() local
3327 unsigned ResultReg = emitLoad(VT, VT, Src); tryEmitSmallMemCpy() local
3471 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass); fastLowerIntrinsicCall() local
3610 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); fastLowerIntrinsicCall() local
3636 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg); fastLowerIntrinsicCall() local
3832 Register ResultReg = fastLowerIntrinsicCall() local
3976 unsigned ResultReg; selectTrunc() local
4019 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1); emiti1Ext() local
4095 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); emitLSL_rr() local
4121 Register ResultReg = createResultReg(RC); emitLSL_ri() local
4198 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); emitLSR_rr() local
4224 Register ResultReg = createResultReg(RC); emitLSR_ri() local
4314 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg); emitASR_rr() local
4340 Register ResultReg = createResultReg(RC); emitASR_ri() local
4587 Register ResultReg = createResultReg(&AArch64::GPR64RegClass); selectIntExt() local
4601 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt); selectIntExt() local
4645 Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg); selectRem() local
4694 unsigned ResultReg = selectMul() local
4711 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg); selectMul() local
4729 unsigned ResultReg = 0; selectShift() local
4785 unsigned ResultReg = 0; selectShift() local
4838 Register ResultReg = fastEmitInst_r(Opc, RC, Op0Reg); selectBitCast() local
4903 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2); selectSDiv() local
4936 unsigned ResultReg; selectSDiv() local
[all...]
H A DAArch64PointerAuth.cpp396 Register ResultReg = MBBI->getOperand(0).getReg(); expandPAuthBlend() local
H A DAArch64InstrInfo.cpp6664 Register ResultReg = Root.getOperand(0).getReg(); genFusedMultiply() local
6729 Register ResultReg = Root.getOperand(0).getReg(); genFNegatedMAD() local
6782 Register ResultReg = Root.getOperand(0).getReg(); genIndexedMultiply() local
6895 Register ResultReg = Root.getOperand(0).getReg(); genMaddR() local
6934 Register ResultReg = Root.getOperand(0).getReg(); genSubAdd2SubSub() local
[all...]
/llvm-project/llvm/lib/Target/X86/
H A DX86FastISel.cpp317 X86FastEmitLoad(MVT VT,X86AddressMode & AM,MachineMemOperand * MMO,unsigned & ResultReg,unsigned Alignment) X86FastEmitLoad() argument
701 X86FastEmitExtend(ISD::NodeType Opc,EVT DstVT,unsigned Src,EVT SrcVT,unsigned & ResultReg) X86FastEmitExtend() argument
1347 unsigned ResultReg = 0; X86SelectLoad() local
1447 unsigned ResultReg = 0; X86SelectCmp() local
1536 Register ResultReg = getRegForValue(I->getOperand(0)); X86SelectZExt() local
1594 Register ResultReg = getRegForValue(I->getOperand(0)); X86SelectSExt() local
1849 Register ResultReg = createResultReg(RC); X86SelectShift() local
1992 unsigned ResultReg = 0; X86SelectDivRem() local
2138 Register ResultReg = fastEmitInst_rri(Opc, RC, RHSReg, LHSReg, CC); X86FastEmitCMoveSelect() local
2194 unsigned ResultReg; X86FastEmitSSESelect() local
2338 Register ResultReg = X86FastEmitPseudoSelect() local
2364 Register ResultReg = createResultReg(RC); X86SelectSelect() local
2437 Register ResultReg = fastEmitInst_rr(Opcode, RC, ImplicitDefReg, OpReg); X86SelectIntToFP() local
2471 Register ResultReg = createResultReg(RC); X86SelectFPExtOrFPTrunc() local
2534 Register ResultReg = fastEmitInst_extractsubreg(MVT::i8, InputReg, X86SelectTrunc() local
2607 unsigned ResultReg = 0; fastLowerIntrinsicCall() local
2829 Register ResultReg = createResultReg(RC); fastLowerIntrinsicCall() local
2892 unsigned ResultReg = 0; fastLowerIntrinsicCall() local
3023 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); fastLowerIntrinsicCall() local
3077 Register ResultReg = fastEmitInst_rr(Opc, RC, LHSReg, RHSReg); fastLowerIntrinsicCall() local
3176 Register ResultReg = createResultReg(RC); fastLowerArguments() local
3304 unsigned ResultReg; fastLowerCall() local
3586 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy); fastLowerCall() local
3712 Register ResultReg = createResultReg(DstClass); fastSelectInstruction() local
3741 Register ResultReg = createResultReg(&X86::GR64RegClass); X86MaterializeInt() local
3822 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); X86MaterializeFP() local
3863 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); X86MaterializeGV() local
3917 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); fastMaterializeConstant() local
3947 Register ResultReg = createResultReg(RC); fastMaterializeAlloca() local
3983 Register ResultReg = createResultReg(TLI.getRegClassFor(VT)); fastMaterializeFloatZero() local
4041 Register ResultReg = createResultReg(RC); fastEmitInst_rrrr() local
[all...]
/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp471 Register ResultReg = selectBinaryOp() local
504 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, selectBinaryOp() local
519 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), selectBinaryOp() local
1466 Register ResultReg = getRegForValue(ConstantInt::getTrue(II->getType())); selectIntrinsicCall() local
1476 Register ResultReg = getRegForValue(II->getArgOperand(0)); selectIntrinsicCall() local
1519 Register ResultReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), selectCast() local
1549 Register ResultReg = fastEmit_r(SrcVT, DstVT, ISD::BITCAST, Op0); selectBitCast() local
1570 Register ResultReg = createResultReg(TyRegClass); selectFreeze() local
1727 Register ResultReg = fastEmit_r(VT.getSimpleVT(), VT.getSimpleVT(), ISD::FNEG, selectFNeg() local
1780 unsigned ResultReg; selectExtractValue() local
2000 Register ResultReg = fastEmit_ri(VT, VT, Opcode, Op0, Imm); fastEmit_ri_() local
2039 Register ResultReg = createResultReg(RC); fastEmitInst_() local
2050 Register ResultReg = createResultReg(RC); fastEmitInst_r() local
2072 Register ResultReg = createResultReg(RC); fastEmitInst_rr() local
2096 Register ResultReg = createResultReg(RC); fastEmitInst_rrr() local
2123 Register ResultReg = createResultReg(RC); fastEmitInst_ri() local
2146 Register ResultReg = createResultReg(RC); fastEmitInst_rii() local
2171 Register ResultReg = createResultReg(RC); fastEmitInst_f() local
2191 Register ResultReg = createResultReg(RC); fastEmitInst_rri() local
2214 Register ResultReg = createResultReg(RC); fastEmitInst_i() local
2231 Register ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); fastEmitInst_extractsubreg() local
[all...]
/llvm-project/llvm/lib/Target/ARM/
H A DARMFastISel.cpp299 Register ResultReg = createResultReg(RC); fastEmitInst_r() local
321 Register ResultReg = createResultReg(RC); fastEmitInst_rr() local
348 Register ResultReg = createResultReg(RC); fastEmitInst_ri() local
373 Register ResultReg = createResultReg(RC); fastEmitInst_i() local
488 unsigned ResultReg = 0; ARMMaterializeInt() local
658 Register ResultReg = createResultReg(RC); fastMaterializeAlloca() local
833 Register ResultReg = createResultReg(RC); ARMSimplifyAddress() local
898 ARMEmitLoad(MVT VT,Register & ResultReg,Address & Addr,MaybeAlign Alignment,bool isZExt,bool allocReg) ARMEmitLoad() argument
1033 Register ResultReg; SelectLoad() local
1562 Register ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); SelectIToFP() local
1589 Register ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); SelectFPToI() local
1655 Register ResultReg = createResultReg(RC); SelectSelect() local
1766 Register ResultReg = createResultReg(&ARM::GPRnopcRegClass); SelectBinaryIntOp() local
1815 Register ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); SelectBinaryFPOp() local
2042 Register ResultReg = createResultReg(DstRC); FinishCall() local
2063 Register ResultReg = createResultReg(DstRC); FinishCall() local
2470 Register ResultReg; ARMTryEmitSmallMemCpy() local
2706 unsigned ResultReg; ARMEmitIntExt() local
2764 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); SelectIntExt() local
2806 Register ResultReg = createResultReg(&ARM::GPRnopcRegClass); SelectShift() local
2947 Register ResultReg = MI->getOperand(0).getReg(); tryToFoldLoadIntoMI() local
3069 Register ResultReg = createResultReg(RC); fastLowerArguments() local
[all...]
H A DARMInstructionSelector.cpp690 auto ResultReg = MIB.getReg(0); in selectGlobal() local
/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyFastISel.cpp610 return ResultReg; in fastMaterializeAlloca() local
598 Register ResultReg = createResultReg(MRI.getRegClass(Reg)); copyValue() local
629 Register ResultReg = fastMaterializeConstant() local
731 Register ResultReg = createResultReg(RC); fastLowerArguments() local
786 unsigned ResultReg; selectCall() local
970 Register ResultReg = createResultReg(RC); selectSelect() local
1086 Register ResultReg = createResultReg(&WebAssembly::I32RegClass); selectICmp() local
1147 Register ResultReg = createResultReg(&WebAssembly::I32RegClass); selectFCmp() local
1240 Register ResultReg = createResultReg(RC); selectLoad() local
[all...]
/llvm-project/llvm/lib/Target/Mips/
H A DMipsFastISel.cpp340 ResultReg) in fastMaterializeAlloca() local
324 Register ResultReg = createResultReg(&Mips::GPR32RegClass); emitLogicalOp() local
361 Register ResultReg = createResultReg(RC); materialize32BitInt() local
633 emitCmp(unsigned ResultReg,const CmpInst * CI) emitCmp() argument
752 emitLoad(MVT VT,unsigned & ResultReg,Address & Addr) emitLoad() argument
861 unsigned ResultReg; selectLogicalOp() local
898 unsigned ResultReg; selectLoad() local
979 Register ResultReg = createResultReg(&Mips::GPR32RegClass); selectCmp() local
1052 Register ResultReg = createResultReg(RC); selectSelect() local
1291 Register ResultReg = createResultReg(TLI.getRegClassFor(CopyVT)); finishCall() local
1463 Register ResultReg = createResultReg(Allocation[ArgNo].RC); fastLowerArguments() local
1815 Register ResultReg = createResultReg(&Mips::GPR32RegClass); selectIntExt() local
1940 Register ResultReg = createResultReg(&Mips::GPR32RegClass); selectDivRem() local
1959 Register ResultReg = createResultReg(&Mips::GPR32RegClass); selectShift() local
2126 Register ResultReg = createResultReg(RC); fastEmitInst_rr() local
[all...]
/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp430 Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); PPCSimplifyAddress() local
448 PPCEmitLoad(MVT VT,Register & ResultReg,Address & Addr,const TargetRegisterClass * RC,bool IsZExt,unsigned FP64LoadOpc) PPCEmitLoad() argument
609 Register ResultReg = 0; SelectLoad() local
1052 Register ResultReg = 0; PPCMoveToFPReg() local
1177 Register ResultReg = 0; PPCMoveToIntReg() local
1299 Register ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass); SelectBinaryIntOp() local
1517 unsigned ResultReg = 0; finishCall() local
1929 Register ResultReg = createResultReg(RC); SelectIntExt() local
2127 Register ResultReg = createResultReg(RC); PPCMaterialize32BitInt() local
2199 Register ResultReg = createResultReg(RC); PPCMaterialize64BitInt() local
2287 Register ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); fastMaterializeAlloca() local
2366 Register ResultReg = MI->getOperand(0).getReg(); tryToFoldLoadIntoMI() local
[all...]
H A DPPCRegisterInfo.cpp593 MRI->getRegClass(ResultReg)->contains(PPC::UACC0) && in getRegAllocationHints() local
[all...]
/llvm-project/llvm/include/llvm/CodeGen/
H A DFastISel.h91 Register ResultReg; member
/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1049 Register ResultReg = I.getOperand(0).getReg(); selectFCmp() local
1637 unsigned ResultReg; // Register containing the desired result. selectMulDivRem() member
/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIInstrInfo.cpp7511 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); moveScalarAddSub() local
7628 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); lowerScalarAbs() local
8127 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); splitScalar64BitBCNT() local
8169 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); splitScalar64BitBFE() local
8193 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); splitScalar64BitBFE() local
8303 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); movePackToVALU() local
[all...]
H A DSIRegisterInfo.cpp2453 Register ResultReg = eliminateFrameIndex() local
[all...]
H A DSIISelLowering.cpp4450 emitLoadM0FromVGPRLoop(const SIInstrInfo * TII,MachineRegisterInfo & MRI,MachineBasicBlock & OrigBB,MachineBasicBlock & LoopBB,const DebugLoc & DL,const MachineOperand & Idx,unsigned InitReg,unsigned ResultReg,unsigned PhiReg,unsigned InitSaveExecReg,int Offset,bool UseGPRIdxMode,Register & SGPRIdxReg) emitLoadM0FromVGPRLoop() argument
/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DMachineIRBuilder.cpp852 for (unsigned ResultReg : ResultRegs) buildIntrinsic() local
H A DLegalizerHelper.cpp1851 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src1Reg).getReg(0); widenScalarMergeValues() local
7343 Register ResultReg = MIRBuilder.buildZExt(WideTy, Src0Reg).getReg(0); lowerMergeValues() local
/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVBuiltins.cpp1273 Register ResultReg = Call->ReturnRegister; generateKernelClockInst() local