Lines Matching defs:ResultReg
361 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);
363 ResultReg)
367 return ResultReg;
384 Register ResultReg = createResultReg(RC);
386 ResultReg).addReg(ZeroReg, getKillRegState(true));
387 return ResultReg;
420 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
422 TII.get(TargetOpcode::COPY), ResultReg)
425 return ResultReg;
438 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
439 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
442 return ResultReg;
465 unsigned ResultReg;
475 ResultReg = createResultReg(&AArch64::GPR32RegClass);
478 ResultReg = createResultReg(&AArch64::GPR64RegClass);
482 ResultReg)
487 return ResultReg;
496 .addReg(ResultReg, RegState::Kill)
529 ResultReg = createResultReg(&AArch64::GPR64spRegClass);
531 ResultReg)
537 return ResultReg;
1067 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);
1069 ResultReg)
1074 Addr.setReg(ResultReg);
1078 unsigned ResultReg = 0;
1082 ResultReg = emitAddSub_rx(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1086 ResultReg = emitAddSub_rs(/*UseAdd=*/true, MVT::i64, Addr.getReg(),
1091 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1094 ResultReg = emitLSL_ri(MVT::i64, MVT::i32, Addr.getOffsetReg(),
1097 ResultReg = emitLSL_ri(MVT::i64, MVT::i64, Addr.getOffsetReg(),
1100 if (!ResultReg)
1103 Addr.setReg(ResultReg);
1112 unsigned ResultReg;
1115 ResultReg = emitAdd_ri_(MVT::i64, Addr.getReg(), Offset);
1117 ResultReg = fastEmit_i(MVT::i64, MVT::i64, ISD::Constant, Offset);
1119 if (!ResultReg)
1121 Addr.setReg(ResultReg);
1218 unsigned ResultReg = 0;
1222 ResultReg = emitAddSub_ri(!UseAdd, RetVT, LHSReg, -Imm, SetFlags,
1225 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, Imm, SetFlags,
1229 ResultReg = emitAddSub_ri(UseAdd, RetVT, LHSReg, 0, SetFlags, WantResult);
1231 if (ResultReg)
1232 return ResultReg;
1259 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, AArch64_AM::LSL,
1261 if (ResultReg)
1262 return ResultReg;
1282 ResultReg = emitAddSub_rs(UseAdd, RetVT, LHSReg, RHSReg, ShiftType,
1284 if (ResultReg)
1285 return ResultReg;
1323 unsigned ResultReg;
1325 ResultReg = createResultReg(RC);
1327 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1332 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1335 return ResultReg;
1368 unsigned ResultReg;
1370 ResultReg = createResultReg(RC);
1372 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1376 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1380 return ResultReg;
1409 unsigned ResultReg;
1411 ResultReg = createResultReg(RC);
1413 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1418 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1422 return ResultReg;
1453 unsigned ResultReg;
1455 ResultReg = createResultReg(RC);
1457 ResultReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
1462 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
1466 return ResultReg;
1547 unsigned ResultReg;
1549 ResultReg = emitAddSub_ri(false, VT, Op0, -Imm);
1551 ResultReg = emitAddSub_ri(true, VT, Op0, Imm);
1553 if (ResultReg)
1554 return ResultReg;
1560 ResultReg = emitAddSub_rr(true, VT, Op0, CReg);
1561 return ResultReg;
1605 unsigned ResultReg = 0;
1608 ResultReg = emitLogicalOp_ri(ISDOpc, RetVT, LHSReg, Imm);
1610 if (ResultReg)
1611 return ResultReg;
1629 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1630 if (ResultReg)
1631 return ResultReg;
1643 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1644 if (ResultReg)
1645 return ResultReg;
1654 ResultReg = fastEmit_rr(VT, VT, ISDOpc, LHSReg, RHSReg);
1657 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
1659 return ResultReg;
1697 Register ResultReg =
1702 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
1704 return ResultReg;
1739 Register ResultReg =
1744 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
1746 return ResultReg;
1865 Register ResultReg = createResultReg(RC);
1867 TII.get(Opc), ResultReg);
1872 unsigned ANDReg = emitAnd_ri(MVT::i32, ResultReg, 1);
1874 ResultReg = ANDReg;
1884 .addReg(ResultReg, getKillRegState(true))
1886 ResultReg = Reg64;
1888 return ResultReg;
1899 unsigned ResultReg;
1904 ResultReg = emitAdd(VT, I->getOperand(0), I->getOperand(1));
1907 ResultReg = emitSub(VT, I->getOperand(0), I->getOperand(1));
1910 if (!ResultReg)
1913 updateValueMap(I, ResultReg);
1925 unsigned ResultReg;
1930 ResultReg = emitLogicalOp(ISD::AND, VT, I->getOperand(0), I->getOperand(1));
1933 ResultReg = emitLogicalOp(ISD::OR, VT, I->getOperand(0), I->getOperand(1));
1936 ResultReg = emitLogicalOp(ISD::XOR, VT, I->getOperand(0), I->getOperand(1));
1939 if (!ResultReg)
1942 updateValueMap(I, ResultReg);
1994 unsigned ResultReg =
1996 if (!ResultReg)
2022 ResultReg = std::prev(I)->getOperand(0).getReg();
2025 ResultReg = fastEmitInst_extractsubreg(MVT::i32, ResultReg,
2028 updateValueMap(I, ResultReg);
2049 updateValueMap(IntExtVal, ResultReg);
2053 updateValueMap(I, ResultReg);
2546 unsigned ResultReg = 0;
2551 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2553 TII.get(TargetOpcode::COPY), ResultReg)
2557 ResultReg = fastEmit_i(MVT::i32, MVT::i32, ISD::Constant, 1);
2561 if (ResultReg) {
2562 updateValueMap(I, ResultReg);
2570 ResultReg = createResultReg(&AArch64::GPR32RegClass);
2598 ResultReg)
2603 updateValueMap(I, ResultReg);
2612 ResultReg)
2617 updateValueMap(I, ResultReg);
2669 Register ResultReg = fastEmitInst_rr(Opc, &AArch64::GPR32RegClass, Src1Reg,
2671 updateValueMap(SI, ResultReg);
2790 Register ResultReg = fastEmitInst_rri(Opc, RC, Src1Reg, Src2Reg, CC);
2791 updateValueMap(I, ResultReg);
2804 Register ResultReg = createResultReg(&AArch64::FPR64RegClass);
2806 ResultReg).addReg(Op);
2807 updateValueMap(I, ResultReg);
2820 Register ResultReg = createResultReg(&AArch64::FPR32RegClass);
2822 ResultReg).addReg(Op);
2823 updateValueMap(I, ResultReg);
2853 Register ResultReg = createResultReg(
2855 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
2857 updateValueMap(I, ResultReg);
2899 Register ResultReg = fastEmitInst_r(Opc, TLI.getRegClassFor(DestVT), SrcReg);
2900 updateValueMap(I, ResultReg);
3007 Register ResultReg = createResultReg(RC);
3009 TII.get(TargetOpcode::COPY), ResultReg)
3011 updateValueMap(&Arg, ResultReg);
3119 Register ResultReg = FuncInfo.CreateRegs(CLI.RetTy);
3123 unsigned CopyReg = ResultReg + i;
3136 CLI.ResultReg = ResultReg;
3333 unsigned ResultReg = emitLoad(VT, VT, Src);
3334 if (!ResultReg)
3337 if (!emitStore(VT, ResultReg, Dest))
3477 Register ResultReg = createResultReg(&AArch64::GPR64spRegClass);
3479 TII.get(AArch64::ADDXri), ResultReg)
3484 updateValueMap(II, ResultReg);
3594 updateValueMap(II, CLI.ResultReg);
3616 Register ResultReg = createResultReg(TLI.getRegClassFor(VT));
3617 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, TII.get(Opc), ResultReg)
3619 updateValueMap(II, ResultReg);
3642 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg);
3643 if (!ResultReg)
3646 updateValueMap(II, ResultReg);
3838 Register ResultReg =
3840 updateValueMap(II, ResultReg);
3982 unsigned ResultReg;
4003 ResultReg = emitAnd_ri(MVT::i32, Reg32, Mask);
4004 assert(ResultReg && "Unexpected AND instruction emission failure.");
4006 ResultReg = createResultReg(&AArch64::GPR32RegClass);
4008 TII.get(TargetOpcode::COPY), ResultReg)
4012 updateValueMap(I, ResultReg);
4025 unsigned ResultReg = emitAnd_ri(MVT::i32, SrcReg, 1);
4026 assert(ResultReg && "Unexpected AND instruction emission failure.");
4034 .addReg(ResultReg)
4036 ResultReg = Reg64;
4038 return ResultReg;
4101 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4103 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
4104 return ResultReg;
4127 Register ResultReg = createResultReg(RC);
4129 TII.get(TargetOpcode::COPY), ResultReg)
4131 return ResultReg;
4204 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4206 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
4207 return ResultReg;
4230 Register ResultReg = createResultReg(RC);
4232 TII.get(TargetOpcode::COPY), ResultReg)
4234 return ResultReg;
4320 Register ResultReg = fastEmitInst_rr(Opc, RC, Op0Reg, Op1Reg);
4322 ResultReg = emitAnd_ri(MVT::i32, ResultReg, Mask);
4323 return ResultReg;
4346 Register ResultReg = createResultReg(RC);
4348 TII.get(TargetOpcode::COPY), ResultReg)
4350 return ResultReg;
4593 Register ResultReg = createResultReg(&AArch64::GPR64RegClass);
4595 TII.get(AArch64::SUBREG_TO_REG), ResultReg)
4599 SrcReg = ResultReg;
4607 unsigned ResultReg = emitIntExt(SrcVT, SrcReg, RetVT, IsZExt);
4608 if (!ResultReg)
4611 updateValueMap(I, ResultReg);
4651 Register ResultReg = fastEmitInst_rrr(MSubOpc, RC, QuotReg, Src1Reg, Src0Reg);
4652 updateValueMap(I, ResultReg);
4700 unsigned ResultReg =
4703 if (ResultReg) {
4704 updateValueMap(I, ResultReg);
4717 unsigned ResultReg = emitMul_rr(VT, Src0Reg, Src1Reg);
4719 if (!ResultReg)
4722 updateValueMap(I, ResultReg);
4735 unsigned ResultReg = 0;
4767 ResultReg = emitLSL_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4770 ResultReg = emitASR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4773 ResultReg = emitLSR_ri(RetVT, SrcVT, Op0Reg, ShiftVal, IsZExt);
4776 if (!ResultReg)
4779 updateValueMap(I, ResultReg);
4791 unsigned ResultReg = 0;
4795 ResultReg = emitLSL_rr(RetVT, Op0Reg, Op1Reg);
4798 ResultReg = emitASR_rr(RetVT, Op0Reg, Op1Reg);
4801 ResultReg = emitLSR_rr(RetVT, Op0Reg, Op1Reg);
4805 if (!ResultReg)
4808 updateValueMap(I, ResultReg);
4844 Register ResultReg = fastEmitInst_r(Opc, RC, Op0Reg);
4845 if (!ResultReg)
4848 updateValueMap(I, ResultReg);
4886 updateValueMap(I, CLI.ResultReg);
4909 unsigned ResultReg = emitASR_ri(VT, VT, Src0Reg, Lg2);
4910 if (!ResultReg)
4912 updateValueMap(I, ResultReg);
4942 unsigned ResultReg;
4944 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg,
4947 ResultReg = emitASR_ri(VT, VT, SelectReg, Lg2);
4949 if (!ResultReg)
4952 updateValueMap(I, ResultReg);