[CodeGen] Use Register/MCRegister::isPhysical. NFC

CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119487)

This reapplies #119122 with a fix for UBSAN errors in the X86 backend
related
to incrementing a nullptr.

Revert "CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)"

Reverting due to UBSan failures in X86RegisterInfo::getLargestLegalSuperClass

This reverts commit c48738

Revert "CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)"

Reverting due to UBSan failures in X86RegisterInfo::getLargestLegalSuperClass

This reverts commit c4873819a98f59ce4e2664f94c73c2dfec3393f8.

show more ...

CodeGen: Eliminate dynamic relocations in the register superclass tables. (#119122)

[PowerPC] Remove unused includes (NFC) (#116163)

Identified with misc-include-cleaner.

[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)

This patch utilizes getReservedRegs() to find asm clobberable registers.
And to make the result of getReservedRegs() a

[PowerPC] Utilize getReservedRegs to find asm clobberable registers. (#107863)

This patch utilizes getReservedRegs() to find asm clobberable registers.
And to make the result of getReservedRegs() accurate, this patch
implements the todo, which is to make r2 allocatable on AIX for some
leaf functions.

show more ...

[PowerPC] option `-msoft-float` should not block the PC-relative address instruction (#92543)

The Prefix instruction is introduced on PowerPC ISA3_1.

In the PR,
1. The `FeaturePrefixInstrs` do

[PowerPC] option `-msoft-float` should not block the PC-relative address instruction (#92543)

The Prefix instruction is introduced on PowerPC ISA3_1.

In the PR,
1. The `FeaturePrefixInstrs` do not imply the `FeatureP8Vector`
,`FeatureP9Vector` .
2. `FeaturePrefixInstrs` implies only the FeatureISA3_1.
3. For the prefix instructions `paddi` and `pli` , they have `Predicates
= [PrefixInstrs] `
4. For the prefix instructions `plfs` and `plfd`, they have `Predicates
= [PrefixInstrs, HasFPU] `
5. For the prefix instructions "plxv` , "plxssp` and `plxsd` , they have
`Predicates = [PrefixInstrs, HasP10Vector]`

Fixes #62372

show more ...

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many

[CodeGen] Make the parameter TRI required in some functions. (#85968)

Fixes #82659

There are some functions, such as `findRegisterDefOperandIdx` and `findRegisterDefOperand`, that have too many default parameters. As a result, we have encountered some issues due to the lack of TRI parameters, as shown in issue #82411.

Following @RKSimon 's suggestion, this patch refactors 9 functions, including `{reads, kills, defines, modifies}Register`, `registerDefIsDead`, and `findRegister{UseOperandIdx, UseOperand, DefOperandIdx, DefOperand}`, adjusting the order of the TRI parameter and making it required. In addition, all the places that call these functions have also been updated correctly to ensure no additional impact.

After this, the caller of these functions should explicitly know whether to pass the `TargetRegisterInfo` or just a `nullptr`.

show more ...

[NFC] Rename TargetInstrInfo::FoldImmediate to TargetInstrInfo::foldImmediate and simplify implementation for X86

[CodeGen][Target] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC

Use isPhysical/isVirtual methods.

[PowerPC] Add handling for WACC register spilling.

This patch adds spilling for the new WACC registers.

In order to get the spilling test to work the MMA instructions from Power 10 are
now supporte

[PowerPC] Add handling for WACC register spilling.

This patch adds spilling for the new WACC registers.

In order to get the spilling test to work the MMA instructions from Power 10 are
now supported for Future CPU except that they are all using the new WACC
registers instead of the ACC registers from Power 10.

Reviewed By: amyk, saghir

Differential Revision: https://reviews.llvm.org/D136728

show more ...

PEI should be able to use backward walk in replaceFrameIndicesBackward.

The backward register scavenger has correct register
liveness information. PEI should leverage the backward register scavenger

PEI should be able to use backward walk in replaceFrameIndicesBackward.

The backward register scavenger has correct register
liveness information. PEI should leverage the backward register scavenger.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D137574

show more ...

[PowerPC] Stash GPR to VSR if emergency spill slot is not reachable

When removing frame indices on PowerPC, we need to scavenge
a GPR to materialize a large constant if the stack offset
for the spil

[PowerPC] Stash GPR to VSR if emergency spill slot is not reachable

When removing frame indices on PowerPC, we need to scavenge
a GPR to materialize a large constant if the stack offset
for the spill/reload cannot be reached by a D-Form
instruction. However, in a perfect storm of conditions,
we may not have GPR's available to scavenge, thereby
requiring an emergency spill. If such an emergency
spill also needs to be spilled to a location with a
large offset, it would itself require register scavenging
thereby creating an infinite loop.

This patch detects when the scavenger cannot scavenge
a register and the spill/reload is to a location with
a large offset. It then stashes a GPR into a VSR so
that it can use the GPR to materialize the constant
(rather than scavenging a GPR).

Fixes: https://github.com/llvm/llvm-project/issues/52894

Differential revision: https://reviews.llvm.org/D124841

show more ...

[PowerPC] Add vector pair calling convention for AIX

This is AIX part of update after https://reviews.llvm.org/D117225

Fixed the issue that AIX64 with vector pair enabled saw redundant
spill/reload

[PowerPC] Add vector pair calling convention for AIX

This is AIX part of update after https://reviews.llvm.org/D117225

Fixed the issue that AIX64 with vector pair enabled saw redundant
spill/reload of callee saved vector registers.

Based on original patch by: Kai Luo

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D133466

show more ...

[PowerPC] Fix the register allocation hints for ACC registers.

The allocation hints for copies of ACC registers assumed that we would only be
copying between VSRp and UACC registers. In reality it i

[PowerPC] Fix the register allocation hints for ACC registers.

The allocation hints for copies of ACC registers assumed that we would only be
copying between VSRp and UACC registers. In reality it is also possible to copy
between UACC and ACC registers.

This patch adds a new case for the ACC copy to fix that issue.
Note that the test case added with this patch will hit an assert without the
fix.

Reviewed By: lei, amyk

Differential Revision: https://reviews.llvm.org/D134501

show more ...

[llvm] Use range-based for loops (NFC)

[PowerPC] Don't use the S30 and S31 regs for the pic code

These changes to address issue
https://github.com/llvm/llvm-project/issues/55857.

Since R30/S30 is used as pointer (32 bits) for GOT Table

[PowerPC] Don't use the S30 and S31 regs for the pic code

These changes to address issue
https://github.com/llvm/llvm-project/issues/55857.

Since R30/S30 is used as pointer (32 bits) for GOT Table in the ppc32 ABI,
remove it from the SPE callee save register when PIC is enabled.

This prevents emitting the SPE load and store for S30 and S31 regs.

Differential revision: https://reviews.llvm.org/D127495

show more ...

[PowerPC] Disable automatic generation of STXVP

There are instances where using paired vector stores leads to significant
performance degradation due to issues with store forwarding.To avoid falling

[PowerPC] Disable automatic generation of STXVP

There are instances where using paired vector stores leads to significant
performance degradation due to issues with store forwarding.To avoid falling
into this trap with compiler - generated code, we will not emit these
instructions unless the user requests them explicitly(with a builtin or by
specifying the option).

Reviewed By : lei, amyk, saghir

Differential Revision: https://reviews.llvm.org/D127218

show more ...

[PowerPC] Fix LQ-STQ instructions to use correct offset and base

This patch fixes the load and store quadword instructions on
PowerPC to use correct offset and base address.

Reviewed By: #powerpc,

[PowerPC] Fix LQ-STQ instructions to use correct offset and base

This patch fixes the load and store quadword instructions on
PowerPC to use correct offset and base address.

Reviewed By: #powerpc, nemanjai, lkail

Differential Revision: https://reviews.llvm.org/D126807

show more ...

[PowerPC] Support huge frame size for PPC64

Support allocation of huge stack frame(>2g) on PPC64.

For ELFv2 ABI on Linux, quoted from the spec 2.2.3.1 General Stack Frame Requirements
> There is no

[PowerPC] Support huge frame size for PPC64

Support allocation of huge stack frame(>2g) on PPC64.

For ELFv2 ABI on Linux, quoted from the spec 2.2.3.1 General Stack Frame Requirements
> There is no maximum stack frame size defined.

On AIX, XL allows such huge frame.

Reviewed By: #powerpc, nemanjai

Differential Revision: https://reviews.llvm.org/D107886

show more ...

[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments

Cleanup codegen includes

This is a (fixed) recommit of https://reviews.llvm.org/D121169

after: 1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-in

Cleanup codegen includes

This is a (fixed) recommit of https://reviews.llvm.org/D121169

after: 1061034926
before: 1063332844

Discourse thread: https://discourse.llvm.org/t/include-what-you-use-include-cleanup
Differential Revision: https://reviews.llvm.org/D121681

show more ...

[PowerPC][P10] Add Vector pair calling convention

Add the calling convention for the vector pair registers.
These registers overlap with the vector registers.

Part of an original patch by: Lei Huan

[PowerPC][P10] Add Vector pair calling convention

Add the calling convention for the vector pair registers.
These registers overlap with the vector registers.

Part of an original patch by: Lei Huang

Reviewed By: nemanjai, #powerpc

Differential Revision: https://reviews.llvm.org/D117225

show more ...

Revert "Cleanup codegen includes"

This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https:/

Revert "Cleanup codegen includes"

This reverts commit 7f230feeeac8a67b335f52bd2e900a05c6098f20.
Breaks CodeGenCUDA/link-device-bitcode.cu in check-clang,
and many LLVM tests, see comments on https://reviews.llvm.org/D121169

show more ...

Cleanup codegen includes

after: 1061034926
before: 1063332844

Differential Revision: https://reviews.llvm.org/D121169