| #
4512d0a6 |
| 17-Nov-2017 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Replace list of SMEM buffer opcodes
llvm-svn: 318506
|
| #
03c67d1e |
| 17-Nov-2017 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Fix breaking SMEM clauses
This was completely ignoring subregisters,
so was not very useful. Also only break them
if xnack is actually enabled.
llvm-svn: 318505
|
|
Revision tags: llvmorg-5.0.1-rc1 |
|
| #
22322438 |
| 26-Oct-2017 |
Marek Olsak <marek.olsak@amd.com> |
AMDGPU: Handle s_buffer_load_dword hazard on SI
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org
AMDGPU: Handle s_buffer_load_dword hazard on SI
Reviewers: arsenm, nhaehnle
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D39171
llvm-svn: 316666
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|
| #
52382714 |
| 06-Sep-2017 |
Nicolai Haehnle <nhaehnle@gmail.com> |
AMDGPU: Make worst-case assumption about the wait states in inline assembly
Summary:
Mesa still uses a hack where empty inline assembly is used as a kind of
optimization barrier. This exposed a prob
AMDGPU: Make worst-case assumption about the wait states in inline assembly
Summary:
Mesa still uses a hack where empty inline assembly is used as a kind of
optimization barrier. This exposed a problem where not enough wait states
were inserted, because the hazard recognizer implicitly assumed that each
inline assembly "instruction" has at least one wait state.
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, llvm-commits, t-tye
Differential Revision: https://reviews.llvm.org/D37205
llvm-svn: 312635
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|
| #
75c98c36 |
| 01-Sep-2017 |
Nicolai Haehnle <nhaehnle@gmail.com> |
AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states
Summary:
This fixes a bug that was exposed on gfx9 in various
GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragmen
AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states
Summary:
This fixes a bug that was exposed on gfx9 in various
GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests,
e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment
Reviewers: arsenm
Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D36193
llvm-svn: 312337
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|
|
Revision tags: llvmorg-5.0.0, llvmorg-5.0.0-rc5, llvmorg-5.0.0-rc4, llvmorg-5.0.0-rc3, llvmorg-5.0.0-rc2 |
|
| #
00755362 |
| 04-Aug-2017 |
Connor Abbott <cwabbott0@gmail.com> |
[AMDGPU] Add missing hazard for DPP-after-EXEC-write
Summary:
Following the docs, we need at least 5 wait states between an EXEC write
and an instruction that uses DPP.
Reviewers: tstellar, arsenm
[AMDGPU] Add missing hazard for DPP-after-EXEC-write
Summary:
Following the docs, we need at least 5 wait states between an EXEC write
and an instruction that uses DPP.
Reviewers: tstellar, arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D34849
llvm-svn: 310013
show more ...
|
|
Revision tags: llvmorg-5.0.0-rc1, llvmorg-4.0.1, llvmorg-4.0.1-rc3 |
|
| #
6bda14b3 |
| 06-Jun-2017 |
Chandler Carruth <chandlerc@gmail.com> |
Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line
Sort the remaining #include lines in include/... and lib/....
I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.
I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.
This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.
Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).
llvm-svn: 304787
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|
|
Revision tags: llvmorg-4.0.1-rc2, llvmorg-4.0.1-rc1 |
|
| #
59ece95f |
| 17-Mar-2017 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Fix broken condition in hazard recognizer
Fixes bug 32248.
llvm-svn: 298125
|
| #
6778b8f7 |
| 15-Mar-2017 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
Reverted unintended commit
llvm-svn: 297841
|
| #
3804a12f |
| 15-Mar-2017 |
Simon Pilgrim <llvm-dev@redking.me.uk> |
Fix Wint-in-bool-context warning (PR32248)
llvm-svn: 297840
|
|
Revision tags: llvmorg-4.0.0, llvmorg-4.0.0-rc4, llvmorg-4.0.0-rc3 |
|
| #
e823d92f |
| 18-Feb-2017 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Merge initial gfx9 support
llvm-svn: 295554
|
|
Revision tags: llvmorg-4.0.0-rc2 |
|
| #
734bb7bb |
| 20-Jan-2017 |
Eugene Zelenko <eugene.zelenko@gmail.com> |
[AMDGPU] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 292623
|
|
Revision tags: llvmorg-4.0.0-rc1, llvmorg-3.9.1, llvmorg-3.9.1-rc3, llvmorg-3.9.1-rc2 |
|
| #
97279a8c |
| 29-Nov-2016 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Rename flat operands to match mubuf
Use vaddr/vdst for the same purposes.
This also fixes a beg in SIInsertWaits for the
operand check. The stored value operand is currently called
data0 in
AMDGPU: Rename flat operands to match mubuf
Use vaddr/vdst for the same purposes.
This also fixes a beg in SIInsertWaits for the
operand check. The stored value operand is currently called
data0 in the single offset case, not data.
llvm-svn: 288188
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|
|
Revision tags: llvmorg-3.9.1-rc1 |
|
| #
e8cc395e |
| 15-Nov-2016 |
Jan Vesely <jan.vesely@rutgers.edu> |
AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument
wbinvl.* are vector instruction that do not sue vector registers.
v2: check only M?BUF instructions
Differential Revision:
AMDGPU/GCN: Exit early in hazard recognizer if there is no vreg argument
wbinvl.* are vector instruction that do not sue vector registers.
v2: check only M?BUF instructions
Differential Revision: https://reviews.llvm.org/D26633
llvm-svn: 287056
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|
| #
aea899e2 |
| 27-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Handle hazard with s_rfe_b64
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25638
llvm-svn: 28
AMDGPU/SI: Handle hazard with s_rfe_b64
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25638
llvm-svn: 285368
show more ...
|
| #
04051b5f |
| 27-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://review
AMDGPU/SI: Handle hazard with sgpr lane selects for v_{read,write}lane
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25637
llvm-svn: 285367
show more ...
|
| #
6b9c1be4 |
| 27-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Fix unused variable warning on non-debug builds
llvm-svn: 285363
|
| #
b133fbb9 |
| 27-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Handle hazard with > 8 byte VMEM stores
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25577
l
AMDGPU/SI: Handle hazard with > 8 byte VMEM stores
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25577
llvm-svn: 285359
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|
| #
30d30824 |
| 27-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25
AMDGPU/SI: Handle s_setreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25528
llvm-svn: 285338
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|
| #
961811c9 |
| 15-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25
AMDGPU/SI: Handle s_getreg hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, llvm-commits, tony-tye
Differential Revision: https://reviews.llvm.org/D25526
llvm-svn: 284298
show more ...
|
| #
5ab6154d |
| 07-Oct-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25
AMDGPU/SI: Handle div_fmas hazard in GCNHazardRecognizer
Reviewers: arsenm
Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits
Differential Revision: https://reviews.llvm.org/D25250
llvm-svn: 283622
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|
|
Revision tags: llvmorg-3.9.0, llvmorg-3.9.0-rc3, llvmorg-3.9.0-rc2, llvmorg-3.9.0-rc1 |
|
| #
43e92fe3 |
| 24-Jun-2016 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
AMDGPU: Cleanup subtarget handling.
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict
AMDGPU: Cleanup subtarget handling.
Split AMDGPUSubtarget into amdgcn/r600 specific subclasses.
This removes most of the static_casting of the basic codegen
classes everywhere, and tries to restrict the features
visible on the wrong target.
llvm-svn: 273652
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|
| #
d3f4c05a |
| 12-Jun-2016 |
Benjamin Kramer <benny.kra@googlemail.com> |
Move instances of std::function.
Or replace with llvm::function_ref if it's never stored. NFC intended.
llvm-svn: 272513
|
|
Revision tags: llvmorg-3.8.1, llvmorg-3.8.1-rc1 |
|
| #
3bd56b3b |
| 03-May-2016 |
Aaron Ballman <aaron@aaronballman.com> |
Silence unused variable warning; NFC.
llvm-svn: 268392
|
| #
1f520e5c |
| 02-May-2016 |
Tom Stellard <thomas.stellard@amd.com> |
AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
Summary:
Add support for detecting hazards in SMEM soft clauses, so that we only
break the clauses when necessary, either by adding s_
AMDGPU/SI: Use the hazard recognizer to break SMEM soft clauses
Summary:
Add support for detecting hazards in SMEM soft clauses, so that we only
break the clauses when necessary, either by adding s_nop or re-ordering
other alu instructions.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D18870
llvm-svn: 268260
show more ...
|