[TargetLowering] Inline the only caller of one of the forceExpandWideMUL functions. NFC

This caller does not need the libcall portion so it can directly
call forceExpandMultiply.

[TargetLowering] Pull similar code out of the forceExpandWideMUL into a helper. NFC (#124371)

These functions have similar code. One of them calculates the 2x width
full product from 2 sources. The

[TargetLowering] Pull similar code out of the forceExpandWideMUL into a helper. NFC (#124371)

These functions have similar code. One of them calculates the 2x width
full product from 2 sources. The other calculates the product from 2
sources that have low and high halves.

This patch introduces a new function that takes HiLHS and HiRHS as
optional values. If they are not null, they will be used in the
calculation of the Hi half. The Signed flag can only be set when
HiLHS/HiRHS are null.

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[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

We have two forceExpandWideMUL functions. One takes the low and high
half of 2 inputs and calculates the low and high half of

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

We have two forceExpandWideMUL functions. One takes the low and high
half of 2 inputs and calculates the low and high half of their product.
This does not calculate the full 2x width product.

The other signature takes 2 inputs and calculates the low and high half
of their full 2x width product. Previously it did this by sign/zero
extending the inputs to create the high bits and then calling the other
function.

We can instead copy the algorithm from the other function and use the
Signed flag to determine whether we should do SRA or SRL. This avoids
the need to multiply the high part of the inputs and add them to the
high half of the result. This improves the generated code for signed
multiplication.

This should improve the performance of #123262. I don't know yet how
close we will get to gcc.

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[TargetLowering] Use getShiftAmountConstant. NFC (#123802)

Previously we always used the pointer size which might need to be
legalized on some targets.

[SDAG] Add an ISD node to help lower vector.extract.last.active (#118810)

Based on feedback from the clastb codegen PR, I'm refactoring basic codegen for the vector.extract.last.active intrinsic to

[SDAG] Add an ISD node to help lower vector.extract.last.active (#118810)

Based on feedback from the clastb codegen PR, I'm refactoring basic codegen for the vector.extract.last.active intrinsic to lower to an ISD node in SelectionDAGBuilder then expand in LegalizeVectorOps, instead of doing everything in the builder.

The new ISD node (vector_find_last_active) only covers finding the index of the last active element of the mask, and extracting the element + handling passthru is left to existing ISD nodes.

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[SelectionDAG] Use SDNode::op_iterator instead of SDNodeIterator. NFC (#122147)

I think SDNodeIterator primarily exists because GraphTraits requires an
iterator that dereferences to SDNode*. op_ite

[SelectionDAG] Use SDNode::op_iterator instead of SDNodeIterator. NFC (#122147)

I think SDNodeIterator primarily exists because GraphTraits requires an
iterator that dereferences to SDNode*. op_iterator dereferences to
SDUse* which is implicitly convertible to SDValue.

This piece of code can use SDValue instead of SDNode* so we should
prefer to use the the more common op_iterator.

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[DAG] expandUINT_TO_FP - use getShiftAmountConstant helper. NFC.

Don't bother with separate getShiftAmountTy/getConstant calls.

[NVPTX] Fix lowering of i1 SETCC (#115035)

Add DAG legalization support for expanding i1 SETCC nodes using
appropriate logical operations to simulate integer comparisons. Use
these expansions to han

[NVPTX] Fix lowering of i1 SETCC (#115035)

Add DAG legalization support for expanding i1 SETCC nodes using
appropriate logical operations to simulate integer comparisons. Use
these expansions to handle i1 SETCC in NVPTX.

fixes #58428 and #57405

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[DAG] SimplifyDemandedVectorElts - add handling for INT<->FP conversions (#117884)

[TargetLowering] Use Type* instead of EVT in shouldSignExtendTypeInLibCall. (#118587)

I want to use this function for GISel too so Type * is a better common
interface. All of the callers already co

[TargetLowering] Use Type* instead of EVT in shouldSignExtendTypeInLibCall. (#118587)

I want to use this function for GISel too so Type * is a better common
interface. All of the callers already convert EVT to Type * as needed
by calling lowering anyway.

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[SelectionDAG] Rename CallOptions::IsSExt to IsSigned. NFC (#118574)

This is eventually passed to shouldSignExtendTypeInLibCall which calls
it IsSigned.

[Clang] Attribute NoFPClass should not prevent tail call optimization. (#116741)

Fixes #111950

[DAG] SimplifyDemandedVectorElts - add SimplifyMultipleUse handling to SEXT/ZEXT/TRUNC nodes (#116227)

Allows us to bypass multiple uses of a SEXT/ZEXT/TRUNC node operand

[TargetLowering] Use Correct VT for Multi-out Asm (#116024)

This was overlooked in 7d940432c46be83b8fcb5dbefee439585fa820cd - when
inline assembly has multiple outputs, they are returned as members

[TargetLowering] Use Correct VT for Multi-out Asm (#116024)

This was overlooked in 7d940432c46be83b8fcb5dbefee439585fa820cd - when
inline assembly has multiple outputs, they are returned as members of a
struct, and the `getAsmOperandType` needs to be called for each member
of struct. The difference between this and the single-output case is
that in the latter, there isn't a struct wrapping the outputs.

I noticed this when trying to use the same mechanism in the RISC-V
backend.

Committing two tests:
- One that shows a crash before this change, which is fixed by this
change.
- One (commented out) that shows a different crash with tied
inputs/outputs. This is commented as it is not fixed by this change and
needs more work in target-independent inline asm handling code.

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[SelectionDAG] Fixup type usage of CondCodeAction table (#116082)

Ensure that all uses of CondCodeAction table are checking the compared
types, not the produced type. This is a prerequisite to land

[SelectionDAG] Fixup type usage of CondCodeAction table (#116082)

Ensure that all uses of CondCodeAction table are checking the compared
types, not the produced type. This is a prerequisite to landing #115035

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[DAGCombiner] Add basic support for `trunc nsw/nuw` (#113808)

This patch adds basic support for `trunc nsw/nuw` in SDAG. It will allow
DAGCombiner to further eliminate in-reg `zext/sext` instructio

[DAGCombiner] Add basic support for `trunc nsw/nuw` (#113808)

This patch adds basic support for `trunc nsw/nuw` in SDAG. It will allow
DAGCombiner to further eliminate in-reg `zext/sext` instructions.

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[DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (#112588)

The dpbusd_const.ll test change is due to us losing the expanded add reduction pattern as one of the elem

[DAG] SimplifyMultipleUseDemandedBits - bypass ADD nodes if either operand is zero (#112588)

The dpbusd_const.ll test change is due to us losing the expanded add reduction pattern as one of the elements is known to be zero (removing one of the adds from the reduction pyramid). I don't think its of concern.

Noticed while working on #107423

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[DAG] SimplifyDemandedBits - ignore SRL node if we're just demanding known sign bits (#114805)

Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the

[DAG] SimplifyDemandedBits - ignore SRL node if we're just demanding known sign bits (#114805)

Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the source node.

We can't demand any upper zero bits that the SRL will shift in (up to max shift amount), and the lower demanded bits bound must already be all signbits.

Same fold as #114389 which added this for SimplifyMultipleUseDemandedBits

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[ISel] Propagate disjoint flag in ShrinkDemandedOp (#114560)

When trying to evaluate an expression in a narrower type, the
DAGCombine should propagate the disjoint flag, as it's equally
valid on t

[ISel] Propagate disjoint flag in ShrinkDemandedOp (#114560)

When trying to evaluate an expression in a narrower type, the
DAGCombine should propagate the disjoint flag, as it's equally
valid on the narrower expression.

This helps improve better use of addressing modes for some
Arm SME instructions, for example.

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[SelectionDAG] Remove unused includes (NFC) (#114697)

Identified with misc-include-cleaner.

[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)

Check to see if we are only demanding (shifted) signbits from a SRL node that are also signb

[DAG] SimplifyMultipleUseDemandedBits - ignore SRL node if we're just demanding known sign bits (#114389)

Check to see if we are only demanding (shifted) signbits from a SRL node that are also signbits in the source node.

We can't demand any upper zero bits that the SRL will shift in (up to max shift amount), and the lower demanded bits bound must already be all signbits.

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[SelectionDAG] Fix a warning

This patch fixes:

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1489:17: error:
unused variable 'Flags' [-Werror,-Wunused-variable]

[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)

This patch allows using enumeration values directly and simplifies the
implementation with bitwise logic. It addresses the comment in
htt

[SDAG] Simplify `SDNodeFlags` with bitwise logic (#114061)

This patch allows using enumeration values directly and simplifies the
implementation with bitwise logic. It addresses the comment in
https://github.com/llvm/llvm-project/pull/113808#discussion_r1819923625.

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DAG: Lower fcNormal is.fpclass to compare with inf (#100389)

[APInt] Fix APInt constructions where value does not fit bitwidth (NFCI) (#80309)

This fixes all the places that hit the new assertion added in
https://github.com/llvm/llvm-project/pull/106524 in t

[APInt] Fix APInt constructions where value does not fit bitwidth (NFCI) (#80309)

This fixes all the places that hit the new assertion added in
https://github.com/llvm/llvm-project/pull/106524 in tests. That is,
cases where the value passed to the APInt constructor is not an N-bit
signed/unsigned integer, where N is the bit width and signedness is
determined by the isSigned flag.

The fixes either set the correct value for isSigned, set the
implicitTrunc flag, or perform more calculations inside APInt.

Note that the assertion is currently still disabled by default, so this
patch is mostly NFC.

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