Home
last modified time | relevance | path

Searched refs:engine (Results 1 – 25 of 31) sorted by relevance

12

/dpdk/drivers/regex/mlx5/
H A Dmlx5_regex_devx.c16 mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey, in mlx5_devx_regex_rules_program() argument
24 MLX5_SET(set_regexp_params_in, in, engine_id, engine); in mlx5_devx_regex_rules_program()
H A Dmlx5_regex.h83 int mlx5_devx_regex_rules_program(void *ctx, uint8_t engine, uint32_t rof_mkey,
/dpdk/doc/guides/dmadevs/
H A Dcnxk.rst86 CNXK supports 6 DMA engines and each engine has an associated FIFO.
87 By default, all engine's FIFO is configured to 8 KB.
89 where each byte represents an engine.
90 In the example above, engine 0-3 FIFO are configure as 8 KB
91 and engine 4-5 are configured as 16 KB.
H A Dodm.rst76 Each queue would be associated with one engine.
77 If the value of the bit corresponding to the queue is 0, then engine 0 would be picked.
78 If it is 1, then engine 1 would be picked.
H A Didxd.rst61 To assign an engine to a group::
63 $ accel-config config-engine dsa0/engine0.0 --group-id=0
94 # configure 4 groups, each with one engine
95 accel-config config-engine dsa0/engine0.0 --group-id=0
96 accel-config config-engine dsa0/engine0.1 --group-id=1
97 accel-config config-engine dsa0/engine0.2 --group-id=2
98 accel-config config-engine dsa0/engine0.3 --group-id=3
101 # is backed by a single engine
/dpdk/doc/guides/cryptodevs/
H A Dcaam_jr.rst16 SEC is the SOC's security engine, which serves as NXP's latest cryptographic
19 and assurance engine. It also implements block encryption algorithms, stream
40 engine provides a scatter/gather capability so that SEC can read and write
H A Ddpaa_sec.rst15 SEC is the SOC's security engine, which serves as NXP's latest cryptographic
18 and assurance engine. It also implements block encryption algorithms, stream
42 engine provides a scatter/gather capability so that SEC can read and write
H A Ddpaa2_sec.rst15 SEC is the SOC's security engine, which serves as NXP's latest cryptographic
18 and assurance engine. It also implements block encryption algorithms, stream
58 engine provides a scatter/gather capability so that SEC can read and write
H A Dcnxk.rst138 higher performance as even VF uses one crypto engine and odd one uses
139 another crypto engine.
/dpdk/doc/guides/rel_notes/
H A Drelease_24_03.rst108 * Added support for GENEVE matching and modifying in HWS flow engine.
109 * Added support for modifying IPv4 proto field in HWS flow engine.
110 * Added support for modifying IPsec ESP fields in HWS flow engine.
111 * Added support for modifying IPv6 traffic class field in HWS flow engine.
112 * Added support for modifying IPv6 flow label field in HWS flow engine.
116 * Added support for copying inner fields in HWS flow engine.
117 * Added support for ``RTE_FLOW_ACTION_TYPE_NAT64`` flow action in HWS flow engine.
120 in HWS flow engine.
H A Drelease_19_11.rst83 Subsystem 3 (HNS3) network engine found in the Hisilicon Kunpeng 920 SoC.
163 * Flow engine selected based on RDMA Core library version.
164 DV flow engine selected if version is rdma-core-24.0 or higher.
165 Verbs flow engine selected otherwise.
H A Drelease_22_03.rst29 * **Added functions to configure the flow engine.**
32 engine, allowing preallocation of some resources for better performance.
H A Drelease_21_08.rst76 the DMA engine in the vhost async data path.
/dpdk/drivers/crypto/ccp/
H A Dccp_crypto.c691 sess->cipher.engine = CCP_ENGINE_AES; in ccp_configure_session_cipher()
696 sess->cipher.engine = CCP_ENGINE_AES; in ccp_configure_session_cipher()
701 sess->cipher.engine = CCP_ENGINE_AES; in ccp_configure_session_cipher()
706 sess->cipher.engine = CCP_ENGINE_3DES; in ccp_configure_session_cipher()
714 switch (sess->cipher.engine) { in ccp_configure_session_cipher()
782 sess->auth.engine = CCP_ENGINE_SHA; in ccp_configure_session_auth()
803 sess->auth.engine = CCP_ENGINE_SHA; in ccp_configure_session_auth()
821 sess->auth.engine = CCP_ENGINE_SHA; in ccp_configure_session_auth()
842 sess->auth.engine = CCP_ENGINE_SHA; in ccp_configure_session_auth()
859 sess->auth.engine = CCP_ENGINE_SHA; in ccp_configure_session_auth()
[all …]
H A Dccp_crypto.h260 enum ccp_engine engine; member
284 enum ccp_engine engine; member
H A Dccp_dev.h100 #define CCP_CMD_ENGINE(p) (CCP_CMD_DW0(p).engine)
379 uint32_t engine:4; member
/dpdk/doc/guides/regexdevs/
H A Dmlx5.rst23 This PMD is configuring the RegEx HW engine.
/dpdk/drivers/net/qede/
H A Dqede_regs.c65 qede_calc_regdump_header(enum debug_print_features feature, int engine, in qede_calc_regdump_header() argument
73 (engine << REGDUMP_HEADER_ENGINE_SHIFT)); in qede_calc_regdump_header()
/dpdk/doc/guides/nics/
H A Dpfe.rst28 PFE is a hardware programmable packet forwarding engine to provide
77 to send and receive packets through packet forwarding engine. Both network
H A Denetfec.rst33 ENETFEC PMD is a hardware programmable packet forwarding engine
/dpdk/doc/guides/howto/
H A Dvirtio_user_for_container_networking.rst56 Here we use Docker as container engine. It also applies to LXC, Rocket with
/dpdk/app/test/
H A Dtest_compressdev.c1438 char engine[] = "zlib (directly, not PMD)"; in test_deflate_comp_finalize() local
1440 strlcpy(engine, "PMD", sizeof(engine)); in test_deflate_comp_finalize()
1444 i, engine, in test_deflate_comp_finalize()
1762 char engine[] = "zlib, (directly, no PMD)"; in test_deflate_decomp_finalize() local
1764 strlcpy(engine, "pmd", sizeof(engine)); in test_deflate_decomp_finalize()
1767 i, engine, in test_deflate_decomp_finalize()
/dpdk/doc/guides/bbdevs/
H A Dvrb2.rst85 - ``RTE_BBDEV_TURBO_MAP_DEC``: supports flexible parallel MAP engine decoding.
/dpdk/doc/guides/rawdevs/
H A Difpga.rst251 single context, because it only has one PR engine, and one PR region which
/dpdk/examples/l3fwd/
H A Dl3fwd_em.c259 #error No vector engine (SSE, NEON, ALTIVEC) available, check your toolchain

12