xref: /dpdk/doc/guides/bbdevs/vrb2.rst (revision 22900d7fd65ec30a47d7f6d5906bb46b6112b507)
1.. SPDX-License-Identifier: BSD-3-Clause
2   Copyright(c) 2023 Intel Corporation
3
4.. include:: <isonum.txt>
5
6Intel\ |reg| vRAN Boost v2 Poll Mode Driver (PMD)
7=================================================
8
9The Intel\ |reg| vRAN Boost integrated accelerator enables
10cost-effective 4G and 5G next-generation virtualized Radio Access Network (vRAN)
11solutions.
12The Intel vRAN Boost v2.0 (VRB2 in the code) is specifically integrated on the
13Intel\ |reg| Xeon\ |reg| Granite Rapids-D Process (GNR-D).
14
15Features
16--------
17
18Intel vRAN Boost v2.0 includes a 5G Low Density Parity Check (LDPC) encoder/decoder,
19rate match/dematch, Hybrid Automatic Repeat Request (HARQ) with access to DDR
20memory for buffer management, a 4G Turbo encoder/decoder,
21a Fast Fourier Transform (FFT) block providing DFT/iDFT processing offload
22for the 5G Sounding Reference Signal (SRS), a MLD-TS accelerator, a Queue Manager (QMGR),
23and a DMA subsystem.
24There is no dedicated on-card memory for HARQ, the coherent memory on the CPU side is being used.
25
26These hardware blocks provide the following features exposed by the PMD:
27
28- LDPC Encode in the Downlink (5GNR)
29- LDPC Decode in the Uplink (5GNR)
30- Turbo Encode in the Downlink (4G)
31- Turbo Decode in the Uplink (4G)
32- FFT processing
33- MLD-TS processing
34- Single Root I/O Virtualization (SR-IOV) with 16 Virtual Functions (VFs) per Physical Function (PF)
35- Maximum of 2048 queues per VF
36- Message Signaled Interrupts (MSIs)
37
38The Intel vRAN Boost v2.0 PMD supports the following bbdev capabilities:
39
40* For the LDPC encode operation:
41   - ``RTE_BBDEV_LDPC_CRC_24B_ATTACH``: set to attach CRC24B to CB(s).
42   - ``RTE_BBDEV_LDPC_RATE_MATCH``: if set then do not do Rate Match bypass.
43   - ``RTE_BBDEV_LDPC_INTERLEAVER_BYPASS``: if set then bypass interleaver.
44   - ``RTE_BBDEV_LDPC_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data.
45   - ``RTE_BBDEV_LDPC_ENC_CONCATENATION``: concatenate code blocks with bit granularity.
46
47* For the LDPC decode operation:
48   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_CHECK``: check CRC24B from CB(s).
49   - ``RTE_BBDEV_LDPC_CRC_TYPE_24B_DROP``: drops CRC24B bits appended while decoding.
50   - ``RTE_BBDEV_LDPC_CRC_TYPE_24A_CHECK``: check CRC24A from CB(s).
51   - ``RTE_BBDEV_LDPC_CRC_TYPE_16_CHECK``: check CRC16 from CB(s).
52   - ``RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE``: provides an input for HARQ combining.
53   - ``RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE``: provides an input for HARQ combining.
54   - ``RTE_BBDEV_LDPC_ITERATION_STOP_ENABLE``: disable early termination.
55   - ``RTE_BBDEV_LDPC_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data.
56   - ``RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION``: supports compression of the HARQ input/output.
57   - ``RTE_BBDEV_LDPC_LLR_COMPRESSION``: supports LLR input compression.
58   - ``RTE_BBDEV_LDPC_HARQ_4BIT_COMPRESSION``: supports compression of the HARQ input/output.
59   - ``RTE_BBDEV_LDPC_SOFT_OUT_ENABLE``: set the APP LLR soft output.
60   - ``RTE_BBDEV_LDPC_SOFT_OUT_RM_BYPASS``: set the APP LLR soft output after rate-matching.
61   - ``RTE_BBDEV_LDPC_SOFT_OUT_DEINTERLEAVER_BYPASS``: disables the de-interleaver.
62
63* For the turbo encode operation:
64   - ``RTE_BBDEV_TURBO_CRC_24B_ATTACH``: set to attach CRC24B to CB(s).
65   - ``RTE_BBDEV_TURBO_RATE_MATCH``: if set then do not do Rate Match bypass.
66   - ``RTE_BBDEV_TURBO_ENC_INTERRUPTS``: set for encoder dequeue interrupts.
67   - ``RTE_BBDEV_TURBO_RV_INDEX_BYPASS``: set to bypass RV index.
68   - ``RTE_BBDEV_TURBO_ENC_SCATTER_GATHER``: supports scatter-gather for input/output data.
69
70* For the turbo decode operation:
71   - ``RTE_BBDEV_TURBO_CRC_TYPE_24B``: check CRC24B from CB(s).
72   - ``RTE_BBDEV_TURBO_SUBBLOCK_DEINTERLEAVE``: perform subblock de-interleave.
73   - ``RTE_BBDEV_TURBO_DEC_INTERRUPTS``: set for decoder dequeue interrupts.
74   - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_IN``: set if negative LLR input is supported.
75   - ``RTE_BBDEV_TURBO_DEC_TB_CRC_24B_KEEP``: keep CRC24B bits appended while decoding.
76   - ``RTE_BBDEV_TURBO_DEC_CRC_24B_DROP``: option to drop the code block CRC after decoding.
77   - ``RTE_BBDEV_TURBO_EARLY_TERMINATION``: set early termination feature.
78   - ``RTE_BBDEV_TURBO_DEC_SCATTER_GATHER``: supports scatter-gather for input/output data.
79   - ``RTE_BBDEV_TURBO_HALF_ITERATION_EVEN``: set half iteration granularity.
80   - ``RTE_BBDEV_TURBO_SOFT_OUTPUT``: set the APP LLR soft output.
81   - ``RTE_BBDEV_TURBO_EQUALIZER``: set the turbo equalizer feature.
82   - ``RTE_BBDEV_TURBO_SOFT_OUT_SATURATE``: set the soft output saturation.
83   - ``RTE_BBDEV_TURBO_CONTINUE_CRC_MATCH``: set to run an extra odd iteration after CRC match.
84   - ``RTE_BBDEV_TURBO_NEG_LLR_1_BIT_SOFT_OUT``: set if negative APP LLR output supported.
85   - ``RTE_BBDEV_TURBO_MAP_DEC``: supports flexible parallel MAP engine decoding.
86
87* For the FFT operation:
88   - ``RTE_BBDEV_FFT_WINDOWING``: flexible windowing capability.
89   - ``RTE_BBDEV_FFT_CS_ADJUSTMENT``: flexible adjustment of Cyclic Shift time offset.
90   - ``RTE_BBDEV_FFT_DFT_BYPASS``: set for bypass the DFT and get directly into iDFT input.
91   - ``RTE_BBDEV_FFT_IDFT_BYPASS``: set for bypass the IDFT and get directly the DFT output.
92   - ``RTE_BBDEV_FFT_WINDOWING_BYPASS``: set for bypass time domain windowing.
93
94* For the MLD-TS operation:
95   - ``RTE_BBDEV_MLDTS_REP``: set to repeat and reuse channel across operations.
96
97Installation
98------------
99
100Section 3 of the DPDK manual provides instructions on installing and compiling DPDK.
101
102DPDK requires hugepages to be configured as detailed in section 2 of the DPDK manual.
103The bbdev test application has been tested with a configuration 40 x 1GB hugepages.
104The hugepage configuration of a server may be examined using:
105
106.. code-block:: console
107
108   grep Huge* /proc/meminfo
109
110
111Initialization
112--------------
113
114When the device first powers up, its PCI Physical Functions (PF)
115can be listed through these commands for Intel vRAN Boost v2:
116
117.. code-block:: console
118
119   sudo lspci -vd8086:57c2
120
121The physical and virtual functions are compatible with Linux UIO drivers:
122``vfio`` (preferred) and ``igb_uio`` (legacy).
123However, in order to work the 5G/4G FEC device first needs to be bound
124to one of these Linux drivers through DPDK.
125
126
127Configure the VFs through PF
128~~~~~~~~~~~~~~~~~~~~~~~~~~~~
129
130The PCI virtual functions must be configured before working or getting assigned
131to VMs/Containers.
132The configuration involves allocating the number of hardware queues, priorities,
133load balance, bandwidth and other settings necessary for the device
134to perform FEC functions.
135
136This configuration needs to be executed at least once after reboot or PCI FLR
137and can be achieved by using the functions ``rte_acc_configure()``,
138which sets up the parameters defined in the compatible ``rte_acc_conf`` structure.
139
140
141Test Application
142----------------
143
144BBDEV provides a test application, ``test-bbdev.py`` and range of test data for testing
145the functionality of the device, depending on the device's capabilities.
146
147For more details on how to use the test application,
148see :ref:`test_bbdev_application`.
149
150
151Test Vectors
152~~~~~~~~~~~~
153
154In addition to the simple LDPC decoder and LDPC encoder tests,
155bbdev also provides a range of additional tests under the test_vectors folder,
156which may be useful.
157The results of these tests will depend on the device capabilities which may
158cause some test cases to be skipped, but no failure should be reported.
159
160
161Alternate Baseband Device configuration tool
162~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
163
164On top of the embedded configuration feature supported in test-bbdev using
165"- -init-device" option mentioned above, there is also a tool available
166to perform that device configuration using a companion application.
167The ``pf_bb_config`` application notably enables then to run bbdev-test
168from the VF and not only limited to the PF as captured above.
169
170See for more details: https://github.com/intel/pf-bb-config
171
172Specifically for the bbdev Intel vRAN Boost v2 PMD, the command below can be used
173(note that ACC200 was used previously to refer to VRB2):
174
175.. code-block:: console
176
177   pf_bb_config VRB2 -c ./vrb2/vrb2_config_vf_5g.cfg
178   test-bbdev.py -e="-c 0xff0 -a${VF_PCI_ADDR}" -c validation -n 64 -b 64 -l 1 -v ./ldpc_dec_default.data
179